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Vishay Siliconix
Document Number: 71337
31-Oct-00
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1
Design Guidelines for the Low-Noise
Low-Dropout Regulator--Si9181
Nitin Kalje
INTRODUCTION
This application note discusses the operation and features of
the Si9181, a 350-mA CMOS low-dropout (LDO), low-noise
voltage regulator. Providing very low ground current to extend
battery life, the Si9181 also offers superior line/load transient
response and ripple rejection. Designed to maintain regulation
while delivering currents from 0 mA to 600 mA, the Si9181
regulator also features an "out of regulation" error flag signal
and ON/OFF control input for complete shutdown.
The Si9181 was designed for applications requiring a regu-
lated voltage equal to or less than the voltage of the source or
battery, and requiring very low output noise. Such applications
include digital signal processors, baseband circuits, mixers, A-
to-D converters, or intermediate amplifiers. The Si9181's LDO
characteristics are determined by its voltage, ground current,
power-dissipation, peak current capability, noise and ripple re-
jection specifications. The Si9181 is designed to meet the cri-
teria for high quality on each of these determinants, and is
suitable for portable and noisesensitive appliances such as
cellular phones.
+
C
IN
2.2
m
F
V
IN
4
6
SD
8
ON
OFF
3
GND
ADJ
+
60 mV
5% V
REF
+
1.215 V
V
REF
1
C
NOISE
+
+
2.2
m
A
To V
IN
5
C
OUT
2.2
m
F
2
7
C
DELAY
0.1
m
F
R
EXT
V
OUT
ERROR
FIGURE 1.
350-mA CMOS LDO Regulator (Adjustable Output)
6 M
W
R
2
R
1
V
ADJ
U1
U2
U3
Q1
Q2
C
NOISE
S19181
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Document Number: 71337
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LDO OPERATION
Choosing the right series pass element for the regulator is key
to achieving low dropout voltages and high efficiency. LDO
regulators are functionally no different than variable resistance
series elements, where the voltage drop across the pass ele-
ment is equal to the input-to-output voltage differential. The
variable resistor can either be a bipolar transistor, controlled by
the base current, or a MOS transistor, which is controlled by
gate voltage. In bipolar transistors the collector current is con-
trolled by the base current, a process that contributes to a high-
er ground current, diminishing the efficiency of the regulator.
For CMOS LDOs the series pass element operates in two dif-
ferent regions depending upon the input voltage. If the input
voltage is significantly higher than output voltage, the power
MOSFET operates in the saturation region and acts as a con-
trollable current source. This drain current is a function of the
transconductance of the power MOSFET,
Gm
+
dI
D
dV
GS
, where
the gate voltage is set by the error amplifier. If the input voltage
decreases to (V
OUT
+ (R
ON
* I
OUT
)), the voltage regulator can-
not maintain a regulated output. If the input voltage falls below
this voltage, the p-channel power MOSFET enters the linear
region. In this linear region, the gate voltage changes with the
input voltage, and is not a function of the output or control volt-
age. All the circuits in the Si9181 are designed to operate with
inputs as low as 2 V and, on adjustable Si9181 regulators, out-
puts can be programmed as low as 1.5 V.
IV CHARACTERISTIC OF SI9181
The Si9181 uses a p-channel power MOSFET series element
that significantly reduces ground current. The Si9181 also fa-
cilitates higher peak current capabilities than solutions using
bipolar series elements, where the maximum current drawn is
limited by the base current. Because the Si9181 uses a p-
channel power MOSFET series element, the gate voltage con-
trols the drain current.
The maximum gate-to-source voltage (V
GS
) is the same as the
input voltage at any load or input to output voltage differential.
For regulator operation, the gate-to-source voltage should be
high enough to operate the p-channel MOSFET in the satura-
tion region. The available drain current is proportional to the
square of the difference between the applied gate voltage and
transistor threshold voltage. The Si9181 gate threshold is
0.8 V and needs minimum V
GS
equal to 1.8 V to produce the
600-mA peak current. The 600-mA peak current can be drawn
for at least 2 ms. The package can handle the power dissi-
pated during the peak current pulse period. The power han-
dling capability of Si9181 is enhanced by the low
junction-to-lead thermal resistance.
FIGURE 2. I-V Characteristic of P-Channel MOSFET
Saturation Region
Linear Region
I
DS
0
V
DS
V
GS1
V
GS2
V
GS3
POWER DISSIPATION/JUNCTION TEMPERATURE
The Si9181 is rated to deliver up to 600-mA peak current for
2 ms. The maximum load current is specified for continuous
operation and for finite pulse widths. Maximum allowable junc-
tion temperature, junction-to-ambient thermal impedance at a
thermal equilibrium, and the ambient temperature determine
the continuous current rating at a given input-to-output differ-
ential. The input voltage, p-channel power MOSFET transcon-
ductance, and the transient thermal impedance between
junction to lead are major issues for the peak current amplitude
and the pulse width. The maximum continuous power dissipa-
tion allows for a safe junction temperature and is calculated us-
ing the following equation:
P
D
+
V
IN
*
V
OUT
I
OUT
)
V
IN
I
GND
(1)
(2)
Efficiency
+
V
OUT
I
OUT
V
IN
I
OUT
)
I
GND
(3)
P
DMAX
+
150
*
T
A
q
JA
Where,
JA
= 120
_
C/W (All leads soldered to PC board on 1-oz
copper)
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Document Number: 71337
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PROTECTION FEATURES
Short circuit
In the event of a short circuit in the equipment powered by an
LDO, the Si9181 limits the maximum current to prevent dam-
age to the electronics. The peak current through the Si9181 is
typically limited to 800 mA during a continuous short circuit at
the output.
Over-Temperature
The Si9181 is designed with an over temperature protection
circuit to prevent thermal runaway in the p-channel power
MOSFET. If the temperature reaches 165
_
C, the internal con-
trol circuit shuts off the p-channel power MOSFET. The LDO
will remain disabled until the chip temperature drops below
145
_
C, and will re-engage automatically. The 20
_
C tempera-
ture difference avoids possible oscillation and reduces the av-
erage power delivery during fault conditions to reduce the risk
of damage.
LOOP COMPENSATION
For the stable operation of a closed loop electronic system,
such as a voltage regulator, the feedback loop needs to be
compensated to keep the total phase lag at less than 360
_
for a
signal having the total gain more than or equal to unity. The
phase lag includes the 180
_
phase change caused by the neg-
ative feedback.
The Si9181 equivalent circuit and its gain characteristic with
internal compensation is shown in Figure 3. The closed loop
has two low frequency poles. A low frequency pole (P
O
) is a
result of output capacitance C
OUT
and the channel length
modulation parameter
l
of the P-MOS. The location of this
pole changes with the load current, I
O
.
P
O
+
l
I
O
2
p
C
OUT
(4)
The second pole is introduced by the compensation capaci-
tance Cc, parasitic capacitance of the series pass element and
the error amplifier. The error amplifier output impedance
r
o
and the compensation capacitor along with the gate capaci-
tance of PMOS determine the location of the second pole P
p
.
The gate capacitance is low enough to be neglected here.
P
p
+
1
2
p
r
O
C
c
(5)
The Si9181 uses an internal zero to achieve a stable feedback
loop, eliminating the need to rely on the ESR value of the out-
put capacitors for a zero. The location of internal zero Z
c
is
changed to offset any effect of the load on the low frequency
pole P
O
. This internal zero also offers the freedom to use a
lowESR ceramic X5R or Y5V capacitor for lower noise.
Z
ESR
+
1
2
p
C
O
ESR
(6)
With the native compensation of the Si9181, a closedloop
bandwidth as high as 100 kHz can be achieved easily with a
phase margin no lower than 60
_
. (See Figure 4.
)
FIGURE 3. Loop Compensation
Gain
P
O
Z
c
Z
ESR
Frequency
Output V
O1
Ref
Input
Com
r
o
C
OUT
ESR
R
LOAD
Rc
Cc
P
P
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Document Number: 71337
31-Oct-00
60
40
20
0
20
40
60
100
1000
10000
100000
1000000
180
120
60
0
60
120
180
100
1000
10000
100000
1000000
FIGURE 4. Closed Loop Bandwidth
Frequency (Hz)
Gain (dB)
Phase
Phase (Deg)
Gain
FIGURE 5. Programmed Delay for Error
Signal
CH1 V
OUT
(Pin 5)
CH2 Error (Pin 7)
CH3 V
IN
(Pin 4)
CH4 C
DELAY
(Pin 2)
C
DELAY
= 0.1
m
F
C
IN
= 2.2
m
F, C
OUT
= 2.2
m
F, I
LOAD
= 150 mA
2V/div
2V/div
2V/div
2V/div
ERROR SIGNAL WITH PROGRAMMABLE DELAY
The Si9181 is provided with an ERROR pin which can be used
as a high-going enable or power-good signal to activate the
electronic equipment once the output is within 5% of the set
value. When output voltage drops below 95% of its set level,
the ERROR pin can positively disable the electronics before
the low-going supply cripples the circuit. The ERROR signal
required to wake up the electronics can also be delayed with
respect to the output by adding a small capacitor at C
DELAY
(pin 2). The ERROR output is a high slewrate open drain and
needs an external pull-up resistor.
The C
DELAY
capacitor is fully discharged through U2 when the
circuit is OFF or when the output is below the set power-good
threshold (0.95 V
OUT
). (See Figure 1.) Once the output goes
above the power-good trip threshold, the U2 output switches to
a high impedance state and C
DELAY
charges with a 2.2-
m
A
(typ) constant current. U3 switches Q2 off at 1.215 V across
the C
DELAY
capacitor and the ERROR output is pulled high by
R
EXT
(Figure 5).
C
DELAY
+
1.81
10
*
6
t
DELAY
(7)
SHUTDOWN
The Si9181 is provided with an ON/OFF control pin (named
SD) that opens and closes the internal power MOSFET switch
and controls the total current drawn by the entire circuit. The
current is less than 1
m
A, reducing the drain on the battery in
standby mode and increasing standby time. While a low at the
SD pin opens the switch, a high at the SD pin enables the regu-
lator operation. This allows the Si9181 to be used as a high-
current simple disconnect switch that works in conjunction with
the regulated output. It is recommended that the user connect
the SD to the input V
IN
when not in use.
INPUT/OUTPUT CAPACITOR SELECTION
The circuit stability and output voltage during line and load step
changes dominate the selection criteria of input and output ca-
pacitors. A higher step load current at the output demands
higher capacitance with a lower ESR value at the output. An
input bypass capacitor is required in applications involving
long traces between the source and LDO. The input capacitor
should be at least equal to or greater than the output capacitor
for proper operation. A 2.2-
m
F to 10-
m
F ceramic capacitor with
a Y5V dielectric is recommended, and an X5R dielectric is rec-
ommended for better temperature characteristics. The Si9181
requires only a small output capacitor because of the high
closed loop bandwidth of 100 kHz or more. Also, the freedom
to use a very lowESR ceramic capacitor reduces the form
factor further for greater performance.
D
V
+
I
STEP
t
RESPONSE
C
OUT
)
I
STEP
ESR
(8)
where:
I
STEP
= Output load step (A)
ESR = ESR of Output capacitor (W)
t
RESPONSE
= Response time of the regulator (s)
t
RESPONSE depends on the unity gain bandwidth and the phase
margin of the closed loop.
AN734
Vishay Siliconix
Document Number: 71337
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DYNAMIC LOAD RESPONSE
The ability to use a low ESR ceramic capacitor at the output of
the Si9181 helps reduce the glitch during the high slew-rate
step load, while the high closed loop bandwidth reduces the re-
covery time. With a 2.2-
m
F ceramic capacitor at the output, the
maximum deviation observed in the output is 30 mV, with bet-
ter than 3-
m
S recovery time. Refer to the Figures 5 and 6. The
recovery time of the output from overshoot during the load re-
moval is the time required to discharge the output capacitor.
The recovery time depends on the voltage overshoot, capaci-
tor and the load current.
Figure 5. Load Transient Response-1
I
LOAD
100 mA/div
V
OUT
10 mV/div
V
OUT
= 3.3 V
C
IN
= 2.2
m
F
C
OUT
= 2.2
m
F
I
LOAD
= 1 to 150 mA
t
rise
= 2
m
sec
Figure 6. Load Transient Response-2
V
OUT
= 3.3 V
C
IN
= 2.2
m
F
C
OUT
= 2.2
m
F
I
LOAD
= 150 to 1 mA
t
fall
= 2
m
sec
5.00
m
s/div
I
LOAD
100 mA/div
V
OUT
10 mV/div
5.00
m
s/div
PCB LAYOUT
The component placement around the LDO should be done
carefully to achieve good dynamic line and load response. The
input and noise capacitor should be kept close to the LDO. The
rise in junction temperature depends on how efficiently the
heat is carried away from the junction to ambient. The junction
to lead thermal impedance is a characteristic of the package
and is fixed. The thermal impedance between lead to ambient
can be reduced by increasing the copper area on PCB. In-
crease the input, output and ground trace area to reduce the
junction-to-ambient thermal impedance.
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