VITESSE
SEMICONDUCTOR CORPORATION
Page 1
4/10/00
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC6511
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
G52311-0, Rev. 2.0
Draf
t Cop
y
Features
General Description
The VSC6511 multi function SMPTE-292M compatible IC with Serializer, Deserializeror, or Deserializer
with reclocker modes which operate at 1.485Gb/s. As a Serializer, 20-bits of data (D19:0) are latched into the
part on the rising edge of REFCLK then scrambled and serialized out SDO0/SDO0 and/or SDO1/SDO1. An
optional CRC Generator may be enabled. As a Deserializer, serial data on SDI/SDI is recovered, de-scrambled
and deserialized onto D[19:0]. Frame alignment on SAV/EAV, line detection and frame detection outputs are
provided. As a Deserializer with reclocker, the device functions as ain the deserializer mode above and serial
data on SDI/SDI is recovered and retransmitted on SDO0/SDO0 and/or SDO1/SDO1.
VSC6511 Block Diagram
Compliant with SMPTE-292M @ 1.485Gb/s
Multiple Functions: Serializer, Deserializer,
and Deserializer with Reclocker
20 Bit TTL Interface @ 74.25 MHz
Scrambler / Descrambler with ENABLE
CRC Generator/Checker with ENABLE
Data Framer aligns data and provides TRS on
SAV/EAV events
Clock Multiplier and Recovery Units
2 or 4 configurable 75ohm cable driver o/ps
3.3V, Low power -- 700-1500mW typical
64-pin, 10x10x1.0mm Exposed Pad TQFP
IP
IN
Clock/
Recovery
REFCLK
Clock
Multiply
1.485 GHz
74.25 MHz
x20
RCLK
SCREN
1.485 GHz
D[19:0]
SDO0
SDO0
SIGDET
OE1
/20
Serializer
Scrambler
D Q
ISET0
SDO1
SDO1
ISET1
MODE0
Unit
MODE1
CRC Gen
CABLE DRIVER
OUTPUTS
CRC Check
Deserializer
D Q
OE0
CRC
/20
FRAME
Framer
HANC
LINE
1001
NRZI Decoder
Descrambler
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
VSC6511
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
4/10/00
G52311-0, Rev 2.0
Draf
t Cop
y
Functional Description
The VSC6511 is a multifunction SMPTE-292M device which can be configured for different modes of
operation: Serializer, Deserializer, or Deserializer/Reclocker. Only one mode is available at a time. A discussion
of the individual building blocks of the device will be followed with specific configurations.
Clock Multiplier Unit (CMU)
The CMU generates the internal 1.485 GHz baud rate clock from the 74.25 MHz TTL REFCLK input. The
rising edges of the REFCLK are used by a PLL which multiplies the frequency by a factor of 20. This internal
baud rate clock is used by the Serializer, Deserializer and Reclocker. An off-chip 0.1uF capacitor sets the loop
bandwidth of the CMU. REFCLK should be a high quality, low jitter signal with sharp rise times in order to
minimize the amount of jitter transferred from the REFCLK through the CMU to the serializer. This optimizes
the signal quality at the output of the serializer.
A secondary function of the CMU is to divide the baud rate clock by 20 to produce an internal 74.25 MHz
clock which is frequency locked and phase aligned to REFCLK. This internal clock is used to latch the 20-bit
data bus D[19:0] into the input register of the Serializer.
REFCLK is also buffered onto the RCLK output when in Serializer or Reclocker mode. This allows multi-
ple devices to be daisy-chained in order to simplify REFCLK distribution to an array of devices.
CRC Generator
The twenty bits of transmit data from the input register is fed into a CRC Generator which calculates the
CRC and substitutes the value into the proper location within the video line. The CRC polynomial is CRC(X)=
(X
18
+ X
5
+ X
4
+ 1). A controller monitors SAV/EAV position and uses this to control the CRC generator and
insertion of the CRC result into the line. The CRC Generator is enabled only in Serializer Mode when CRC is
HIGH. In other modes, or if CRC is LOW, the CRC Generator is disabled and powered down. CRC is a bidi-
rectional pin.
Scrambler and NRZI Encoder
The twenty bits out of the CRC Generator are sent to the parallel Scrambler where the data is scrambled and
NRZI encoded using the combined generator polynomial of G(x)=(x
9
+ x
4
+1)(x+1). Scrambling is enabled
only when in Serializer Mode if SCREN is HIGH. Scrambling is disabled when SCREN is LOW and in other
modes.
Serializer
The data from the Scrambler is converted from 20-bits at 74.25 Mb/s to 1 bit at 1.485 Gb/s by the Serializer
with D0 being transmitted first. Two differential PECL-style serial outputs are provided for transporting the
1.485 Gb/s signal. These outputs SDO0/SDO0 and SDO1/SDO1 are supplied data from the serializer (in Serial-
izer mode) or the CRU of the Reclocker (in Deserializer/Reclocker mode). Each output, SDO0 and SDO1,
have independent TTL inputs, OE0 and OE1, which when HIGH enable the outputs and when LOW disable the
outputs. When disabled, the output buffer will be powered down and both legs will float HIGH.
Each output is compliant with the SMPTE-292M cable driver specification when driving 75 ohm loads. In
this application, a TBD ohm resistor should be connected from the ISET0/ISET1 pin to ground in order to con-
trol the current in the differential output amplifier. By lowering the ISET resistor, higher output swings may be
realized.
VITESSE
SEMICONDUCTOR CORPORATION
Page 3
4/10/00
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC6511
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
G52311-0, Rev. 2.0
Draf
t Cop
y
Serial Input
The differential PECL-style input, SDI/SDI, is the input source for 1.485 Gb/s SMPTE-292M data in the
Deserializer and Reclocker modes. This input is ignored in Serializer mode.
Clock Recovery Unit
The serial data on the SDI/SDI input is sent to the digital Clock Recovery Unit (CRU) which extracts the
clock and retimes the data. This digital CRU is completely monolithic and requires no external components.
Furthermore, it automatically locks onto data when present and locks to REFCLK when data is not present. This
eliminates the need for the system to control the CRU. The CRU is enabled only in the Deserializer and Deseri-
alizer/Reclocker modes.
Deserializer
The reclocked serial bit stream is deserialized into a 20-bit parallel character. D0 is serially received prior to
D1. The VSC6511 provides a TTL recovered clock, RCLK at one twentieth of the serial baud rate. This clock is
generated by dividing down the high-speed clock from the CRU which is phase locked to the serial data. The
deserializer is enabled only in the Deserializer and Deserializer/Reclocker modes.
If serial input data is not present, or does not meet the required baud rate, the VSC6511 will continue to
produce a recovered clock so that downstream logic may continue to function. The RCLK output frequency
under these circumstances will differ from their expected frequency by less than +1%.
Descrambler and NRZI Decoder
The VSC7152 contains a descrambler/NRZI Decoder which processes the recovered serial data and out-
puts unscrambled and NRZI decoded serial data from the deserializer. The serial scrambled data is descrambled/
NRZI decoded assuming data has been scrambled/NRZI encoded with the following combined generator poly-
nomial: G(x)=(x
9
+x
4
+1)(x+1). Descrambling is enabled with the SCREN input is HIGH and disabled when
LOW. The descrambler is enabled only in the Deserializer mode.
CRC Checker
The 20-bit data from the Descrambler is sent to the CRC Checker where a running CRC checksum is con-
tinuously calculated. As 20-bit data is sent out of the chip, the CRC output pin is asserted if the checksum did
not meet the value expected. This error is asserted from the first CRC Error until the end of the line. A controller
monitors the 20-bit data out of the serializer for SAV/EAV frames in order to control the CRC Checker. The
CRC Checker is enabled only in Deserializer and Deserializer/Reclocker modes.
Frame Aligner
The VSC6511 monitors the serial data stream for SAV/EAV characters. These characters should be located
within each line of video data. If SAV/EAV is not detected within the period of one line, the Framer sends a sig-
nal to the Deserializer to shift the data one bit. The Framer then looks for SAV/EAV and the process repeats
until properly detected. Without these patterns, serial data is not aligned in any way with the parallel outputs.
The Framer outputs a once-per-line (LINE), Horizontal ANCilliary period (HANC), 1.001/1.000 output (1.001)
and a once-per-frame (FRAME) signal indicating the detection of the proper synchronization pulse in the data.
Framing is enabled only in Deserializer mode.
The Frame Aligner also outputs the LINE, FRAME and HANC outputs signals. The timing of these signals
is indicated below.
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
VSC6511
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
4/10/00
G52311-0, Rev 2.0
Draf
t Cop
y
Table 1: Frame Aligner Output Timing
D[19:0] Databus
As mentioned previously, in Serializer mode D[19:0] is configured as a input. In Deserializer mode,
D[19:0] is configured as an output.
Application Information
The VSC6511 cable driver output is intended to fully comply with the SMPTE-292M cable driver specifi-
cations. This includes an 800mV swing and a return loss of more than 15dB. The circuit shown below shows
how to connect the output of the VSC6511 to the 75 ohm cable and downstream device. The output of the
VSC6511 is actually 1200mV. The output termination circuit shown below attenuates the output signal to
800mV and ensures a return loss better than -15dB. The ISET resistor is 1.78K
D10-19
D0-9
LINE
FRAME
HANC
CRCERR
AC
T
I
V
E
VI
DE
O
DATA
DATA
0
0
0
0
---
---
0
0
0
0
DATA
DATA
0
0
0
0
EA
V
3FF
3FF
0
0
0
0
000
000
0
0
0
0
000
000
0
0
0
0
XYZ
XYZ
0
0
0
0
LINE
LN0
LN0
0
0
0
0
LN1
LN1
1
1*
0
0
CRC
CRC0
CRC0
0
0
0
0
CRC1
CRC1
0
0
0
0 or 1
HORIZ
B
L
ANK
DATA
DATA
0
0
1
0
---
---
0
0
1
0
DATA
DATA
0
0
1
0
SA
V
3FF
3FF
0
0
0
0
000
000
0
0
0
0
000
000
0
0
0
0
XYZ
XYZ
0
0
0
0
AC
T
I
V
E
VIDEO
DATA
DATA
0
0
0
0
DATA
DATA
0
0
0
0
---
---
0
0
0
0
* FRAME is HIGH only if LN0/LN1 indicates the first line of a frame.
** CRCERR is HIGH only during CRC1 if the CRC is incorrect.
VITESSE
SEMICONDUCTOR CORPORATION
Page 5
4/10/00
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC6511
Deserializer/Reclocker at 1.485Gb/s
SMPTE-292M Serializer, Deserializer, and
G52311-0, Rev. 2.0
Draf
t Cop
y
Figure 1: High Speed Interconnect Example (Differential)
Figure 2: High Speed Interconnect Example (Single Ended)
6511
V
DD
75
75 ohm Cables
75
75
75
V
DD
1.78K
ISETx
NOTE: All resistors are 1%
10nH
10nH
V
SS
WARNING: SUBJECT TO CHANGE
6511
V
DD
75
75 ohm Coax
75
NOTE: All resistors are 1%
10nH
Optional use of external Voltage Reference provides tighter swing tolerance
1.78K
ISETx
V
SS
75
75
V
DD
10nH
75
V
DD
37.5
V
DD
or
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