V
EL
OC
ITY
TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 1
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
General Description
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard
pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK
frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit
(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty
clocks. The VSC7123 receiver detects "Comma" characters for frame alignment. An analog/digital signal
detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for
InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher
performance, lower cost replacement for the VSC7125 and VSC7135.
VSC7123 Block Diagram
802.3z Gigabit Ethernet-Compliant
1.25 Gb/s Transceiver
ANSI X3T11 Fibre Channel-Compliant
1.0625 Gb/s Transceiver
0.98 to 1.36 Gb/s Full-Duplex Operation
10-Bit TTL Interface for Transmit and
Receive Data
Automatic Lock-to-Reference
RX Cable Equalization
Analog/Digital Signal Detection
JTAG Access Port for Testability
Single +3.3V Supply, 650mW Typical
Packages: 64-Pin 10mm and 14mm PQFP and
10mm TQFP
RX+
RX-
Q D
Serial to
Parallel
Clock
Recovery
10
Comma
R(0:9)
COMDET
ENCDET
T(0:9)
x10 Clock
Multiply
Parallel
to Serial
TX+
TX-
EWRAP
20
RCLK
10
10
2:1
RCLKN
REFCLK
Signal
Detect
Q D
Q
D
Detect
SIGDET
D Q
D Q
NOT SHOWN: JTAG Boundary Scan
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OC
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TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 2
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Functional Description
Clock Synthesizer
The VSC7123 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to
achieve a baud rate clock between 0.98GHz and 1.36GHz. The on-chip Phase Lock Loop (PLL) uses a single
external 0.1
F capacitor to control the Loop Filter.
Serializer
The VSC7123 accepts TTL input data as a parallel 10-bit character on the T(0:9) bus, which is latched into
the input register on the rising edge of REFCLK. This data is serialized and transmitted on the TX PECL
differential outputs at a baud rate that is 10 times the frequency of the REFCLK, with bit T0 transmitted first.
User data should be encoded using 8B/10B block code or equivalent.
Transmission Character Interface
An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the
VSC7123 corresponds to a transmission character. This mapping is illustrated in Figure 1.
Figure 1: Transmission Order and Mapping of an 8B/10B Character
Clock Recovery
The VSC7123 accepts differential high-speed serial inputs on the RX+/RX- pins, extracts the clock and
retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol
Interference which may be present in the incoming data. The serial bit stream should be encoded to provide DC
balance and limited run length by an 8B/10B encoding scheme. The Clock Recovery Unit is completely
monolithic and requires no external components. For proper operation, the baud rate of the data stream to be
recovered should be within +200 ppm of 10 times the REFCLK frequency. For example, Gigabit Ethernet
systems would use 125MHz oscillators with a +100ppm accuracy resulting in +200 ppm between VSC7123
pairs.
Deserializer
The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7123 provides
complementary TTL recovered clocks, RCLK and RCLKN, which are 1/20
th
of the serial baud rate. The clocks
are generated by dividing down the high-speed recovered clock, which is phase-locked to the serial data. The
First Data Bit Transmitted
Last Data Bit Transmitted
Parallel Data Bits
8B/10B Bit Position
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
j
h
g
f
i
e
d
c
b
a
Comma Character
X
X
X
1
1
1
1
1
0
0
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OC
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TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 3
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
serial data is retimed, deserialized and output on R(0:9). The parallel data will be captured by the adjoining
protocol logic on the rising edges of RCLK and RCLKN.
If serial input data is not present or does not meet the required baud rate, the VSC7123 will continue to
produce a recovered clock, allowing downstream logic functionality to continue. Under these circumstances,
the RCLK/RCLKN output frequency differ from its expected frequency by no more than +1%.
Word Alignment
The VSC7123 provides 7-bit comma character recognition and data word alignment. Word synchronization
is enabled by asserting ENCDET HIGH. When synchronization is enabled, the receiver examines the recovered
serial data for the presence of the "Comma" character. This pattern is "0011111XXX", where the leading zero
corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data
character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and
K28.7, which are defined for synchronization purposes. Improper alignment of the comma character is defined
as any of the following conditions:
1) The comma is not aligned within the 10-bit transmission character such that R0...R6 = "0011111."
2) The comma straddles the boundary between two 10-bit transmission characters.
3) The comma is properly aligned but occurs in the received character presented during the rising edge of
RCLK rather than RCLKN.
When ENCDET is HIGH and an improperly aligned comma is encountered, the recovered clock is
stretched (never slivered) so that the comma character and recovered clocks are properly aligned to R(0:9). This
results in proper character and word alignment. When the parallel data alignment changes in response to a
improperly aligned comma pattern, some data which would have been presented on the parallel output port may
be lost. Additionally, the first Comma pattern may also be lost or corrupted. Subsequent data will be output
correctly and properly aligned. When ENCDET is LOW, the current alignment of the serial data is maintained
indefinitely, regardless of data pattern.
When encountering a comma character, COMDET is driven HIGH. The COMDET pulse is presented
simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The
COMDET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of
RCLKN. Functional waveforms for synchronization are given in Figure 2 and Figure 3. Figure 2 shows the case
when a comma character is detected and no phase adjustment is necessary. Figure 2 illustrates the position of
the COMDET pulse in relation to the comma character on R(0:9). Figure 3 shows the case where the K28.5 is
detected, but it is misaligned so a change in the output data alignment is required. Note that up to three
characters prior to the comma character may be corrupted by the realignment process.
V
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OC
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TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 4
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 2: Detection of a Properly Aligned Comma Character
Figure 3: Detection
TChar: 10-bit transmission character
COMDET
R(0:9)
RCLK
RCLKN
K28.5 TChar TChar TChar
COMDET
Receiving Two Consecutive K28.5+TChar Transmission Words
K28.5 TChar TChar TChar
K28.5
TChar
Potentially Corrupted
R(0:9)
RCLK
RCLKN
Clock Stretching
TChar: 10-bit transmission character
V
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OC
ITY
TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 5
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Signal Detection
The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre
Channel or Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determine
if the incoming signal contains valid data. SIGDET is updated every four RCLKs. If during the current period,
all the four criteria are met, SIGDET will be HIGH during the next 4 RCLK period. If during the current period,
any of the four criteria is not met, SIGDET will be LOW during the next 4 RCLK period.
1)
Analog transition detection is performed on the input to verify that the signal swings are of adequate
amplitude. The RX+/- input buffer contains a differential voltage comparator which will go HIGH if the
differential peak-to-peak amplitude is greater than 400mV or LOW if under 200mV. If the amplitude is
between 200mV and 400mV, the output is indeterminate.
2) Data on R(0:9) is monitored for all zeros (0000000000). If this pattern is encountered during the current
RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.
3)
Data on R(0:9) is monitored for all ones (1111111111). If this pattern is encountered during the current
RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.
4)
Data on R(0:9) is monitored for K28.5- (0011111010). Unlike previous patterns, the interval during which
a K28.5- must occur is 64K+24 10-bit characters in length. Valid Fibre Channel or Gigabit Ethernet data
will contain a K28.5- character during any period of this length. If a K28.5- is not detected during the
monitoring period, SIGDET will go LOW during the next period.
The behavior of SIGDET is affected by EWRAP and ENCDET as shown in Table 1.
Table 1: Signal Detect Behavior
Note: COMDET, RCLK, RCLKN and R(0:9) are unaltered by SIGDET.
JTAG Access Port
A JTAG Access Port is provided to assist in board-level testing. Through this port, most pins can be
accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this
device is available in "VSC7123/VSC7133 JTAG Access Port Functionality."
EWRAP
ENCDET
COMDET
Transition
Detect
All Zeros/
All Ones
K28.5
Presence
Mode
0
0
Disabled
Enabled
Enabled
Enabled
Normal
0
1
Enabled
Enabled
Enabled
Disabled
SIGDET ignores commas
1
0
Disabled
Enabled
Disabled
Disabled
Rollback
1
1
Enabled
Enabled
Disabled
Disabled
Loopback
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TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 6
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 4: Transmit Timing Waveforms
Table 2: Transmit AC Characteristics
Parameters
Description
Min
Typ
Max
Units
Conditions
T
1
T(0:9) Setup time to the rising
edge of REFCLK
1.5
--
--
ns
Measured between the valid data
level of T(0:9) to the 1.4V point
of REFCLK.
T
2
T(0:9) hold time after the rising
edge of REFCLK
1.0
--
--
ns
T
SDR
,T
SDF
TX+/TX- rise and fall time
--
--
300
ps
20% to 80%, 50
load to
V
DD
-2.0.
T
LAT
Latency from rising edge of
REFCLK to T0 appearing on
TX+/TX-
8bc
--
8bc+
4ns
ns
bc = Bit clocks
ns = Nano second
Transmitter Output Jitter Allocation
RJ
Random jitter (RMS)
--
5
8
ps.
Measured at SO+/-, 1 sigma
deviation of 50% crossing point.
DJ
Serial data output deterministic
jitter (pk-pk)
--
30
80
ps.
IEEE 802.3Z Clause 38.68,
tested on a sample basis.
Data Valid
T(0:9)
T
1
T
2
REFCLK
Data Valid
Data Valid
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OC
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TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 7
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 5: Receive Timing Waveforms
Table 3: Receive AC Characteristics
NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3.
Parameters
Description
Min.
Max.
Units
Conditions
T
1
TTL Outputs Valid prior to
RCLK/RCLKN rise
4.0
3.0
--
--
ns
At 1.0625Gb/s
At 1.25Gb/s
T
2
TTL Outputs Valid after
RCLK or RCLKN rise
3.0
2.0
--
--
ns
At 1.0625Gb/s
At 1.25Gb/s
T
3
Delay between rising edge of
RCLK to rising edge of
RCLKN
10 x T
RX
-500
10 x T
RX
+500
ps
T
RX
is the bit period of the
incoming data on Rx.
T
4
Period of RCLK and
RCLKN
1.98 x
T
REFCLK
2.02 x
T
REFCLK
ps
Whether or not locked to
serial data.
T
R
, T
F
R(0:9), COMDET, SIGDET,
RCLK and RCLKN rise and
fall time
--
2.4
ns
Between V
IL(MAX)
and
V
IH(MIN)
, into 10pf load.
R
LAT
Latency from RX to R(0:9)
12 bc + 1 ns
13 bc + 9 ns
bc
ns
bc = bit clock
ns = nano second
T
LOCK
(1)
Data acquisition lock time
--
1400
bc
8B/10B IDLE pattern.
bc = bit clocks
RCLK
R(0:9)
RCLKN
T
2
T
3
Data Valid
Data Valid
T
1
T
4
Data Valid
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TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 8
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 6: REFCLK Timing Waveforms
Table 4: Reference Clock Requirements
Parameter
Description
Min
Max
Units
Conditions
FR
Frequency Range
98
136
MHz
Range over which both transmit and
receive reference clocks on any link may
be centered.
FO
Frequency Offset
-200
200
ppm
Maximum frequency offset between
transmit and receive reference clocks on
one link.
DC
REFCLK duty cycle
35
65
%
Measured at 1.5V
T
R
,T
F
REFCLK rise and fall time
--
1.5
ns
Between V
IL(MAX)
and V
IH(MIN)
REFCLK
V
IL(MAX)
V
IH(MIN)
T
L
T
H
T
R
T
F
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OC
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TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 9
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 7: Parametric Measurement Information
Serial Input Rise and Fall Time
TTL Input and Output Rise and Fall Time
TTL AC Output Load
Receiver Input Eye Diagram Jitter Tolerance Mask
Serial Output Load
T
R
T
F
80%
20%
T
R
T
F
V
IH(MIN)
V
IL(MIN)
10pF
Z
0
= 75W
50 or 75W
V
DD
2.0V
Bit Time
24% Minimum Eye Width%
Amplitude
Parametric Test Load Circuit
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TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 10
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 8: Input Structures
INPUT
INPUT
High-Speed Input (RX+/RX-)
V
DDD
GND
TTL Inputs (not REFCLK)
INPUT
GND
V
DDD
3K
V
DDP
GND
V
DDD
TX+
TX-
High-Speed Outputs (TX+/-)
3K
4K
4K
V
DDT
V
SST
OUTPUT
TTL Outputs
REFCLK
REFCLK TTL Input
V
DD
GND
+3.3 V
12.6K
12.6K
9.3K
9.3K
V
SSD
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OC
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TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 11
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
DC Characteristics
(over recommended operating conditions)
NOTE: (1) Refer to Application Note, AN-37, for differential measurement techniques.
Parameters
Description
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH voltage (TTL)
2.4
--
--
V
I
OH
= 1.0 mA
V
OL
Output LOW voltage (TTL)
--
--
0.5
V
I
OL
= +1.0 mA
V
IH
Input HIGH voltage (TTL)
2.0
--
5.5
V
5V Tolerant Inputs
V
IL
Input LOW voltage (TTL)
0
--
0.8
V
--
I
IH
Input HIGH current (TTL)
--
50
500
A
V
IN
=
2.4V
I
IL
Input LOW current (TTL)
--
--
-500
A
V
IN
= 0.5V
V
OUT75
(1)
TX output differential peak-
to-peak voltage swing
1200
--
2200
mVp-p
75
to V
DD
2.0V
(TX+) - (TX-)
V
OUT50
(1)
TX output differential peak-
to-peak voltage swing
1000
--
2200
mVp-p
50
to V
DD
2.0V
(TX+) - (TX-)
V
IN
(1)
RX Input differential peak-
to-peak input sensitivity
300
--
2600
mVp-p
Internally biased to V
DD
/2
(RX+) - (RX-)
V
DD
Supply voltage
3.14
--
3.47
V
3.3V5%
P
D
Power dissipation
--
650
900
mW
Outputs open,
V
DD
=
V
DD
max
I
DD
Supply current (all supplies)
--
190
260
mA
Outputs open, Case temp =
95
o
C, V
DD
= V
DD
max
I
DDA
Analog supply current
--
--
100
mA
V
DDA
=
V
DDA
max
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TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 12
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Absolute Maximum Ratings
(1)
Power Supply Voltage, (V
DD
)
................................................................................................................
0.5V to +4V
DC Input Voltage (PECL inputs)
................................................................................................
0.5V to V
DD
+0.5V
DC Input Voltage (TTL inputs)
...........................................................................................................
0.5V to +5.5V
DC Output Voltage (TTL outputs)
............................................................................................
0.5V to V
DD
+ 0.5V
Output Current (TTL outputs) .................................................................................................................... +50mA
Output Current (PECL outputs)................................................................................................................... +50mA
Case Temperature Under Bias
..........................................................................................................
55
o
C to +125
o
C
Storage Temperature
..........................................................................................................................
65
o
C to +150
o
C
Recommended Operating Conditions
Power Supply Voltage, (V
DD
) ................................................................................................................+3.3V+5%
Operating Temperature Range ............................................................. 0
o
C Ambient to +95
o
C Case Temperature
Note: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing
permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended peri-
ods may affect device reliability.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC7123 is rated to the following
ESD voltages based on the human body and charge device models:
1. All pins are rated at or above 1000V (charge device model).
2. All pins are rated at or above 2000V (human body model).
V
EL
OC
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TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 13
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Package Pin Descriptions
Figure 9: Pin Diagram
Table 5: Pin Identifications
Pin #
Name
Description
2,3,4,6
7,8,9,11
12,13
T0,T1,T2,T3
T4,T5,T6,T7
T8,T9
INPUTS - TTL:
10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of
REFCLK. The data bit corresponding to T0 is transmitted first.
22
REFCLK
INPUT - TTL:
This rising edge of this clock latches T(0:9) into the input register. It also provides the
reference clock, at one tenth the baud rate to the PLL.
T5
TD
O
V
DDD
V
DD
T
RC
L
K
N
RC
L
K
V
SS
T
T4
V
DDD
T7
T8
T9
V
SS
D
RX
-
V
SS
D
V
DD
D
V
DDD
V
DD
P
TX
+
TCK
TR
STN
R6
R5
COMDET
R4
V
DDT
R7
R8
T2
V
DDD
T3
V
SS
D
R2
V
SSD
TDI
V
SST
C
AP1
EN
C
D
ET
V
DD
A
T6
CAP0
V
SSD
V
SSA
EW
R
A
P
RE
F
C
L
K
V
DDD
V
DDD
V
SS
D
SI
GD
ET
R9
R3
R1
R0
V
SST
N/C
V
DDT
V
DD
P
TX
-
T1
T0
V
DD
D
V
SS
D
TM
S
RX
+
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
63
61
59
57
55
53
51
49
33
35
37
39
41
43
45
47
(Top View)
VSC7123
V
EL
OC
ITY
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 14
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
62, 61
TX+, TX-
OUTPUTS - Differential PECL (AC-coupling recommended):
These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is
HIGH, TX+ is HIGH and TX- is LOW.
45,44,43,41
40,39,38,36
35,34
R0,R1,R2,R3
R4,R5,R6,R7
R8,R9
OUTPUTS - TTL:
10-bit received character. Parallel data on this bus is clocked out on the rising edges of
RCLK and RCLKN. R0 is the first bit received on RX+/RX-.
19
EWRAP
INPUT - TTL:
LOW for normal operation. When HIGH, an internal loopback path from the transmitter to
the receiver is enabled. TX+ is held HIGH and TX- is held LOW.
54, 52
RX+, RX-
INPUTS - Differential PECL (AC-coupling recommended):
The serial receive data inputs selected when EWRAP is LOW. Internally biased to VDD/2,
with 3.3K
resistors from each input pin to VDD and GND.
31, 30
RCLK,
RCLKN
OUTPUT - Complementary TTL:
Recovered clocks derived from 1/20
th
of the RX+/- data stream. Each rising transition of
RCLK or RCLKN corresponds to a new word on R(0:9).
24
ENCDET
INPUT - TTL:
Enables COMDET and word resynchronization when HIGH. When LOW, keeps current
word alignment and disables COMDET.
47
COMDET
OUTPUT - TTL:
This output goes HIGH for half of an RCLK period to indicate that R(0:9) contains a comma
character (`0011111XXX'). COMDET will go HIGH only during a cycle when RCLKN is
rising. COMDET is enabled by ENCDET being HIGH.
26
SIGDET
OUTPUT - TTL
SIGnal DETect. This output goes HIGH when the RX input contains a valid Fibre Channel or
Gigabit Ethernet signal. A LOW indicates an invalid signal.
16, 17
CAP0, CAP1
ANALOG: Differential capacitor for the CMU's VCO, 0.1
F nominal.
49
TCK
INPUT - TTL: JTAG clock input. Not normally connected.
48
TDI
INPUT - TTL: JTAG data input. Not normally connected.
55
TMS
INPUT - TTL: JTAG mode select input. Normally tied to V
DDD
56
TRSTN
INPUT - TLL: JTAG reset input. Tie to V
SSD
for normal operation.
27
TDO
OUTPU - TTL: JTAG data output. Normally tri-stated.
18
VDDA
Analog Power Supply
15
VSSA
Analog Ground
5,10,20,23
28,50,57,59
VDDD
Digital Logic Power Supply
1,14,21,25
51,58,64
VSSD
Digital Logic Ground
29, 37, 42
VDDT
TTL Output Power Supply
32, 33, 46
VSST
TTL Output Ground
60,63
VDDP
PECL I/O Power Supply
53
N/C
No internal connection
Pin #
Name
Description
V
EL
OC
ITY
TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 15
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Package Information: 64-pin PQFP
64
49
1
48
33
32
17
G
F
I
H
16
10
o
TYP
10
0
TYP
A
K
A2
0.102 MAX. LEAD
COPLANARITY
0.17 MAX.
A
0.25
J
0
o
- 8
o
0.25 MAX.
E
0.30 RAD. TYP.
0.20 RAD. TYP.
STANDOFF
Item
10mm
14mm
Tolerance
A
2.45
2.35
MAX
A2
2.00
2.00
+0.10/-0.05
E
0.22
0.35
0.05
F
13.20
17.20
0.25
G
10.00
14.00
0.10
H
13.20
17.20
0.25
I
10.00
14.00
0.10
J
0.88
0.88
+0.15/-0.10
K
0.50
0.80
BASIC
NOTES:
Drawing not to scale.
All units in mm unless otherwise noted.
V
EL
OC
ITY
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 16
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Package Information: 64-pin TQFP
64
49
1
48
33
32
17
G
F
I
H
16
11/13
o
8 PLACES
A
K
A2
0.08 MAX. LEAD
COPLANARITY
0.09/0.20
A
0.25
J
0
o
- 7
o
E
0.08/0.20 R
0.08 R MIN
STANDOFF
Item
10 mm
Tolerance
A
1.20
MAX
A1
0.10
0.05
A2
1.00
0.05
E
0.22
0.05
F
12.00
BASIC
G
10.00
BASIC
H
12.00
BASIC
I
10.00
BASIC
J
0.60
0.15
K
0.50
BASIC
L
3.80
BASIC
M
3.80
BASIC
NOTES:
Drawing not to scale.
All units in mm unless otherwise noted.
A1
L
M
V
EL
OC
ITY
TM
VITESSE
SEMICONDUCTOR CORPORATION
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
Page 17
03/25//01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Package Thermal Considerations
The VSC7123 is packaged in a 14mm, thermally-enhanced PQFP with an internal heat spreader a 10 mm,
thermally enhanced PQFP and a 10mm cavity-down, exposed pad TQFP. These packages use industry-standard
EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the packages is
shown in Figure 10.
Figure 10: PQFP Package Cross Section
Table 6: Thermal Resistance
The VSC7123 is designed to operate with a case temperature up to 95
o
C. The user must guarantee that the
case temperature specification is not violated. With the thermal resistances shown in Table 7, the 10mm
thermally-enhanced PQFP package can operate in still air ambient temperatures of 50
o
C [50
o
C = 95
o
C - 0.9W *
50 C/W]. The 14mm thermally-enhanced PQFP package can operate in still air ambient temperatures of 69
o
C
[69
o
C = 95
o
C - 0.9W * 29 C/W]. The TQFP package can operate in a still air ambient temperature of 59
o
C
[59
o
C = 95
o
C - 0.9W * 40 C/W]. If the ambient air temperature exceeds these limits, a form of cooling through
a heatsink or an increase in airflow must be provided.
Moisture Sensitivity Level
This device is rated at a Moisture Sensitivity Level 3 rating with maximum floor life of 168 hours at 30C,
60% relative humidity. Please refer to Application Note AN-20 for appropriate handling procedures.
Symbol
Description
10mm
PQFP
14mm
PQFP
10mm
TQFP
Units
jc
Thermal resistance from junction-to-case
10
9.5
7.0
o
C/W
ca
Thermal resistance from case-to-ambient in still air including
conduction through the leads.
50
29
40
o
C/W
ca-100
Thermal resistance from case-to-ambient with 100 LFM airflow
41
26
38
o
C/W
ca-200
Thermal resistance from case-to-ambient with 200 LFM airflow
37
24
35
o
C/W
ca-400
Thermal resistance from case-to-ambient with 400 LFM airflow
32
21
33
o
C/W
ca-600
Thermal resistance from case-to-ambient with 600 LFM airflow
28
18
30
o
C/W
Internal Heat Spreader
Die
Plastic Molding Compound
Lead
Bond Wire
Insulator
V
EL
OC
ITY
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 18
G52212-0, Rev 4.3
03/25/01
VITESSE
SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Ordering Information
The part number for this product is formed by a combination of the device number and the package style.
Marking Information
The package is marked with three lines of text as shown in Figure 11 (QU package shown).
Figure 11: Package Marking Information
Notice
Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. All information in this document, includ-
ing descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Noth-
ing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be
available as described or will be suitable for or will accomplish any particular task.
Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without writ-
ten consent is prohibited.
VSC7123
xx
Device Type
Package
10-Bit Transceiver
QN: 64-Pin, 14x14mm PQFP
QU: 64-Pin, 10x10mm PQFP
RD: 64-Pin, 10x10mm TQFP
VITESSE
VSC7123QU
####AAAAA
Part Number
DateCode
Package Suffix
Lot Tracking Code (4 or 5 characters)
Pin 1 Identifier
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