VITESSE
SEMICONDUCTOR CORPORATION
Page 1
12/1/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
G52225-0, Rev. 2.9
Features
General Description
The VSC8151 is a 2.488Gb/s Section Termination device which both monitors and modifies the section and
line overhead of a received SONET/SDH signal, and can generate AIS-L maintenance signals for trouble sec-
tionalization. These features allow all section termination requirements to be supported for Operations, Admin-
istration, Management, and Provisioning (OAM&P) functions in SONET/SDH terminal and optical networking
applications. An integrated 2.488Gb/s serial transceiver isolates the SONET/SDH signal interface, allowing
protocol information to be exchanged with programmable logic using a low-speed TTL interface.
VSC8151 Functional Block Diagram
NOTE: References (R#-#) or (O#-#) refer to the SONET requirement or option specification listed in
Bellcore document GR-253 CORE Issue 2, Rev. 2, January 1999.
Functional Overview
The VSC8151 is divided into two logic sections, a monitoring section and a modification section, each
interfaced externally through both 2.5Gb/s serial interfaces as well as 16-bit parallel interfaces. Incoming
Integrated 2.488Gb/s Transceiver
SONET/SDH Transport Overhead Output
SONET/SDH Transport Overhead Modification
B1 Error Detection, Re-calculation, and Insertion
Support for Multiple SONET/SDH Rates
LOF/SEF Alarm Generation
Section & Line AIS Insertion
50
Source Terminated 2.488Gb/s I/O
1:8
DMX
FRAMING
CONTROL
& ALARM
DETECTION
RXSIN+/-
RXSCLKIN+/-
DESCRAMBLER
RXSEF
RXFPOUT
RXFRERR
RXLOF
B1
MONITOR
OVERHEAD
OUTPUT
RXOHCLK
RXOHOUT[7:0]
OVERHEAD
INPUT &
INTERNAL
CONTROL
TXOHIN[7:0]
AIS
GENERATION
SCRAMBLER
& B1 CALC
8:1
MUX
TXSCLKOUT+/-
TXSOUT+/-
TXPOUT[15:0]
POUTCLK
TXFPOUT
LOS
SYSRST
TXSCLKIN+/-
ASSEMBLER
TXWRENA
TXOHWI
POUTCLK
RXPIN[15:0]
TXADDR[5:0]
RXPIN[7:0]
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
12/1/99
G52225-0, Rev. 2.9
SONET/SDH data is demultiplexed, framed, descrambled, and the 27 bytes of the section and line overhead are
output. The BIP parity of the incoming signal is calculated and compared with the received B1 and B2 bytes for
calculating received parity errors. The byte aligned data, calculated B1/B2 parity, and frame boundary location
are then passed to the modification section where new overhead bytes are inserted. The modified data is
rescrambled, and B1/B2 parity recalculated (if desired) prior to serialization and output. An internal state
machine generates a section alarm inhibit signal (AIS) with user defined transport overhead that can be alterna-
tively transmitted in place of the received signal.
2.5G Serial and Parallel Input Interfaces
The demux receives differential clock and data signals at the appropriate SONET/SDH rate and demulti-
plexes the data for framing. These inputs are internally terminated by a center-tapped resistor network and
include biasing resistors to facilitate AC coupling. For differential input DC coupling, the network is terminated
to the appropriate termination voltage V
Term
providing a 50
to
V
Term
termination for both true and complement
inputs. For differential input AC coupling, the network is terminated to V
Term
via a blocking capacitor.
The common mode reference voltage is created by a resistor divider as shown. If the input signal is driven
differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this
reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-coupling operations,
it is recommended that the user provides an external reference voltage which has better temperature and power
supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value
equivalent to the common mode switch point of the DC coupled signal, and can be connected to either side of
the differential gate.
Figure 1: High Speed Serial Clock and Data Inputs
R
| |
Chip Boundary
V
CC
=
3.3V
V
EE
= 0V
1.65V
1.65V
Z
O
Z
O
C
IN
C
IN
TYP = 100 pF (clock), 100nF (data)
C
SE
TYP = 100 pF (clock), 100nF (data) for single ended applications.
C
SE
C
AC
V
TERM
=
1.5k
50
50
VITESSE
SEMICONDUCTOR CORPORATION
Page 3
12/1/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
G52225-0, Rev. 2.9
The serial demux can be bypassed and the 16-bit single-ended PECL bus RXPIN[15:0] can be used to input
SONET/SDH data for applications where the data has already been deserialized by a previous device. This
mode is selected by asserting the EQULOOP input (active high). Input setup and hold requirements are speci-
fied with respect to the falling edge of POUTCLK; the user is responsible for meeting loop timing requirements
between the VSC8151 and previous device. The user must still provide a line rate clock to the serial clock input
RXSLKIN+/- to provide a high-speed output clock to the mux and the means to create the divide-by-16 POUT-
CLK.
2.5G Serial and Parallel Output Interfaces
The high speed clock and data output driver consists of a differential pair designed to drive a 50
transmis-
sion line. The transmission line should be terminated with a 100
resistor at the load between true and comple-
ment outputs. No connection to a termination voltage is required. The output driver is source terminated to 50
on-chip, providing a snubbing of any reflections. If used single-ended, one way to terminate the output driver is
differentially at the load with a 100
resistor between true and complement outputs. See Figure 2A. Another
option is to terminate the used output at the load with 50 ohm to V
TERM
and the unused output with 50 ohm to
V
TERM
at the source. See Figure 2B.
In some applications, it may be desirable to turn off the high speed outputs (TXSOUT, TXSCLKOUT) to
reduce power. To disable the high speed clock output, tie pin 22 to V
CC
(3.3V) instead of GND. To disable the
high speed data output, tie pin 17 to V
CC
(3.3V) instead of GND. Turning off each output will reduce maximum
current consumption by 107mA for the clock output, and 122mA for the data output.
Figure 2: High Speed Output Driver & Termination
V
CC
V
EE
Z
0
= 50
50
100
50
Pre-Driver
Figure 2A
V
CC
V
EE
V
TERM
V
TERM
Z
0
= 50
50
50
50
50
Pre-Driver
Figure 2B
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
12/1/99
G52225-0, Rev. 2.9
The serial mux output can be bypassed and the 16-bit single-ended PECL bus TXPOUT[15:0] can be used
to output modified SONET/SDH data or AIS to another device. These outputs are enabled by setting the DP bit
in the MISC register appropriately, and should be disabled if not being used. It is possible to use both the 16-bit
parallel output bus and the 2.5Gb/s serial output simultaneously. The POUTCLK output is used to provide a bus
output clock for RXFPOUT and is a divide-by-16 version of TXSCLKIN.
2.5G Output Clocking Domains
The 2.5GHz clock input to the VSC8151 mux (TXSCLKIN) acts as the permanent transmit clock for the
VSC8151. An internal clock domain boundary exists between the monitor and the transmit sections of the
device, allowing the AIS transmit portion to function completely independently of the receive portion. This
allows a CDR to track whatever data is being received and allows the VSC8151 to monitor in-frame status of
the signal continuously.
During a LOS condition, the CDR clock output may drift outside of the SONET/SDH transmission stan-
dard of +/-20PPM. By providing the option of using an external clock multiplication unit (CMU), one can
maintain a standard of +/-20PPM even during AIS states. This backup CMU receives it's timing reference from
either a local AIS reference or the divided clock from the received RXSCLKIN +/-, depending whether AIS
transmit mode is selected or not.
The user controls the source of the reference clock output through settings in the VSC8151 register file.
The user will change these settings at the same time AIS is asserted or when imminent loss of RXSCLKIN
clock quality exists. The AIS reference output can be switched from a divided down RXSCLKIN signal to a
copy of one of the external references, ensuring that a proper reference clock remains for the transmit multi-
plexer. (See Table 2: VSC8151 Configuration Registers, Definition 13)
Figure 3: VSC8151 using CMU as Transmit Timing Source
Clock and
Data Recovery
Clock
Multiplication
Unit
2.488Gb/s Data
622Mb/s Data
155MB/s Data
2.488GHz Clock
622MHz Clock
155MHz Clock
Demux &
Monitor
Logic
SEF/LOF ALARMS
Modify
Logic
AIS State
Machine
Mux &
Frame
Assembly
Logic
AIS Insert
Received
Data
CMU
Reference
Generator
AIS Reference
155/78 MHz
AIS Reference
78 MHz
VSC8122
VSC812X
2.488GHz Clock
622MHz Clock
155MHz Clock
RXSIN+/-
RXSCLKIN+/-
TXSOUT+/-
TXSCLKOUT+/-
TXSCLKIN+/-
VITESSE
SEMICONDUCTOR CORPORATION
Page 5
12/1/99
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
G52225-0, Rev. 2.9
If the user chooses to use the CDR as a timing source even during AIS mode, the output of the CDR can be
connected single ended to both RXSCLKIN and TXSCLKIN, or a multi-drop connection can be made differen-
tially.
Figure 4: VSC8151 using CDR as Transmit Timing Source
SONET/SDH Monitoring Circuitry Overview
The monitoring circuitry provides SONET/SDH compliant framing and framing alarms, as well as detect-
ing B1 and B2 parity errors and transport overhead byte output.
Framing
The frame acquisition algorithm determines the in-frame/out-of-frame status of the receiver. Out-of-frame
is defined as a state where the frame boundaries of the received SONET/SDH signal are unknown, i.e. after sys-
tem reset or if for some reason the receiver looses synchronization, e.g. due to `bit slips'. In-frame is defined as
a state where the frame boundaries are known.
The receiver monitors the frame synchronization by checking for the presence of a portion of the A1/A2
framing pattern every 125uS. If one or more bit errors are detected in the expected A1/A2 framing pattern out-
put RXFRERR (active high) will be asserted (See Figure 5). If framing pattern errors are detected for four con-
secutive frames a Severely Errored Frame (SEF) alarm will be asserted on output RXSEF (active high) (R5-
223).
Clock and
Data Recovery
2.488Gb/s Data
622Mb/s Data
155MB/s Data
2.488GHz Clock
622MHz Clock
155MHz Clock
Demux &
Monitor
Logic
SEF/LOF ALARMS
Modify
Logic
AIS State
Machine
Mux &
Frame
Assembly
Logic
AIS Insert
Received
Data
CMU
Reference
Generator
AIS Reference
155/78 MHz
AIS Reference
78 MHz
VSC8122
2.488GHz Clock
622MHz Clock
155MHz Clock
RXSIN+/-
RXSCLKIN+/-
TXSOUT+/-
TXSCLKOUT+/-
TXSCLKIN+/-
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