PHYSICAL LAYER PRODUCT
VSC9185
F E A T U R E S :
Interconnection Matrix
Time & Space Switches any STS-(n) [n=1,3c,12c,48c,192c]
Signal of an Incoming STS-48 into any Byte Position of any
STS-48 Output
Single Stage Non-blocking Structure of the Switch Allows
for Unrestricted Multicast and Broadcast
Programmable Service/Protection Map (with Individual
Shadow Memories)
New Connection Maps Take Effect on the Next Frame
Boundary After User Intervention or In-Band
Reconfiguration Signal
Input Backplane Interface
Serial 2.488 and 0.622 Gb/s Differential CML STS-48/STM-
16 and STS-12/STM-4 Inputs
Includes Optional Analog Equalization Circuitry for
Deterministic Link Jitter Reduction
Receives 64 Serial Line Channels Frequency Synchronous
and Frame Aligned to within +/- 24 Time Slots for STS-48
Frames, or +/- 12 Time Slots for STS-12 Frames
Provides On-chip Data Recovery De-skewing Functionality
to Bit Align, Byte Align, and Frame-align all Incoming
Signals (within the above tolerance) to the Local Clock
VSC9185 Blackcomb - 64x64 STS-48/STM-16 TSI Switch Fabric
S P E C I F I C A T I O N S :
Input Backplane Interface Cont.
Flags Out-of-Frame (OOF), Loss-of-Signal (LOS), Out-of-Alignment
OOA), and Parity Errors
Checks B1 Parity of Incoming Data
Accumulates Received B1 Errors
Inserts Unequipped or AIS When Channel is in OOF, LOS, or
Unprovisioned State and Inhibits Alarms
Optionally De-scrambles Incoming SONET Data
Monitors Received TOH Bytes
Output Backplane Interface
Serial 2.488 and 0.622 Gb/s Differential CML STS-48/STM-16 and STS-
12/STM-4 Outputs
Optionally Pre-emphasizes Electrical Signals for Deterministic Link Jitter
Reduction
Optionally Inserts Byte-Interleaved Parity into B1 Byte of
Following Frame
Originates In-Band Messages to Port Cards for Switching Purposes
Optionally Scrambles Outgoing SONET Data
Optionally Inserts AIS or UNEQ on a Per-channel, Per-timeslot Basis
CPU Interface
Generic Microprocessor (CPU) Interface used for Device Configuration
and Status Checking
Test Interface
IEEE P1149.1 Test Access Port Controls External Boundary Scan
TIMESTREAM PRODUCT FAMILY
PB-VSC9185-001
741 Calle Plano
Camarillo, CA 93012
Tel: 805.388.3700
Fax: 805.987.5896
www.vitesse.com
Your Partner for Success.
For more information on Vitesse Products visit the Vitesse web site
at www.vitesse.com or contact Vitesse Sales at (800) VITESSE
or sales@vitesse.com
2002 Vitesse Semiconductor Corporation
The VSC9185 is a 64x64 Time Slot
Interchange Switch IC supporting STS-
48/STM-16 and STS-12/STM-4 on every
input and output independently. A single
device provides 160G of non-blocking
STS-1 connectivity (3072x3072 STS-1) with
support for concatenated tributaries. All inputs and outputs
are differential serial signals running at 2.488 or 0.622Gb/s for
flexibility in switch card and system backplane design.
Backplane BER monitoring and deskew are integrated, and
the service/protection connection maps can be manually
selected on an individual output timeslot basis or driven by in-
band signaling for hardware protection switching. Path AIS or
UNEQ can be optionally inserted into all 3072 outgoing STS-1
tributaries. A standard asynchronous CPU interface with
event interrupts is also supported.
VSC9185 Architectures
A single VSC9185 provides sufficient connectivity for a 64x64
OC-48 STS-1 grooming solution. One VSC9185 in conjunction
with the VSC9186 10G Pointer Processor & Frame Aligner
provide a solution for a 64x64 OC-48 grooming solution with
support for larger switch fabrics. Multiple VSC9185 devices
can be used in a three stage Clos architecture to construct
larger switches. The VSC9185 is designed to interface directly
with the VSC9186 Pointer Processor & Frame Aligner and the
VSC9180 2.5G Backplane Transceiver.
G E N E R A L D E S C R I P T I O N :
VSC9185 Blackcomb - 64x64 STS-48/STM-16 TSI Switch Fabric
In-band Signaling and Hardware Protection Switching
Observes In-Band Alarm-Status (ASB) Bytes and Performs
Hardware Comparison to Drive Selection of Service/
Protection Connection Maps
Provides True Hardware Support for 1+1 Protection Switching
Utilizes ASB Byte Generation Capability of VSC9186 10G
Pointer Processor
VSC9185
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4 x OC-48
1 x OC-192
2.5Gb/s
2.5Gb/s
2.5Gb/s
VSC9187/88
VT/TU Switch
T1/E1/DS-3 Term
DS-0/DS-1/DS-3
HDLC & M13
VSC9186 10Gb/s
Pointer Processor
PHY's & Analog
DS-3
T1/E1
VSC9182/VSC9185 40G/160G TSI
2.5Gb/s
2.5Gb/s
Ethernet
PHY, MAC,
Packet
P
SONET/SDH Framer
(STS3c) - STS48c)
Packet/Cell
P
SONET/SDH Framer
(STS48c - STS-768c)
Packet/Cell
P
Layer 2/3/4 Packet/Cell Switch Fabric
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T I M E S T R E A M D I A G R A M :
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