Document:1G5-0179
Rev.3
Page 1
VIS
VG26(V)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Description
The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is
fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V only
power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. Self-
refresh is supported and CBR cycles are being performed. lt is packaged in JEDEC standard 42-pin 400mil SOJ and
50(44)-pin 400mil TSOPII.
Features
Single 5V or 3.3V only power supply
High speed t
RAC
access time: 50/60ns
Extended-data-out (EDO) page mode access
I/O level: TTL compatible (Vcc = 5V)
LVTTL compatible (Vcc = 3.3V)
4 refresh modes:
- RAS only refresh
- CAS - before - RAS refresh
- Hidden refresh
- Self-refresh
Refresh interval:
- RAS only refresh, CAS - before - RAS refresh and hidden refresh: 1024 cycles in 16 ms
- Self-refresh: 1024 cycles
JEDEC standard pinout: 42-pin 400mil SOJ and 50(44)-pin 400mil TSOPII
Document:1G5-0179
Rev.3
Page 2
VIS
VG26(V)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Pin Name
Function
A0-A9
Address inputs
- Row address: A0-A9
- Column address: A0-A9
- Refresh address: A0-A9
DQ0~DQ15
Data-in / data-out
RAS
Row address strobe
UCAS, LCAS
Column address strobe
WE
Write enable
OE
Output enable
Vcc
Power (+5 V or + 3.3V)
Vss
Ground
NC
No connection
Pin Description
Pin Configuration
42-Pin 400mil SOJ
VCC
1
DQ0
2
DQ1
3
DQ2
4
DQ3
5
VCC
6
DQ4
7
DQ5
8
DQ6
9
DQ7
10
NC
11
NC
12
WE
13
RAS
14
NC
15
A0
16
A1
17
A2
18
A3
19
VCC
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
24
23
22
21
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
NC
NC
41
42
A9
26
25
VCC
1
DQ0
2
DQ1
3
DQ2
4
DQ3
5
VCC
6
DQ4
7
DQ5
8
DQ6
9
DQ7
10
NC
11
NC
WE
RAS
18
NC
19
A0
20
A1
21
A2
22
A3
23
VCC
24
36
35
33
34
31
28
27
26
25
NC
30
29
17
15
16
50
49
48
47
46
45
44
43
42
41
40
32
NC
DQ14
DQ13
DQ12
GND
DQ11
DQ10
DQ9
DQ8
NC
NC
LCAS
UCAS
A8
A7
A6
GND
DQ15
GND
OE
A9
A5
A4
50(44)-Pin 400mil TSOPII
Document:1G5-0179
Rev.3
Page 3
VIS
VG26(V)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
WE
LCAS
UCAS
NO.2 CLOCK
GENERATOR
CAS
COLUMN-
ADDRESS
BUFFERS (10)
REFRESH
CONTROLLER
REFRESH
COUNTER
BUFFERS (10)
ADDRESS
ROW -
NO.1 CLOCK
GENERATOR
A0
RAS
A1
A2
A3
A4
A5
A6
A7
A9
CONTROL
LOGIC
DATA - IN BUFFER
DATA - OUT
BUFFER
OE
DQ1
.
DQ16
.
COLUMN
DECODER
1024
SENSE AMPLIFIERS
I/0 GATING
1024x16
1024 x 1024 x 16
MEMORY
ARRAY
1
0
2
4
R
O
W
D
E
C
O
D
E
R
Vcc
Vss
Block Diagram
A8
Document:1G5-0179
Rev.3
Page 4
VIS
VG26(V)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
TRUTH TABLE
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
FUNCTION
RAS
LCAS
UCAS
WE
OE
ADDRESSES
DQ
S
Notes
ROW
COL
STANDBY
H
X
X
X
X
High-Z
READ : WORD
L
L
L
H
L
ROW
COL
Data-Out
READ : LOWER BYTE
L
L
H
H
L
ROW
COL
Lower Byte: Data-Out
Upper Byte: High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte: High-Z
Upper Byte: Data-Out
WRITE: WORD
(EARLY WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte: Data-In
Upper Byte: High-Z
WRITE : UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte: High-Z
Upper Byte: Data-In
READ WRITE
L
L
L
ROW
COL
Data-Out, Data-In
1,2
PAGE-MODE
READ
1st Cycle
L
H
L
ROW
COL
Data-Out
2
2nd Cycle
L
H
L
n/a
COL
Data-Out
2
PAGE-MODE
WRITE
1st Cycle
L
L
X
ROW
COL
Data-In
1
2nd Cycle
L
L
X
n/a
COL
Data-In
1
PAGE-MODE
READ-
WRITE
1st Cycle
L
ROW
COL
Data-Out, Data-In
1,2
2nd Cycle
L
n/a
COL
Data-Out, Data-In
1,2
HIDDEN
REFRESH
READ
L
L
H
L
ROW
COL
Data-Out
2
WRITE
L
L
L
X
ROW
COL
Data-In
1,3
RAS-ONLY REFRESH
L
H
H
X
X
ROW
n/a
High-Z
CBR REFRESH
L
L
H
X
X
X
High-Z
4
H
X
H
X
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
H
L
H
L
L
H
L
H
L
L
H
L
H
L
Document:1G5-0179
Rev.3
Page 5
VIS
VG26(V)18165C
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Absolute Maximum Ratings
Recommended DC Operating Conditions
Capacitance
Ta = 25C, V
CC
= 5V
%
or 3.3V
%, f = 1MHz
Note: 1. Capacitance measured with effective capacitance measuring method.
2. RAS,
LCAS and UCAS
= V
IH
to disable Dout.
Parameter
Symbol
Value
Unit
Voltage on an any pin relative to Vss 5V
3.3V
V
T
-1.0 to + 7.0
V
-0.5 to + 4.6
Supply voltage relative to Vss 5V
3.3V
V
CC
-1.0 to + 7.0
V
-0.5 to + 4.6
Short circuit output current
I
OUT
50
mA
Power dissipation
P
D
1.0
W
Operating temperature
T
OPT
0 to + 70
C
Storage temperature
T
STG
-55 to + 125
C
Parameter/Condition
Sym-
bol
5 Volt Version
3.3 Volt Version
Unit
Min
Typ
Max
Min
Typ
Max
Supply Voltage
V
CC
4.5
5.0
5.5
3.15
3.3
3.6
V
Input High Voltage, all inputs
V
IH
2.4
-
V
CC
+ 1.0
2.0
-
V
CC
+ 0.3
V
Input Low Voltage, all inputs
V
IL
-1.0
-
0.8
-0.3
-
0.8
V
Parameter
Symbol
Max
Unit
Note
Input capacitance (Address)
C
I1
5
pF
1
Input capacitance (RAS , LCAS , UCAS, OE, WE)
C
I2
7
pF
1
Output capacitance (Data-in, Data-out)
C
I/O
7
pF
1, 2
10
10
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