Document:1G5-0189
Rev.1
Page 1
VIS
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
Description
The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V
power supply. This SDRAM is delicately designed with performance concern for current high-speed applica-
tion. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It
is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features
Single 3.3V +/- 0.3V power supply
Clock frequency:166MHz, 143MHz, 125MHz
Fully synchronous with all signals referenced to a positive clock edge
Programmable CAS Iatency (2,3)
Programmable burst length (1,2,4,8,& Full page)
Programmable wrap sequence (Sequential/Interleave)
Automatic precharge and controlled precharge
Auto refresh and self refresh modes
Dual internal banks controlled by A11(Bank select)
Simultaneous and independent two bank operation
I/O level : LVTTL interface
Random column access in every cycle
X16 organization
Byte control by LDQM and UDQM
4096 refresh cycles/64ms
Burst termination by burst stop and precharge command
Document:1G5-0189
Rev.1
Page 2
VIS
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
Pin Configuration
Pin Description
(VG3617161ET)
Pin Name
Function
Pin Name
Function
A0-A11
Address inputs
- Row address A0-A10
- Column address A0-A7
A11: Bank select
LDQM,
UDQM
Lower DQ mask enable and
Upper DQ mask enable
DQ0~DQ15
Data-in/data-out
CLK
Clock input
RAS
Row address strobe
CKE
Clock enable
CAS
Column address strobe
CS
Chip select
WE
Write enable
V
DDQ
Supply voltage for DQ
V
SS
Ground
V
SSQ
Ground for DQ
V
DD
Power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
38
37
36
35
34
33
32
31
30
29
28
27
26
V
G
3
6
1
7
1
6
1
E
T
50-Pin Plastic TSOP(II)(400 mil)
V
DD
DQ0
V
DDQ
DQ1
V
SSQ
DQ2
DQ3
DQ4
V
SSQ
CAS
A
10
(BS)A
11
A
0
A
1
V
SS
DQ15
V
SSQ
DQ13
V
SSQ
DQ12
V
DDQ
DQ11
CLK
DQ8
NC
UDQM
CKE
NC
A8
A9
A7
A6
DQ5
DQ6
DQ7
V
DDQ
23
24
25
50
49
48
47
46
45
DQ14
DQ10
DQ9
V
DDQ
A5
A4
V
SS
A
2
A
3
V
DD
CS
40
39
LDQM
RAS
WE
Document:1G5-0189
Rev.1
Page 3
VIS
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
Block Diagram
CLK
CKE
Clock
Generator
CS
RAS
Mode
Register
Column
Address
Buffer
&
Burst
Counter
CAS
WE
C
o
m
m
a
n
d
D
e
c
o
d
e
r
C
o
n
t
r
o
l
L
o
g
i
c
Address
Row
Address
Buffer
&
Refresh
Counter
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
R
o
w
D
e
c
o
d
e
r
Data Control Circuit
DQ
DQM
L
a
t
c
h
C
i
r
c
u
i
t
I
n
p
u
t
&
O
u
t
p
u
t
B
u
f
f
e
r
Document:1G5-0189
Rev.1
Page 4
VIS
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
Absolute Maximum Ratings
(1)
Recommended DC Operating Conditions (T
A
=0~70
C)
Note I.Overshoot limit : V
IH(MAX.)
=V
DDQ
+2.0V with a pulse width < 3ns
II .Undershoot limit : V
IL
=V
SSQ
-2.0V with a pulse width< 3ns and -1.5V with a pulse width< 5ns
DC Electrical Characteristics
Capacitance
(T
A
=25C,f=1MHZ)
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
,V
OUT
-1.0 to +4.6
V
Supply voltage relative to Vss
V
DD
,V
DDQ
-1.0 to +4.6
V
Short circuit output current
I
OUT
50
mA
Power dissipation
P
D
1.0
W
Operating temperature
T
OPT
0 to + 70
C
Storage temperature
T
STG
-55 to + 125
C
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
V
DD
3.0
3.3
3.6
V
Input High Voltage, all inputs
V
IH
2.0
V
DD
+0.3
V
I
Input Low Voltage, all inputs
V
IL
-0.3
0.8
V
II
Parameter
Description
Min.
Max.
Unit
Note
I
IL
Input Leakage Current
(
All other pins not under test = 0V)
-5
5
A
I
OL
Output Leakage Current
Output disable, (
)
-5
5
A
V
OH
LVTTL Output "H" Level Voltage(l
OUT
= -2mA)
2.4
-
V
V
OL
LVTTL Output "L" Level Voltage(l
OUT
= 2mA)
-
0.4
V
Parameter
Symbol
Typ
Max
Unit
Input capacitance(CLK)
C
11
2.5
4
pF
Input capacitance(all input pins except data
pins)
C
12
2.5
5
pF
Data input/output capacitance
C
I/O
4.0
6.5
pF
0V VIN VDD
0V VOUT VDDQ
Document:1G5-0189
Rev.1
Page 5
VIS
VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
I
DD
Specifications (V
DD
= 3.3V 0.3V, T
A
= 0 ~ 70C)
Description/test condition
Symbol
-6
-7
-8
Unit Note
Min
Max
Min
Max
Min
Max
Operating Current
, outputs open
Address changed once during t
CK(min)
.
Burst length = 1 (One bank active)
I
DD1
115
105
95
mA
3,4
Precharge Standby Current in non power-down
mode
(min)
,
(min),
t
CK
=t
CK
(min)
Input signals are changed once during 2 clocks
I
DD2N
40
40
40
3
Precharge Standby Current in non power-down
mode
(min)
, t
CK
= ,
(max)
Input signals are stable
I
DD2NS
35
35
35
Precharge Standby Current in power-down mode
(max)
, t
CK
= t
CK
(min)
I
DD2P
2
2
2
Precharge Standby Current in power-down mode
(max)
, t
CK
= ,
(max)
I
DD2PS
2
2
2
Active Standby Current in non power-down mode
(min)
, CS V
IH(min)
, t
CK
= t
CK(min)
Input signals are changed once during 2 clocks
I
DD3N
50
50
50
3
Active Standby Current in non power-down mode
(min)
, t
CK
= ,
(max)
Input signals are stable
I
DD3NS
40
40
40
Active Standby Current in power-down mode
(max)
, t
CK =
t
CK(min)
I
DD3P
35
35
35
Active Standby Current in power-down mode
(max)
, t
CK =
,
(max)
I
DD3PS
35
35
35
Operating Current
(Page burst, and all banks activated)
t
CCD
= t
CCD(min)
, outputs open, gapless data
I
DD4
150
140
130
4,5
Refresh Current
(min)
(t
REF
= 64ms)
I
DD5
100
90
80
3
Self Refresh Current
I
DD6
1
1
1
tRC tRC min
(
)
CKE V
IH
CS V
IH
CKE V
IH
CLK
V
IL
CKE V
IL
CKE V
IL
CLK
V
IL
CKE
V
IH
CKE
V
IH
CLK
V
IL
CKE
V
IL
CKE
V
IL
CLK
V
IL
t
RC
t
RC
CKE
0.2V
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