Document:1G5-0133
Rev.1
Page 1
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
Description
The VG3617801CT is CMOS Synchronous Dynamic RAMs organized as 1,048,576-word X 8-bit X 2-
bank. It is fabricated with an advanced submicron CMOS technology and is designed to operate from a sin-
gle 3.3V power supply. This is packaged using JEDEC standard pinouts and standard plastic TSOP.
Features
Single 3.3V(
) power supply
Clock Frequency:100MHz
Fully synchronous with all signals referenced to a positive clock edge
Programmable CAS Iatency (2,3)
Programmable burst length (1,2,4,8,& Full page)
Programmable wrap sequence (Sequential/Interleave)
Automatic precharge and controlled precharge
Auto refresh and self refresh modes
Dual Internal banks controlled by A11(Bank select)
Simultaneous and independent two bank operation
I/O level : LVTTL interface
Random column access in every cycle
X8 organization
Input/output control by DQM
2048 refresh cycles/32ms
Burst termination by burst stop and precharge command
Burst read single write option
0.3V
Document:1G5-0133
Rev.1
Page 2
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
Pin Configuration
Pin Description
(VG3617801CT)
Pin Name
Function
Pin Name
Function
A0-A11
Address inputs
- Row address A0-A10
- Column address A0-A8
A11:Bank select
DQM
DQ mask enable
DQ0~DQ7
Data-in/data-out
CLK
Clock input
RAS
Row address strobe
CKE
Clock enable
CAS
Column address strobe
CS
Chip select
WE
Write enable
V
DDQ
Supply voltage for DQ
V
SS
Ground
V
SSQ
Ground for DQ
V
DD
Power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
G
3
6
1
7
8
0
1
C
T
44-Pin Plastic TSOP(II)(400 mil)
V
DD
DQ0
V
SSQ
V
DDQ
DQ2
V
SSQ
DQ3
V
DDQ
NC
NC
CAS
RAS
CS
(BS)A
11
A
10
A
0
A
1
A
2
A
3
V
DD
V
SS
DQ7
V
SSQ
DQ6
V
DDQ
DQ5
V
SSQ
DQ4
V
DDQ
NC
CLK
DQM
CKE
NC
V
SS
WE
A
9
A
8
A
7
A
6
A
5
A
4
NC
DQ1
Document:1G5-0133
Rev.1
Page 3
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
Block Diagram
CLK
CKE
Clock
Generator
CS
RAS
Mode
Register
Column
Address
Buffer
&
Burst
Counter
CAS
WE
C
o
m
m
a
n
d
D
e
c
o
d
e
r
C
o
n
t
r
o
l
L
o
g
i
c
Address
Row
Address
Buffer
&
Refresh
Counter
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
R
o
w
D
e
c
o
d
e
r
Data Control Circuit
DQ
DQM
L
a
t
c
h
C
i
r
c
u
i
t
I
n
p
u
t
&
O
u
t
p
u
t
B
u
f
f
e
r
Document:1G5-0133 Rev.1 Page 4
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
Absolute Maximum Ratings
Recommended DC Operating Conditions
Note 1.Overshoot limit : V
IH(MAX.)
=V
DDQ
+2.0V with a pulse width < 3ns
2.Undershoot limit : V
IL
=V
SSQ
-2.0V with a pulse < 3ns and -1.5V with a pulse < 5ns
Capacitance
(Ta=25J,f=1MHZ)
Parameter Symbol Value Unit
Voltage on any pin relative to Vss V
IN
,V
OUT
-1.0 to +4.6 V
Supply voltage relative to Vss V
DD
,V
DDQ
-1.0 to +4.6 V
Short circuit output current I
OUT
50 mA
Power dissipation P
D
1.0 W
Operating temperature T
OPT
0 to + 70
J
Operating temperature T
STG
-55 to + 125
J
Parameter Symbol Min Typ Max Unit Note
Supply Voltage V
DD
3.0 3.3 3.6 V
Input High Voltage, all inputs V
IH
2.0
V
DD
+0.3 V 1
Input Low Voltage, all inputs V
IL
-0.3
0.8 V 2
Parameter Symbol Min Max Unit
Input capacitance(CLK) C
11
2.5 4 pF
Input capacitance(all input pins except data pins) C
12
2.5 5 pF
Data input/output capacitance C
I/O
4.0 6.5 pF
Document:1G5-0133
Rev.1
Page 5
VIS
VG3617801CT
16Mb CMOS Synchronous Dynamic RAM
DC Characteristics(Recommended Operating Conditions unless otherwise noted)
Notes 1.I
cc
depends on output loading and cycle rates. Specified values are obtained with the output open.
2.I
cc
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
Parameter
Symbol
Test Conditions
VG3617801CT
-8H
-8L
-10
Unit
Notes
Min
Max
Min
Max
Min
Max
Operating current
I
CC1
Burst length=1
(MIN.)
,Io=0mA
One bank active
CL=3
90
90
85
mA
1,2
CL=2
85
85
80
Precharge standby
current in power
down mode
I
CC2
P
IL(MAX.)
t
CK
=15ns
3
3
3
mA
I
CC2
PS
IL(MAX)
t
CK
=
2
2
2
Precharge standby
current in Nonpower
down mode
I
CC2
N
IH(MIN.)
t
CK
=15ns
IH(MIN.)
Input signals are changed.
one time during 30ns.
30
30
30
mA
I
CC2
NS
IH(MIN.)
, tCK=
IL(MAX.)
Input signals are stable.
6
6
6
Active standby current
in power down mode
I
cc3
P
IL(MAX.)
,t
CK
=15ns
3
3
3
mA
I
cc3
PS
IL(MAX.)
,t
CK
=
2
2
2
Active standby current
in nonpower down
mode
I
cc3
N
IL(MAX.)
,t
CK
=15ns
IL(MIN.)
Input signals are changed
one time during 30ns
30
30
30
mA
I
cc3
NS
IH(MIN.)
t
CK
=
IL(MAX.)
Input signals are stable.
15
15
15
Operating current
(Burst mode)
I
cc4
(MIN.)
,Io=0mA
Burst length=4
CL=3
120
120
105
mA
1,2
CL=2
115
105
100
Refresh current
I
cc5
(MIN.)
CL=3
110
110
100
mA
2
CL=2
105
105
95
Self refresh current
I
cc6
2
2
2
mA
Input leakage current
I
LI
,
+0.3V
Pins not under test=0V
-5
5
-5
5
-5
5
uA
Output leakage current I
LO
, +0.3V
DQ# in H-Z., Dout disabled
-5
5
-5
5
-5
5
uA
Output Low Voltage
V
OL
I
OL
=2mA
0.4
0.4
0.4
V
Output High Voltage
V
OH
I
OH
=2mA
2.4
2.4
2.4
V
t
R C
t
RC
CKE
V
CKE
V
CKE
V
CS
V
CKE
V
CLK
V
CKE
V
CKE
V
CKE
V
CS
V
CKE
V
CLE
V
t
C K
t
C K
t
R C
t
RC
CKE
0.2V
V
in
0
V
in
V
DD
V
OUT
0
V
OUT
V
DD
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