Document :1G5-0174
Rev.3
Page 1
VIS
VG37128802AT
Preliminary VG37128162AT
CMOS DDR Synchronous Dynamic RAM
Description
The 128Mb DDR SDRAM is a high-speed COMS, dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-bank DRAM. The 128Mb DDR SDRAM
uses a double-data-rate architecture to achieve high-speed operation. A bidirectional data
strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the mem-
ory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with
data for WRITEs.
The 128Mb DDR SDRAM operates from a differential clock (CLK and CLK#; the crossing of
CLK going HIGH and CLK# going LOW will be referred to as the positive edge of CLK). Com-
mands (address and control signals) are registered at every positive edge of CLK. Input data is
latched by both edges of DQS with DQS aligned to center of data packet, and output data is
latched by both edges of DQS with DQS aligned to edge of data packet.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4 or 8 loca-
tions. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective bandwidth by hiding row precharge and
activation time.
The 128Mb DDR SDRAM is designed to operate in either low-power memory systems. An
auto refresh mode is provided, along with a power-saving, power-down mode. All inputs are
compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described in, and the timing specifications included in this data sheet are
for the DLL Enabled mode of operation. This is the only normal operating mode for these
DDR devices.
Document :1G5-0174
Rev.3
Page 2
VIS
VG37128802AT
Preliminary VG37128162AT
CMOS DDR Synchronous Dynamic RAM
Features
JEDEC compatible
Double-data-rate architecture: two data transfers per clock cycle
Bidirectional, intermittent data strobe (DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge-aligned with data for READs: center-aligned with data for WRITEs
Differential clock inputs (CLK and CLK#)
DLL aligns DQ and DQS transitions with CLK transitions
Commands entered on each positive CLK edge; data referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 2, 4, or 8
CAS Latency: 2, 2.5,3
AUTO PRECHARGE option for each burst access
Auto Refresh and Self Refresh Modes
15.6 us Auto Refresh Interval
2.5V (SSTL_2 compatible) I/O
VDDQ=+2.5V 0.2V
VDD=+2.5V 0.2V
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