1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI2AG272129V
July 1999
Rev 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
2 Megabyte Sync/Sync Burst, Small Outline DIMM
FEATURES
The EDI2AG272129VxxD1 is a Synchronous/
Syn chro nous Burst SRAM, 72 position SO DIMM (144
con tacts) Module, organized as 2x128Kx72. The Module
con tains four (4) Synchronous Burst Ram Devices,
pack aged in the industry standard JEDEC 14mmx20mm
TQFP placed on a Multilayer FR4 Sub strate. The
module architecture is defi ned as a Sync/Sycn Burst,
Flow-Through, with support for sequential burst. This
module pro vides High Per for mance, 2-1-1-1 ac cess es
when used in Burst Mode, and used as a Synchronous
Only Mode, provides a high per for mance cost ad van tage
over BiCMOS aysnchronous device ar chi tec tures.
Synchronous Only operations are performed via
strap ping ADSC# Low, and ADSP# / ADV# High, which
pro vides for Ultra Fast Accesses in Read Mode while
pro vid ing for internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in
re la tion to an externally supplied clock, Registered
Address, Reg is tered Global Write, Registered Enables
as well as an Asynchronous Output enable. This Module
has been defined with full flexibility, which allows
individual control of each of the eight bytes, as well as
Quad Words in both Read and Write Operations.
*This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
2x128Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Sequential
Burst
MODE
Clock Controlled Registered Bank Enables (E1#, E2#)
Clock
Controlled
Byte
Write
Mode
Enable
(BWE#)
Clock
Controlled
Byte
Write
Enables
(BW1# - BW8#)
Clock
Controlled
Registered
Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous
Output
Enable
(G#)
Internally
self-timed
Write
Gold
Lead
Finish
3.3V 10% Operation
Access Speed(s): TKHQV=8.5, 9, 10, 12ns
Common
Data
I/O
High Capacitance (30pf) drive, at rated Access Speed
Single total array Clock
Multiple
Vcc
and
Gnd
DESCRIPTION
2
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
EDI2AG272129V
July 1999
Rev 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DQ0-DQ63
Input/Output Bus
DQP0-DQP7
Parity Bits
A0-A16
Address Bus
E1#, E2#
Synchronous Bank Enables
BWE#
Byte Write Mode Enable
BW1#-BW8#
Byte Write Enables
CK
Array Clock
GW#
Synchronous Global write
Enable
G#
Asynchronous Output
Enable
Vcc
3.3V Power Supply
Vss
Gnd
PIN NAMES
PIN CONFIGURATION
PIN SYMBOLS
PIN
FUNCTION
PIN
FUNCTION
1
V
SS
37
DQ0
2
V
SS
38
DQ7
3
A0
39
DQ1
4
RFU
40
DQ6
5
A16
41
DQ2
6
A1
42
DQ5
7
A2
43
DQ3
8
A15
44
DQ4
9
A14
45
V
SS
10
A3
46
V
SS
11
A4
47
BW
2
#
12
A13
48
DQP
1
13
A12
49
V
CC
14
A5
50
V
CC
15
A6
51
DQ8
16
A11
52
DQ15
17
A10
53
DQ9
18
A7
54
DQ14
19
A8
55
DQ10
20
A9
56
DQ13
21
V
CC
57
DQ11
22
V
CC
58
DQ12
23
G#
59
V
SS
24
RFU
60
V
SS
25
GW#
61
BW
3
#
26
ADV#
62
DQP
2
27
ADSP#
63
V
CC
28
ADSC#
64
V
CC
29
E
1
#
65
DQ16
30
CK
66
DQ23
31
E
2
#
67
DQ17
32
BWE#
68
DQ22
33
BW
1
#
69
DQ18
34
DQP0
70
DQ21
35
V
CC
71
DQ19
36
V
CC
72
DQ20
PIN
FUNCTION
PIN
FUNCTION
73
V
SS
109
DQ41
74
V
SS
110
DQ46
75
BW
4
#
111
DQ42
76
DQP
3
112
DQ45
77
V
CC
113
DQ43
78
V
CC
114
DQ44
79
DQ24
115
V
SS
80
DQ31
116
V
SS
81
DQ25
117
BW
7
#
82
DQ30
118
DQP
6
83
DQ26
119
V
CC
84
DQ29
120
V
CC
85
DQ27
121
DQ48
86
DQ28
122
DQ55
87
V
SS
123
DQ49
88
V
SS
124
DQ54
89
BW
5
#
125
DQ50
90
DQP
4
126
DQ53
91
V
CC
127
DQ51
92
V
CC
128
DQ52
93
DQ32
129
V
SS
94
DQ39
130
V
SS
95
DQ33
131
BW
8
#
96
DQ38
132
DQP
7
97
DQ34
133
V
CC
98
DQ37
134
V
CC
99
DQ35
135
DQ56
100
DQ36
136
DQ63
101
V
SS
137
DQ57
102
V
SS
138
DQ62
103
BW
6
#
139
DQ58
104
DQP
5
140
DQ61
105
V
CC
141
DQ59
106
V
CC
142
DQ60
107
DQ40
143
V
SS
108
DQ47
144
V
SS
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
EDI2AG272129V
July 1999
Rev 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FUNCTIONAL BLOCK DIAGRAM
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
A
0-16
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
DQ
E#
BW#
E
1
#
BW
1-4
#
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
DQ
E#
BW#
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
DQ
E#
BW#
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
DQ
E#
BW#
U1
U2
U3
U4
E
2
#
BW
5-8
#
DQ
0-31
DQP
0-3
DQ
32-63
DQP
4-7
DQ
32-63
DQP
4-7
DQ
0-31
DQP
0-3
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
EDI2AG272129V
July 1999
Rev 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
3, 6, 7, 10, 11, 14
15, 18, 19, 20, 17
16, 13, 12, 9, 8, 5
A0-A16
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times
around the rising edge of CK. The burst counter generates internal addresses
associated with A0 and A1, during burst and wait cycle.
33, 47, 61, 75,
89, 103, 117, 131
BW1#, BW2#,
BW3#, BW4#,
BW5#, BW6#,
BW7#, BW8#
Input
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle.
BW0# controls DQ0-7 and DQP0, BW1# controls DQ8-15 and DQP1. BW2#
controls DQ16-23 and DQP2. BW3# controls DQ24-31 and DQP3.
BW4# controls DQ32-39 and DQP4. BW5# controls DQ40-47 and DQP5.
BW6#controls DQ48-55 and DQP6. BW7# controls DQ56-64 and DQP7.
32
BWE#
Input
Synchronous
Write Enable: This active LOW input gates byte write operations and must meet the
setup and hold times around the rising edge of CK.
25
GW#
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur
independent of the BWE# and BWx# lines and must meet the setup and hold times
around the rising edge of CK.
30
CK
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock's rising edge.
29, 31
E1#, E2#
Input
Synchronous
Bank Enables: These active LOW inputs are used to enable each individual bank
and to gate ADSP#.
23
G#
Input
Output Enable: This active LOW asynchronous input enables the data output
drivers.
26
ADV#
Input
Synchronous
Address Status Processor: This active LOW input is used to control the internal
burst counter. A HIGH on this pin generates wait cycle (no address advance)
27
ADSP#
Input
Synchronous
Address Status Processor: This active LOW input, along with EL# and EH# being
LOW, causes a new external address to be registered and a READ cycle is initiated
using the new address.
28
ADSC#
Input
Synchronous
Address Status Controller: This active LOW input causes device to be de-selected
or selected along with new external address to be registered.
A READ or WRITE cycle is initiated depending upon write control inputs.
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fi fth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
38, 48, 62,
76, 90, 104,
118, 132
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15.
DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity
bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6# is parity bit for DQ48-55.
DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device confi gured as
a 128K x 64, the parity bits need to be tied to Vss through a 10K ohm resistor.
Various
Vcc
Supply
Core power supply: +3.3V -5%/ + 10%
Various
Vss
Ground
Ground
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
EDI2AG272129V
July 1999
Rev 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1#
E2#
ADSP#
ADSC#
ADV#
GW#
G#
CK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
X
L
X
X
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
X
L
X
X
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
X
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
L
X
X
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
H
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
H
X
H
L
H
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
H
X
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
H
X
H
L
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
H
H
H
H
H
L-H
High-Z
Cur rent
Read Cycle, Suspend Burst; Bank 2
H
X
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H
H
H
H
L-H
High-Z
Cur rent
Read Cycle, Suspend Burst; Bank 1
H
H
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
H
X
H
H
H
H
L-H
High-Z
Cur rent
Read Cycle, Suspend Burst; Bank 2
H
H
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
H
X
H
H
H
H
L-H
High-Z
Cur rent
Write Cycle, Suspend Burst; Bank 1
X
H
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
H
X
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
H
X
H
H
L
X
L-H
D
Current
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