1
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
EDI2CG472128V
July 1999
Rev 1
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FEATURES
4 Megabyte Sync/Sync Burst, Dual Key DIMM
The EDI2CG472128VxxD2 is a Synchronous/Syn chro nous
Burst SRAM, 84 position Dual Key; Double High DIMM (168
contacts) Module, organized as 4x128Kx72. The Module
contains eight (8) Synchronous Burst Ram Devices,
packaged in the industry standard JEDEC 14mmx20mm
TQFP placed on a Multilayer FR4 Sub strate. The module
architecture is defi ned as a Sync/Sync Burst, Flow-Through,
with support for either linear or sequential burst. This
module pro vides High Per for mance, 2-1-1-1 ac cess es
when used in Burst Mode, and used as a Synchronous
Only Mode, provides a high per for mance cost advantage
over BiCMOS aysnchronous device ar chi tec tures.
Synchronous Only operations are performed via strap ping
ADSC# Low, and ADSP# / ADV# High, which pro vides for
Ultra Fast Accesses in Read Mode while pro vid ing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in re la tion
to an externally supplied clock, Registered Address,
Reg is tered Global Write, Registered Enables as well as
an Asynchronous Output enable. This Module has been
defi ned with full fl exibility, which allows individual control
of each of the eight bytes, as well as Quad Words in both
Read and Write Operations.
*This product is under development, is not qualifi ed or characterized and is subject to
change or cancellation without notice.
4x128Kx72 Synchronous, Synchronous Burst
Flow-Through
Architecture
Linear and Sequential Burst Support via MODE pin
Clock Controlled Registered Module Enable (EM#)
Clock Controlled Registered Bank Enables (E1#, E2#,
E3#, E4#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables (BW1# - BW8#)
Clock
Controlled
Registered
Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally
Self-timed
Write
Individual Bank Sleep Mode enables (ZZ
1
, ZZ
2
, ZZ
3
, ZZ
4
)
Gold Lead Finish
3.3V +10% Operation
Access Speed(s): TKHQV=8.5, 10, 12, 15ns
Common
Data
I/O
High Capacitance (30pf) drive, at rated Access Speed
Single
Total
Array
Clock
Multiple
Vcc
and
Gnd
DESCRIPTION
2
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
EDI2CG472128V
July 1999
Rev 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PIN CONFIGURATION
DQ0-DQ63
Input/Output Bus
DQP0-DQP7
Parity Bits
A0-A6
Address Bus
EM#
Module Enable
E1#, E2#, E3#, E4#
Synchronous Bank Enables
BWE#
Byte Write Mode Enable
BWE1#-BW8#
Byte Write Enables
CK
Array Clock
GW#
Synchronous Global
Write Enable
G#
Asynchronous Output Enable
ZZ
1
, ZZ
2,
ZZ
3
, ZZ
4
Blank Sleep Mode Enables
Vcc
3.3V Power Supply
Vss
Ground
PIN NAMES
PIN
FRONT
PIN
BACK
1
V
SS
85
V
SS
2
A0
86
A
17
3
A
16
87
A
1
4
A
2
88
A
15
5
A
14
89
A
3
6
V
CC
90
V
CC
7
A
4
91
A
13
8
A
12
92
A
5
9
A
6
93
A
11
10
A
10
94
A
7
11
V
SS
95
V
SS
12
A
8
96
A
9
13
NC
97
NC
3
14
E
4
#
98
E
1
#
15
E
2
#
99
E
3
#
16
V
SS
100
V
SS
17
MODE
101
CK
18
EM#
102
V
SS
19
GW#
103
G#
20
NC
1
104
BWE#
21
V
CC
105
V
CC
22
BW
4
#
106
BW
2
#
23
BW
3
#
107
BW
1
#
24
BW
8
#
108
BW
6
#
25
BW
7
#
109
BW
5
#
26
ADSC#
110
V
SS
27
ADSP#
111
ADV#
28
V
SS
112
V
SS
29
NC
113
DQP
0
30
V
CC
114
V
CC
31
DQ
0
115
DQ
7
32
DQ
1
116
DQ
6
33
DQ
2
117
DQ
5
34
DQ
3
118
DQ
4
35
V
SS
119
V
SS
36
ZZ
1
120
DQP
1
37
V
CC
121
V
CC
38
DQ
8
122
DQ
15
39
DQ
9
123
DQ
14
40
DQ
10
124
DQ
13
41
DQ
11
125
DQ
12
42
V
SS
126
V
SS
PIN
FRONT
PIN
BACK
43
NC
127
CRFU
44
V
CC
128
V
CC
45
DQ
16
129
DQ
23
46
DQ
17
130
DQ
22
47
DQ
18
131
DQ
21
48
DQ
19
132
DQ
20
49
V
SS
133
V
SS
50
ZZ
2
134
DQP
3
51
V
CC
135
V
CC
52
DQ
24
136
DQ
31
53
DQ
25
137
DQ
30
54
DQ
26
138
DQ
29
55
DQ
27
139
DQ
28
56
V
SS
140
V
SS
57
NC
5
141
DQP
4
58
V
CC
142
V
CC
59
DQ
32
143
DQ
39
60
DQ
33
144
DQ
38
61
DQ
34
145
DQ
37
62
DQ
35
146
DQ
36
63
V
SS
147
V
SS
64
ZZ
3
148
DQP
5
65
V
CC
149
V
CC
66
DQ
40
150
DQ
47
67
DQ
41
151
DQ
46
68
DQ
42
152
DQ
45
69
DQ
43
153
DQ
44
70
V
SS
154
V
SS
71
NC
155
DQP
6
72
V
CC
156
V
CC
73
DQ
48
157
DQ
55
74
DQ
49
158
DQ
54
75
DQ
50
159
DQ
53
76
DQ
51
160
DQ
52
77
V
SS
161
V
SS
78
ZZ
4
162
DQP
7
79
V
CC
163
V
CC
80
DQ
56
164
DQ
63
81
DQ
57
165
DQ
62
82
DQ
58
166
DQ
61
83
DQ
59
167
DQ
60
84
V
SS
168
V
SS
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
EDI2CG472128V
July 1999
Rev 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
FUNCTIONAL BLOCK DIAGRAM
G#
GW#
E
1
#
GW#
G#
E#
DQ
E
3
#
E
2
#
E
4
#
CK
CK
A
0-16
DQ
0-31
DQP
0-3
128Kx36
DQP
DQP
4-7
ZZ
ZZ1
ZZ
2
ZZ
3
ZZ
4
U1
GW#
GW#
G#
E#
DQ
CK
128Kx36
DQP
ZZ
U3
GW#
G#
E#
DQ
CK
128Kx36
DQP
ZZ
U2
G#
E#
DQ
CK
128Kx36
DQP
ZZ
U4
GW#
G#
E#
DQ
CK
128Kx36
DQP
ZZ
GW#
G#
E#
DQ
CK
128Kx36
DQP
ZZ
U6
GW#
G#
E#
DQ
CK
128Kx36
DQP
ZZ
U8
GW#
G#
E#
DQ
CK
128Kx36
DQP
ZZ
U7
DQ
32-63
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
EDI2CG472128V
July 1999
Rev 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
2, 87, 4, 89, 7, 92,
9, 94, 12, 96, 10,
93, 8, 91, 5, 88, 3
A0-A16
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times
around the rising edge of CK. The burst counter generates internal addresses
associated with A0 and A1, during burst and wait cycle.
107, 106, 23, 22,
109, 108, 25, 24
BW1#, BW2#,
BW3#, BW4#,
BW5#, BW6#,
BW7#, BW8#
Input
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle.
BW0/ controls DQ0-7 and DQP0, BW1# controls DQ8-15 and DQP1.
BW2# controls DQ16-23 and DQP2. BW3# controls DQ24-31 and DQP3.
BW4# controls DQ32-39 and DQP4. BW5# controls DQ40-47 and DQP5.
BW6# controls DQ48-55 and DQP6. BW7# controls DQ56-64 and DQP7.
104 BWE#
Input
Synchronous
Write Enable: This active LOW input gates byte write operations and must meet the
setup and hold times around the rising edge of CK.
19
GW#
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent
of the BWE# and BWx# lines and must meet the setup and hold times around the
rising edge of CK.
101
CK
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock's rising edge.
98, 15, 99, 14
E1#, E2#,
E3#, E4#
Input
Synchronous
Bank Enables: These active LOW inputs are used to enable each individual bank
and to gate ADSP#.
103
G#
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
111
ADV#
Input
Synchronous
Address Status Processor: This active LOW input is used to control the internal burst
counter. A HIGH on this pin generates wait cycle (no address advance).
27
ADSP#
Input
Synchronous
Address Status Processor: This active LOW input, along with EL# and EH# being
LOW, causes a new external address to be registered and a READ cycle is initiated
using the new address.
26
ADSC#
Input
Synchronous
Address Status Controller: This active LOW input causes device to be de-selected or
selected along with new external address to be registered.
A READ or WRITE cycle is initiated depending upon write control inputs.
17
MODE
Input Static
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR
BURST. A NC or HIGH on this pin selects INTERLEAVED BURST.
36, 50,
64, 78
ZZ
1
, ZZ
2
,
ZZ
3
, ZZ
4
Input
Asynchronous
Snooze: These active HIGH inputs put the individual banks in low power
consumption standby mode. For normal operation, this input has to be either
LOW or NC (no connect).
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fi fth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
113, 120, 127, 134,
141, 148, 155, 162
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15.
DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity
bit for DQ-32-39. DQP5 is parity bit for DQ40-47. DQP6# is parity bit for DQ48-55.
DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device confi gured as a
128K x 64, the parity bits need to be tied to V
SS
through a 10K ohm resistor.
Various
Vcc
Supply
Core Power supply: +3.3V -5%/+10%
Various
Vss
Ground
Ground
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
EDI2CG472128V
July 1999
Rev 1
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1#
E2#
E3#
E4#
ADSP#
ADSC#
ADV#
GW#
G#
CK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
*
*
X
L
X
X
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
*
*
X
L
X
X
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
*
*
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
*
*
L
X
X
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
*
*
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
*
*
L
X
X
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
*
*
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
*
*
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
*
*
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
*
*
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
*
*
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
*
*
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
*
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
*
*
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
*
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
*
*
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
H
*
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
H
*
*
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
H
*
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
H
*
*
X
H
L
H
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
*
*
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
H
*
*
X
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
*
*
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
H
*
*
X
H
L
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
*
*
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
*
*
H
H
H
H
H
L-H
High-Z
Cur rent
Read Cycle, Suspend Burst; Bank 2
H
X
*
*
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
*
*
H
H
H
H
H
L-H
High-Z
Cur rent
Read Cycle, Suspend Burst; Bank 1
H
H
*
*
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
H
*
*
X
H
H
H
H
L-H
High-Z
Cur rent
Read Cycle, Suspend Burst; Bank 2
H
H
*
*
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
H
*
*
X
H
H
H
H
L-H
High-Z
Cur rent
Write Cycle, Suspend Burst; Bank 1
X
H
*
*
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
H
*
*
X
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
*
*
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
H
*
*
X
H
H
L
X
L-H
D
Current
*All Truth Table Functions Repeat for Bank 3 (E3#) and Bank 4 (E4#)
PDF 
ZIP