1
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
HI-RELIABILITY PRODUCT
EDI816256CA
256Kx16 MONOLITHIC SRAM
FEATURES
s 256Kx16 bit CMOS Static
s Random Access Memory
Access Times of 17, 20, 25, 35ns
Data Retention Function (LPA version)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
s 44 lead JEDEC Approved Revolutionary Pinout
Ceramic SOJ (Package 322)
Ceramic Flatpack (Package 323)
s Single +5V (
10%) Supply Operation
PIN CONFIGURATION
TOP VIEW
September 2000 Rev. 7
PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
0-17
Address Inputs
LB (I/O
1-8
)
Lower-Byte Control (I/O
1-8
)
UB (I/O
9-16
)
Upper-Byte Control (I/O
9-16
)
I/O
1-16
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
V
CC
+5.0V Power
V
SS
Ground
NC
No Connection
The EDI816256CA is a 4 megabit Monolithic CMOS Static RAM.
The EDI816256CA uses 16 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. The device allows upper and lower byte access
by use of the data byte control pins (LB, UB).
The devices are available in a fully hermetic 44 lead ceramic SOJ
and a 44 lead Ceramic Flatpack. The Ceramic SOJ is pin for pin
compatible with the commercially available plastic SOJ. This
allows the user the luxury of designing a board that can be used
for both the commercial and military market.
A Low Power version with Data Retention (EDI816256LPA) is also
available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
2
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI816256CA
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
Parameter
Unit
Voltage on any pin relative to VSS
-0.5 to 7.0
V
Operating Temperature T
A
(Ambient)
Commercial
0 to +70
C
Industrial
-40 to +85
C
Military
-55 to +125
C
Storage Temperature, Plastic
-65 to +125
C
Power Dissipation
1.5
W
Output Current
20
mA
Junction Temperature, T
J
175
C
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
V
CC
4.5
5.0
5.5
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
Vcc +0.5
V
Input Low Voltage
V
IL
-0.3
--
0.8
V
Parameter
Symbol
Condition
Max
Unit
Address Lines
C
I
V
IN
= Vcc or Vss, f = 1.0MHz
12
pF
Data Lines
C
D/Q
V
IN
= Vcc or Vss, f = 1.0MHz
14
pF
These parameters are sampled, not 100% tested.
CAPACITANCE
(T
A
= +25
C)
Parameter
Symbol
Conditions
Units
Min
Max
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
10
A
Output Leakage Current
I
LO
V
I/O
= 0V to V
CC
10
A
Operating Power Supply Current
I
CC1
WE, CS = V
IL
, I
I/O
= OmA, Min Cycle
300
mA
Standby (TTL) Power Supply Current
I
CC2
CS
V
IH
, V
IN
V
IL
, V
IN
V
IH
60
mA
Full Standby Power Supply Current
I
CC3
CS
V
CC
-0.2V
CA
--
25
mA
V
IN
Vcc -0.2V or V
IN
0.2V
LPA
--
16
mA
Output Low Voltage
V
OL
I
OL
= 8.0mA
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0mA
2.4
V
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
DC CHARACTERISTICS
(V
CC
= 5V, V
SS
= 0V, T
A
= -55
C to +125
C)
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 1
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
30pF
480
Vcc
Q
Figure 1
Figure 2
255
5pF
480
Vcc
Q
255
AC TEST CONDITIONS
TRUTH TABLE
CS
WE
OE
LB
UB
Mode
Data I/O
Supply
I/O
1-8
I/O
9-16
Current
H
X
X
X
X
Not Select
High Z
High Z
I
CC2
, I
CC3
L
H
H
X
X
Output
L
X
X
H
H
Disable
L
H
Data Out
High Z
L
H
L
H
L
Read
High Z
Data Out
I
CC1
L
L
Data Out Data Out
L
H
Data In
High Z
L
L
X
H
L
Write
High Z
Data In
I
CC1
L
L
Data In
Data In
3
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI816256CA
AC CHARACTERISTICS READ CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55
C to +125
C)
Symbol
17ns
20ns
25ns
35ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
t
AVAV
t
RC
17
20
25
35
ns
Address Access Time
t
AVQV
t
AA
17
20
25
35
ns
Chip Enable Access Time
t
ELQV
t
ACS
17
20
25
35
ns
Chip Enable to Output in Low Z (1)
t
ELQX
t
CLZ
2
5
5
5
ns
Chip Disable to Output in High Z (1)
t
EHQZ
t
CHZ
0
7
0
7
0
8
0
10
ns
Output Hold from Address Change
t
AVQX
t
OH
0
0
0
0
ns
Output Enable to Output Valid
t
GLQV
t
OE
10
10
12
15
ns
Output Enable to Output in Low Z (1)
t
GLQX
t
OLZ
0
0
0
0
ns
Output Disable to Output in High Z(1)
t
GHQZ
t
OHZ
0
7
0
7
0
8
0
10
ns
LB, UB Access Time
t
UBLQV
t
BA
10
10
12
15
ns
t
LBLQV
LB, UB Enable to Low Z Output
t
UBLQX
t
BLZ
0
0
0
0
0
ns
t
LBLQX
LB, UB Disable to High Z Output
t
UBHQZ
t
BHZ
0
7
0
7
0
8
0
10
ns
t
LBHQZ
NOTE:
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55
C to +125
C)
Symbol
17ns
20ns
25ns
35ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
t
AVAV
t
WC
17
20
25
35
ns
Chip Enable to End of Write
t
ELWH
t
CW
14
15
17
20
ns
t
ELEH
t
CW
14
15
17
20
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
0
ns
t
AVEL
t
AS
0
0
0
0
ns
t
AVUBL
t
AS
0
0
0
0
ns
Address Valid to End of Write
t
AVWH
t
AW
14
15
17
20
ns
t
AVEH
t
AW
14
15
17
20
ns
t
AVUBH
t
AW
14
15
17
20
ns
Write Pulse Width
t
WLWH
t
WP
14
14
15
17
ns
t
WLEH
t
WP
14
14
15
17
ns
Write Recovery Time
t
WHAX
t
WR
0
0
0
0
ns
t
EHAX
t
WR
0
0
0
0
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
0
ns
t
EHDX
t
DH
0
0
0
0
ns
Write to Output in High Z (1)
t
WLQZ
t
WHZ
0
8
0
8
0
8
0
10
ns
Data to Write Time
t
DVWH
t
DW
10
10
12
15
ns
t
DVEH
t
DW
10
10
12
15
ns
Output Active from End of Write (1)
t
WHQX
t
WLZ
0
0
0
0
ns
LB, UB Valid to End of Write
t
LBLLBH
t
BW
14
16
18
20
ns
t
UBLUBH
NOTE:
1. This parameter is guaranteed by design but not tested.
4
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI816256CA
WS32K32-XHX
WRITE CYCLE - CS CONTROLLED
WRITE CYCLE - LB, UB CONTROLLED
TIMING WAVEFORM - READ CYCLE
WRITE CYCLE - WE CONTROLLED
ADDRESS
READ CYCLE 2 (WE HIGH)
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AVAV
t
EHQZ
t
GHQZ
OE
t
LBLQX
t
UBLQX
t
LBHQZ
t
UBHQZ
LB, UB
CS
t
LBLQV
t
UBLQV
DATA I/O
ADDRESS
DATA I/O
READ CYCLE 1 (WE HIGH; OE, CS LOW)
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
ADDRESS
DATA IN
WRITE CYCLE 1, WE CONTROLLED
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
DATA VALID
HIGH
WE
t
LBLLBH
t
UBLUBH
CS
DATA OUT
LB, UB
WRITE CYCLE 2, CS CONTROLLED
t
AVEH
t
ELEH
t
EHAX
t
WLEH
t
DVEH
t
EHDX
t
AVAV
DATA VALID
HIGH
t
LBLLBH
t
UBLUBH
t
AVEL
ADDRESS
DATA IN
WE
LB, UB
CS
DATA OUT
ADDRESS
DATA IN
DATA OUT
WRITE CYCLE 3, LB, UB CONTROLLED
t
AVWH
t
AVUBL
t
WHAV
t
AVUBH
t
WLWH
t
WLQX
t
AVAV
CS
WE
DATA UNDEFINED
DATA VALID
t
UBHAV
t
WHDX
t
DVWH
t
UBLUBH
LB, UB
HIGH Z
HIGH Z
5
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI816256CA
Characteristic
Sym
Conditions
Min
Typ
Max
Units
Low Power Version only
Data Retention Voltage
V
DD
V
DD
= 2.0V
2
V
Data Retention Quiescent Current
I
CCDR
CS
V
DD
-0.2V
2.2
mA
Chip Disable to Data Retention Time (1)
T
CDR
V
IN
V
DD
-0.2V
0
ns
Operation Recovery Time (1)
T
R
or V
IN
0.2V
T
AVAV
ns
DATA RETENTION CHARACTERISTICS (EDI816256LPA ONLY)
(T
A
= -55
C to +125
C)
WS32K32-XHX
DATA RETENTION - CS CONTROLLED
DATA RETENTION, CS CONTROLLED
Data Retention Mode
t
R
Vcc
CS
t
CDR
CS = V
DD
-0.2V
V
DD
4.5V
4.5V
NOTE:
1. This parameter is guaranteed by design but not tested.
* Read Cycle Time
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