1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
EDI88128CS
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s Access Times of 15*, 17, 20, 25, 35, 45, 55ns
s CS and OE Functions for Bus Control
s 2V Data Retention (EDI88128LPS)
s TTL Compatible Inputs and Outputs
s Fully Static, No Clocks
s Organized as 128Kx8
s Commercial, Industrial and Military Temperature Ranges
s Thru-hole and Surface Mount Packages JEDEC Pinout
32 pin Ceramic DIP, 400 mil (Package 102)
32 pin Ceramic DIP, 600 mil (Package 9)
32 lead Ceramic ZIP (Package 100)
32 lead Ceramic SOJ (Package 140)
32 pad Ceramic LCC (Package 141)
32 lead Ceramic Flatpack (Package 142)
s Single +5V (
10%) Supply Operation
32 ZIP
TOP VIEW
February 2000 Rev. 10
PIN DESCRIPTION
I/O
0-7
Data Inputs/Outputs
A
0-16
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
V
CC
Power (+5V
10%)
V
SS
Ground
NC
Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
A
-16
I/O
-7
WE
CS
OE
FIG. 1
PIN CONFIGURATION
The EDI88128CS is a high speed, high performance, 128Kx8
megabit density Monolithic CMOS Static RAM.
The device has eight bi-directional input-output lines to provide
simultaneous access to all bits in a word. An automatic power
down feature permits the on-chip circuitry to enter a very low
standby mode and be brought back into operation at a speed equal
to the address access time.
A Low Power version with 2V Data Retention (EDI88128LPS) is
also available for battery back-up opperation. Military product is
available compliant to MIL-PRF-38535.
* 15ns access time is advanced information, contact factory for availability.
32 DIP
32 SOJ
32 LCC
32 FLATPACK
TOP VIEW
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
V
CC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
I/O
I/O1
I/O2
V
SS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
I/O
I/O1
I/O2
V
SS
2
White Electronic Designs Corporation (602) 437-1520 ww.whiteedc.com
EDI88128CS
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Voltage on any pin relative to Vss
-0.5 to 7.0
V
Operating Temperature T
A
(Ambient)
Commercial
0 to +70
C
Industrial
-40 to +85
C
Military
-55 to +125
C
Storage Temperature, Plastic
-65 to +150
C
Power Dissipation
1.5
W
Output Current
20
mA
Junction Temperature, T
J
175
C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
Vcc +0.5
V
Input Low Voltage
V
IL
-0.3
--
+0.8
V
Parameter
Symbol
Condition
Max
Unit
LCC
Address Lines
C
I
V
IN
= Vcc or Vss, f = 1.0MHz
6
12
pF
Data Lines
C
O
V
OUT
= Vcc or Vss, f = 1.0MHz
8
14
pF
These parameters are sampled, not 100% tested.
CAPACITANCE
(T
A
= +25
C)
TRUTH TABLE
OE
CS
WE
Mode
Output
Power
X
H
X
Standby
High Z
Icc
2
, Icc3
H
L
H
Output Deselect
High Z
Icc
1
L
L
H
Read
Data Out
Icc
1
X
L
L
Write
Data In
Icc
1
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Conditions
Units
Min
Typ
Max
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
--
--
5
A
Output Leakage Current
I
LO
V
I/O
= 0V to V
CC
--
--
10
A
(15-17ns)
--
300
mA
Operating Power Supply Current
I
CC1
WE, CS = V
IL
, I
I/O
= 0mA, Min Cycle
(20ns)
--
225
mA
(25-55ns)
--
200
mA
Standby (TTL) Power Supply Current
I
CC2
CS
V
IH
, V
IN
V
IL
, V
IN
V
IH
(17-55ns)
--
25
mA
(15ns)
--
60
mA
CS
V
CC
-0.2V
CS (17-55ns)
--
3
10
mA
Full Standby Power Supply Current
I
CC3
V
IN
Vcc -0.2V or V
IN
0.2V
CS (15ns)
--
--
15
mA
LPS
--
--
5
mA
Output Low Voltage
V
OL
I
OL
= 8.0mA
--
--
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0mA
2.4
--
--
V
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
DC CHARACTERISTICS
(V
CC
= 5V, T
A
= -55
C to +125
C)
CSOJ,
ZIP, DIP,
Flatpack
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128CS
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 1
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
30pF
480
Vcc
Q
Figure 1
Figure 2
255
5pF
480
Vcc
Q
255
AC TEST CONDITIONS
AC CHARACTERISTICS READ CYCLE (15 to 20ns)
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55
C to +125
C)
Symbol
15ns*
17ns
20ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
t
AVAV
t
RC
15
17
20
ns
Address Access Time
t
AVQV
t
AA
15
17
20
ns
Chip Enable Access Time
t
ELQV
t
ACS
15
17
20
ns
Chip Enable to Output in Low Z (1)
t
ELQX
t
CLZ
3
3
3
ns
Chip Disable to Output in High Z (1)
t
EHQZ
t
CHZ
8
8
10
ns
Output Hold from Address Change
t
AVQX
t
OH
0
0
0
ns
Output Enable to Output Valid
t
GLQV
t
OE
6
6
8
ns
Output Enable to Output in Low Z (1)
t
GLQX
t
OLZ
0
0
0
ns
Output Disable to Output in High Z(1)
t
GHQZ
t
OHZ
6
6
8
ns
Chip Enable to Power Up (1)
t
ELICCH
t
PU
0
0
0
ns
Chip Enable to Power Down (1)
t
EHICCL
t
PD
15
17
20
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS READ CYCLE (25 to 55ns)
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55
C to +125
C)
Symbol
25ns
35ns
45ns
55ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
t
AVAV
t
RC
25
35
45
55
ns
Address Access Time
t
AVQV
t
AA
25
35
45
55
ns
Chip Enable Access Time
t
ELQV
t
ACS
25
35
45
55
ns
Chip Enable to Output in Low Z (1)
t
ELQX
t
CLZ
3
3
3
3
ns
Chip Disable to Output in High Z (1)
t
EHQZ
t
CHZ
12
20
20
20
ns
Output Hold from Address Change
t
AVQX
t
OH
0
0
0
0
ns
Output Enable to Output Valid
t
GLQV
t
OE
10
15
20
25
ns
Output Enable to Output in Low Z (1)
t
GLQX
t
OLZ
0
0
0
0
ns
Output Disable to Output in High Z(1)
t
GHQZ
t
OHZ
10
15
20
20
ns
Chip Enable to Power Up (1)
t
ELICCH
t
PU
0
0
0
0
ns
Chip Enable to Power Down (1)
t
EHICCL
t
PD
25
35
45
55
ns
1. This parameter is guaranteed by design but not tested.
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White Electronic Designs Corporation (602) 437-1520 ww.whiteedc.com
EDI88128CS
AC CHARACTERISTICS WRITE CYCLE (12 to 20ns)
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55
C to +125
C)
Symbol
15ns*
17ns
20ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
t
AVAV
t
WC
15
17
20
ns
Chip Enable to End of Write
t
ELWH
t
CW
12
13
15
ns
t
ELEH
t
CW
12
13
15
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
ns
t
AVEL
t
AS
0
0
0
ns
Address Valid to End of Write
t
AVWH
t
AW
12
13
15
ns
t
AVEH
t
AW
12
13
15
ns
Write Pulse Width
t
WLWH
t
WP
12
13
15
ns
t
WLEH
t
WP
12
13
15
ns
Write Recovery Time
t
WHAX
t
WR
0
0
0
ns
t
EHAX
t
WR
0
0
0
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
ns
t
EHDX
t
DH
0
0
0
ns
Write to Output in High Z (1)
t
WLQZ
t
WHZ
0
8
0
8
0
10
ns
Data to Write Time
t
DVWH
t
DW
7
7
10
ns
t
DVEH
t
DW
7
7
10
ns
Output Active from End of Write (1)
t
WHQX
t
WLZ
3
3
3
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS WRITE CYCLE (25 to 55ns)
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55
C to +125
C)
Symbol
25ns
35ns
45ns
55ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
t
AVAV
t
WC
25
35
45
55
ns
Chip Enable to End of Write
t
ELWH
t
CW
20
25
35
45
ns
t
ELEH
t
CW
20
25
35
45
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
0
ns
t
AVEL
t
AS
0
0
0
0
ns
Address Valid to End of Write
t
AVWH
t
AW
20
25
35
45
ns
t
AVEH
t
AW
20
25
35
45
ns
Write Pulse Width
t
WLWH
t
WP
20
30
30
35
ns
t
WLEH
t
WP
20
30
30
35
ns
Write Recovery Time
t
WHAX
t
WR
0
0
5
5
ns
t
EHAX
t
WR
0
0
5
5
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
0
ns
t
EHDX
t
DH
0
0
0
0
ns
Write to Output in High Z (1)
t
WLQZ
t
WHZ
0
10
0
13
0
15
0
20
ns
Data to Write Time
t
DVWH
t
DW
15
20
20
25
ns
t
DVEH
t
DW
15
20
20
25
ns
Output Active from End of Write (1)
t
WHQX
t
WLZ
3
3
3
3
ns
1. This parameter is guaranteed by design but not tested.
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128CS
ADDRESS
DATA I/O
READ CYCLE 1 (WE HIGH; OE, CS LOW)
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
ADDRESS
DATA I/O
READ CYCLE 2 (WE HIGH)
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AVAV
t
EHQZ
t
GHQZ
OE
Icc
CS
t
ELICCH
t
EHICCL
WS32K32-XHX
FIG. 2
TIMING WAVEFORM - READ CYCLE
FIG. 4
WRITE CYCLE - CS CONTROLLED
FIG. 3
WRITE CYCLE - WE CONTROLLED
ADDRESS
DATA IN
WRITE CYCLE 2, CS CONTROLLED
t
AVEH
t
ELEH
t
EHAX
t
WLEH
t
DVEH
t
EHDX
t
AVAV
DATA VALID
HIGH Z
WE
CS
DATA OUT
t
AVEL
ADDRESS
DATA IN
WRITE CYCLE 1, WE CONTROLLED
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
DATA VALID
HIGH Z
WE
CS
DATA OUT
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