1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
EDI88128C
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s Access Times of 70, 85, 100ns
s Available with Single Chip Selects (EDI88128) or Dual Chip
Selects (EDI88130)
s 2V Data Retention (LP Versions)
s CS and OE Functions for Bus Control
s TTL Compatible Inputs and Outputs
s Fully Static, No Clocks
s Organized as 128Kx8
s Industrial, Military and Commercial Temperature Ranges
s Thru-hole and Surface Mount Packages JEDEC Pinout
32 pin Ceramic DIP, 0.6 mils wide (Package 9)
32 lead Ceramic ZIP (Package 100)
32 lead Ceramic SOJ (Package 140)
s Single +5V (
10%) Supply Operation
32 ZIP
TOP VIEW
July 1999 Rev. 13
PIN DESCRIPTION
I/O
0-7
Data Inputs/Outputs
A
0-16
Address Inputs
WE
Write Enable
CS
1
, CS
2
Chip Selects
OE
Output Enable
V
CC
Power (+5V
10%)
V
SS
Ground
NC
Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
A
-16
I/O
-7
WE
CS
1
CS
2
OE
FIG. 1
PIN CONFIGURATION
The EDI88128C is a high speed, high performance, Monolithic
CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an additional chip
select line (CS
2
) which will automatically power down the device
when proper logic levels are applied.
The second chip select line (CS
2
) can be used to provide system
memory security during power down in non-battery backed up
systems and simplifiy decoding schemes in memory banking
where large multiple pages of memory are required.
The EDI88128C and the EDI88130C have eight bi-directional in-
put-output lines to provide simultaneous access to all bits in a
word. An automatic power down feature permits the on-chip
circuitry to enter a very low standby mode and be brought back
into operation at a speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a 2V data
retention function for battery back-up opperation. Military prod-
uct is available compliant to Appendix A of MIL-PRF-38535.
32 DIP
32 SOJ
TOP VIEW
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
V
CC
A15
NC/CS2*
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
I/O
I/O1
I/O2
V
SS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
A15
NC/CS2*
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A
I/O
I/O1
I/O2
V
SS
* Pin 30 is NC for 88128 or CS
2
for 88130.
2
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128C
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Voltage on any pin relative to Vss
-0.5 to 7.0
V
Operating Temperature T
A
(Ambient)
Commercial
0 to +70
C
Industrial
-40 to +85
C
Military
-55 to +125
C
Storage Temperature, Plastic
-65 to +150
C
Power Dissipation
1
W
Output Current
20
mA
Junction Temperature, T
J
175
C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Supply Voltage
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
--
Vcc +0.5
V
Input Low Voltage
V
IL
-0.3
--
+0.8
V
Parameter
Symbol
Condition
Max
Unit
Address Lines
C
I
V
IN
= Vcc or Vss, f = 1.0MHz
12
pF
Input/Output Lines
C
O
V
OUT
= Vcc or Vss, f = 1.0MHz
14
pF
These parameters are sampled, not 100% tested.
CAPACITANCE
(T
A
= +25
C)
TRUTH TABLE
OE
CS
1
CS
2
WE
Mode
Output
Power
X
H
X
X
Standby
High Z
Icc
2
, Icc
3
X
X
L
X
Standby
High Z
Icc
2
, Icc
3
X
X
L
X
Output Deselect
High Z
Icc
1
H
L
H
H
Output Deselect
High Z
Icc
1
L
L
H
H
Read
Data Out
Icc
1
X
L
H
L
Write
Data In
Icc
1
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Conditions
Units
Min
Typ
Max
Input Leakage Current
I
LI
V
IN
= 0V to V
CC
-5
--
+5
A
Output Leakage Current
I
LO
V
I/O
= 0V to V
CC
, CS
1
V
IH
and/or CS
2
V
IL
-10
--
+10
A
Operating Power Supply Current
I
CC1
WE, CS
1
= V
IL
, I
I/O
= 0mA, Min Cycle
(70-85ns)
--
120
mA
CS
2
= V
IH
(100ns)
--
110
mA
Standby (TTL) Power Supply Current
I
CC2
CS
1
V
IH
and/or CS
2
V
IL
, V
IN
V
IH
or
V
IL
--
10
mA
CS
1
V
CC
-0.2V and/or CS
2
Vcc +0.2V
C
--
1
5
mA
Full Standby Power Supply Current
I
CC3
V
IN
Vcc -0.2V or V
IN
0.2V
LP
--
--
1
mA
Output Low Voltage
V
OL
I
OL
= 2.1mA
--
--
0.4
V
Output High Voltage
V
OH
I
OH
= -1.0mA
2.4
--
--
V
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
DC CHARACTERISTICS
(V
CC
= 5V, T
A
= +25
C)
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128C
Input Pulse Levels
V
SS
to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
Figure 1
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
30pF
480
Vcc
Q
Figure 1
Figure 2
255
5pF
480
Vcc
Q
255
AC TEST CONDITIONS
AC CHARACTERISTICS READ CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0
C to +70
C)
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
t
AVAV
t
RC
70
85
100
ns
Address Access Time
t
AVQV
t
AA
70
85
100
ns
Chip Select Access Time
t
ELQV
t
ACS
70
85
100
ns
t
SHQV
t
ACS
70
85
100
ns
Chip Select to Output in Low Z (1)
t
ELQX
t
CLZ
3
3
3
ns
t
SHQX
t
CLZ
3
3
3
ns
Chip Disable to Output in High Z (1)
t
EHQZ
t
CHZ
0
30
0
30
0
30
ns
t
SLQZ
t
CHZ
0
30
0
30
0
30
ns
Output Hold from Address Change
t
AVQX
t
OH
3
3
3
ns
Output Enable to Output Valid
t
GLQV
t
OE
25
30
50
ns
Output Enable to Output in Low Z (1)
t
GLQX
t
OLZ
0
0
0
ns
Output Disable to Output in High Z (1)
t
GHQZ
t
OHZ
0
30
0
30
0
30
ns
1. This parameter is guaranteed by design but not tested.
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128C
AC CHARACTERISTICS WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= 0
C to +70
C)
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
t
AVAV
t
WC
70
85
100
ns
Chip Select to End of Write
t
ELWH
t
CW
60
75
85
ns
t
ELEH
t
CW
60
75
85
ns
t
SHWH
t
CW
60
75
85
ns
t
SHSL
t
CW
60
75
85
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
ns
t
AVEL
t
AS
0
0
0
ns
t
AVSH
t
AS
0
0
0
ns
Address Valid to End of Write
t
AVWH
t
AW
60
75
85
ns
Write Pulse Width
t
WLWH
t
WP
35
70
80
ns
t
WLEH
t
WP
35
70
80
ns
t
WLSL
t
WP
35
70
80
ns
Write Recovery Time
t
WHAX
t
WR
5
5
5
ns
t
EHAX
t
WR
5
5
5
ns
t
SLAX
t
WR
5
5
5
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
ns
t
EHDX
t
DH
0
0
0
ns
t
SLDX
t
DH
0
0
0
ns
Write to Output in High Z (1)
t
WLQZ
t
WHZ
0
30
0
35
0
40
ns
Data to Write Time
t
DVWH
t
DW
35
40
40
ns
t
DVEH
t
DW
35
40
40
ns
t
DVSL
t
DW
35
40
40
ns
Output Active from End of Write (1)
t
WHQX
t
WLZ
5
5
5
ns
1. This parameter is guaranteed by design but not tested.
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI88128C
ADDRESS
DATA I/O
READ CYCLE 1 (WE HIGH; OE, CS LOW)
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1
ADDRESS 2
DATA 1
ADDRESS
DATA I/O
READ CYCLE 2 (WE HIGH)
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
SHQV
t
SHQX
t
GLQX
t
AVAV
t
EHQZ
t
GHQZ
OE
CS
2
t
SLQZ
CS
1
WS32K32-XHX
FIG. 2
TIMING WAVEFORM - READ CYCLE
FIG. 4
WRITE CYCLE2
FIG. 3
WRITE CYCLE 1
ADDRESS
DATA IN
WRITE CYCLE 2 - EARLY WRITE, CS
1
CONTROLLED
t
WLEH
t
EHAX
t
ELEH
t
DVEH
t
EHDX
t
AVAV
DATA VALID
WE
CS
1
t
AVEL
CS
2
ADDRESS
DATA IN
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
DATA VALID
HIGH Z
WE
t
SHWH
CS
1
DATA OUT
CS
2
WRITE CYCLE 3
ADDRESS
DATA IN
WRITE CYCLE 3 - EARLY WRITE, CS
2
CONTROLLED
t
WLSL
t
SLAX
t
SHSL
t
DVSL
t
SLDX
t
AVAV
DATA VALID
WE
CS
1
t
AVSH
CS
2
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