1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Oct. 2002 Rev. 0A
ECO #15735
EDI8F32259V
The EDI8F32259V is a high speed 8Mb Static RAM module
organized as 256K words by 32 bits. This module is constructed
from eight 256Kx4 Static RAMs in SOJ packages on an epoxy
laminate (FR4) board.
Four chip enables (E-E3) are used to independently enable the
four bytes. Reading or writing can be executed on individual
bytes or any combination of multiple bytes through proper use of
selects.
The EDI8F32259V is offered in 72 pin ZIP/SIMM package which
enables eight megabits of memory to be placed in less than 1.3
square inches of board space.
All inputs and outputs are TTL compatible and operate from a
single 3.3V supply. Fully asynchronous circuitry requires no
clocks or refreshing for operation and provides equal access and
cycle times for ease of use.
The ZIP and SIMM modules contain four PD (Presence Detect)
pins which are used to identify module memory density in appli-
cations where alternate modules can be interchanged.
FEATURES
n 256Kx32 bit CMOS Static RAM
Access Times: 12, 15, 20, and 25ns
Individual Byte Selects
Fully Static, No Clocks
TTL Compatible I/O
n High Density Package with JEDEC Standard Pinouts
72 Pin SIMM No. 175 (Angle)
72 Pin ZIP No. 176
72 Pin SIMM, No. 354 (Straight)
n Single +3.3V (10%) Supply Operation
PIN NAMES
PIN CONFIGURATIONS AND BLOCK DIAGRAM
256Kx32 Static RAM CMOS, High Speed Module
DESCRIPTION
FIG. 1
PD 1,2 = VSS
PD 3,4 = Open
0
A-A17
Address Inputs
E-E3
Chip Enables
W,
Write Enables
G
Output Enable
DQ-DQ31
Common Data Input/Output
VCC
Power (3.3V10%)
VSS
Ground
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Oct. 2002 Rev. 0A
ECO #15735
EDI8F32259V
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
These parameters are sampled, not 100% tested.
AC TEST CONDITIONS
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
TRUTH TABLE
CAPACITANCE
DC ELECTRICAL CHARACTERISTICS
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
VCC
3.0
3.3
3.6
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
--
VCC+0.3V
V
Input Low Voltage
VIL
-0.3
--
0.8
V
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
1TTL, CL = 30pF
E
W
G
Mode
Output
Power
H
X
X
Standby
HIGH Z
ICC3
L
H
L
Read
DOUT
ICC1
L
L
X
Write
DIN
ICC1
L
H
H
Output Deselect
HIGH Z
ICC1
Parameter
Sym
Max
Unit
Address Lines
CI
60
pF
Data Lines
CD/Q
20
pF
Chip Enable Line
CC
20
pF
Write Control Line
CN
60
pF
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Sym
Conditions
Min
Max
Units
12-25
ns
Operating Power Supply Current
ICC1
W, E = VIL, II/O = 0mA, Min Cycle
800
mA
Standby (TTL) Power Supply Current
ICC2
E VIH, VIN VIL or VIN VIH
240
mA
Full Standby Power Supply Current
ICC3
E VCC-0.2V
40
mA
CMOS
VIN VCC-0.2V or VIN 0.2V
Input Leakage Current
ILI
VIN = 0V to VCC
--
80
A
Output Leakage Current
ILO
V I/O = 0V to VCC
--
20
A
Output High Voltage
VOH
IOH = -4.0mA
2.4
V
Output Low Voltage
VOL
IOL = 8.0mA
0.4
V
Voltage on any pin relative to VSS
-0.5V to 4.6V
Operating Temperature TA (Ambient)
Commercial
0C to +70C
Storage Temperature, Plastic
-55C to +125C
Power Dissipation
2.5 Watts
Output Current
20 mA
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Oct. 2002 Rev. 0A
ECO #15735
EDI8F32259V
AC CHARACTERISTICS READ CYCLE
READ CYCLE 2 - W HIGH
Note 1: Parameter guaranteed, but not tested.
READ CYCLE 1 - W HIGH, G, E LOW
Symbol
12ns
15ns
20ns
25ns
Parameter
JEDEC
Alt.
Min Max
Min
Max Min
Max Min
Max Units
Read Cycle Time
TAVAV
TRC
12
15
20
25
ns
Address Access Time
TAVQV
TAA
12
15
20
25
ns
Chip Enable Access
TELQV TACS
12
15
20
25
ns
Chip Enable to Output in Low Z (1)
TELQX TCLZ
3
3
3
3
ns
Chip Disable to Output in High Z (1)
TEHQZ TCHZ
6
7
9
9
ns
Output Hold from Address Change
TAVQX TOH
3
3
3
3
ns
Output Enable to Output Valid
TGLQV TOE
6
7
9
9
ns
Output Enable to Output in Low Z (1)
TGLQX TOLZ
0
0
0
0
ns
Output Disable to Output in High Z (1)
TGHQZ TOHZ
6
7
9
9
ns
FIG. 2
FIG. 3
ADDRESS 1
ADDRESS 2
TAVAV
DATA 1
DATA 2
TAVQV
TAVQX
A
Q
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Oct. 2002 Rev. 0A
ECO #15735
EDI8F32259V
AC CHARACTERISTICS WRITE CYCLE
Note 1: Parameter guaranteed, but not tested.
Symbol
12ns
15ns
20ns
25ns
Parameter
JEDEC
Alt.
Min Max
Min
Max Min
Max Min
Max
Units
Write Cycle Time
TAVAV TWC
12
15
20
25
ns
Chip Enable to End of Write
TELWH TCW
8
9
10
10
ns
TWLEH TCW
8
9
10
10
ns
Address Setup Time
TAVWL
TAS
0
0
0
0
ns
TAVEL
TAS
0
0
0
0
ns
Address Valid to End of Write
TAVWH TAW
8
9
10
10
ns
TAVEH TAW
8
9
10
10
ns
Write Pulse Width
TWLWH TWP
8
9
10
10
ns
TELEH TWP
8
9
10
10
ns
Write Recovery Time
TWHAX TWR
0
0
0
0
ns
TEHAX TWR
0
0
0
0
ns
Data Hold Time
TWHDX TDH
3
3
3
3
ns
TEHDX TDH
3
3
3
3
ns
Write to Output in High Z (1)
TWLQZ TWHZ
0
6
0
7
0
9
0
9
ns
Data to Write Time
TDVWH TDW
6
7
8
8
ns
TDVEH TDW
6
7
8
8
ns
Output Active from End of Write (1)
TWHQX TWLZ
3
3
3
3
ns
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Oct. 2002 Rev. 0A
ECO #15735
EDI8F32259V
WRITE CYCLE 1 - W CONTROLLED
WRITE CYCLE 2 - E CONTROLLED
E
A
TAVAV
TELWH
TAVWH
TWLWH
TAVWL
TWHAX
W
HIGH Z
DATA VALID
TWLQZ
TWHQX
TDVWH
TWHDX
Q
D
A
TAVEL
HIGH Z
TAVAV
TELEH
E
TAVEH
TEHAX
W
TWLEH
TEHDX
TDVEH
Q
DATA VALID
D
PDF 
ZIP