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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 8A
ECO #15405
EDI8F81024C
The EDI8F81024C is a 8Mb CMOS Static RAM based on eight
128Kx8 Static RAMs mounted on a multi-layered epoxy laminate
(FR4) substrate.
A version featuring Low Power with Data Retention (EDI8F81024LP)
is also available.
The EDI8F81024C is offered in a double sided, 36 pin single-in-
line Package (SIP). Surface mount SIP technology is a cost
effective solution to very high packing density requirements.
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous, the EDI8F81024C re-
quires no clocks or refreshing for operation.
P
IN
C
ONFIGURATIONS
AND
B
LOCK
D
IAGRAM
P
IN
N
AMES
FEATURES
n 1024Kx8 bit CMOS Static
n Random Access Memory
Access Times 70 thru 100ns
Data Retention Function (EDI8F81024LP)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
n High Density Packaging
36 Pin SIP, No. 62
n Single +5V (10%) Supply Operation
1Mx8 Static RAM CMOS, Module
DESCRIPTION
A-A19
Address Inputs
E
Chip Enable
W
Write Enable
G
Output Enable
DQ-DQ7
Common Data Input/Output
VCC
Power (+5V10%)
VSS
Ground
NC
No Connection
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 8A
ECO #15405
EDI8F81024C
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
DC E
LECTRICAL
C
HARACTERISTICS
*Typical: TA = 25C, VCC = 5.0V
C
APACITANCE
T
RUTH
T
ABLE
(f=1.0MHz, VIN=VCC or VSS)
These parameters are sampled, not 100% tested.
AC T
EST
C
ONDITIONS
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
Voltage on any pin relative to VSS
-0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial
0C to +70C
Industrial
-40C to +85C
Storage Temperature
Plastic
-55C to +125C
Power Dissipation
1 Watt
Output Current
20 mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
VCC
4.5
5.0
5.5
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
--
6.0
V
Input Low Voltage
VIL
-0.3
--
0.8
V
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
1TTL, CL =100pF
Parameter
Sym
Conditions
Min
Typ*
Max
Units
Operating Power
ICC1
W, E = VIL, II/O = 0mA,
--
80
130
mA
Supply Current
Min Cycle
Standby (TTL) Power
ICC2
E VIH, VIN VIL
--
40
90
mA
Supply Current
VIN VIH
Full Standby Power
ICC3
E VCC-0.2V
C
--
10
20
mA
Supply Current (CMOS)
VIN VCC-0.2V or
LP
--
400
950
A
VIN 0.2V
Input Leakage Current
ILI
VIN = 0V to VCC
--
--
10
A
Output Leakage Current
ILO
V I/O = 0V to VCC
--
--
10
A
Output High Voltage
VOH
IOH = -1.0mA
2.4
--
--
V
Output Low Voltage
VOL
IOL = 2.1mA
--
--
0.4
V
G
E
W
Mode
Output
Power
X
H
X
Standby
High Z
ICC2, ICC3
H
L
H
Output Deselect
High Z
ICC1
L
L
H
Read
DOUT
ICC1
X
L
L
Write
DIN
ICC1
Parameter
Sym
Max
Unit
Input Capacitance
(Except DQ Pins)
CI
58
pF
Capacitance (DQ Pins)
CD/Q
43
pF
Input (E) Control Lines
CC
10
pF
Input (W) Line (G)
CW
60
pF
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 8A
ECO #15405
EDI8F81024C
AC C
HARACTERISTICS
R
EAD
C
YCLE
R
EAD
C
YCLE
2 - W H
IGH
R
EAD
C
YCLE
1 - W H
IGH
, G, E L
OW
Note: Parameter guaranteed, but not tested.
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min Max
Min
Max Min
Max Units
Read Cycle Time
TAVAV
TRC
70
85
100
ns
Address Access Time
TAVQV
TAA
70
85
100
ns
Chip Enable Access Time
TELQV TACS
70
85
100
ns
Chip Enable to Output in Low Z (1)
TELQX TCLZ
5
5
5
ns
Chip Disable to Output in High Z (1)
TEHQZ TCHZ
30
35
40
ns
Output Hold from Address Change
TAVQX TOH
3
3
3
ns
Output Enable to Output Valid
TGLQV TOE
40
45
50
ns
Output Enable to Output in Low Z (1)
TGLQX TOLZ
0
0
0
ns
Output Disable to Output in High Z(1)
TGHQZ TOHZ
30
35
40
ns
ADDRESS 1
ADDRESS 2
TAVAV
DATA 1
DATA 2
TAVQV
TAVQX
A
Q
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 8A
ECO #15405
EDI8F81024C
AC C
HARACTERISTICS
W
RITE
C
YCLE
W
RITE
C
YCLE
1 - W C
ONTROLLED
Note 1: Parameter guaranteed, but not tested.
Symbol
70ns
85ns
100ns
Parameter
JEDEC
Alt.
Min Max
Min
Max Min
Max Units
Write Cycle Time
TAVAV TWC
70
85
100
ns
Chip Enable to End of Write
TELWH TCW
65
70
80
ns
TELEH TCW
65
70
80
ns
Address Setup Time
TAVWL
TAS
0
0
0
ns
TAVEL
TAS
0
0
0
ns
Address Valid to End of Write
TAVWH TAW
65
70
80
ns
TAVEH TAW
65
70
80
ns
Write Pulse Width
TWLWH TWP
65
70
80
ns
TWLEH TWP
65
70
80
ns
Write Recovery Time
TWHAX TWR
0
0
0
ns
TEHAX TWR
0
0
0
ns
Data Hold Time
TWHDX TDH
0
0
0
ns
TEHDX TDH
0
0
0
ns
Write to Output in High Z (1)
TWLQZ TWHZ
0
30
0
35
0
40
ns
Data to Write Time
TDVWH TDW
30
35
40
ns
TDVEH TDW
30
35
40
ns
Output Active from End of Write (1)
TWHQX TWLZ
5
5
5
ns
E
A
TAVAV
TELWH
TAVWH
TWLWH
TAVWL
TWHAX
W
HIGH Z
DATA VALID
TWLQZ
TWHQX
TDVWH
TWHDX
Q
D
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 8A
ECO #15405
EDI8F81024C
W
RITE
C
YCLE
2 - E C
ONTROLLED
D
ATA
R
ETENTION
E C
ONTROLLED
Data Retention
Characteristics
Note 1: Parameter guaranteed, but not tested.
* Read Cycle Time
Characteristic
Sym
Test Conditions
VDD
Min
Typ
Max
Unit
70C
85C
Data Retention Voltage
VDD
VDD = 0.2V
2
--
--
--
V
Data Retention Quiescent Current
ICCDR
E VDD -0.2V
2V
--
25
300
400
A
VIN VDD -0.2V
3V
--
50
450
550
A
Chip Disable to Data Retention Time (1) TCDR
or VIN 0.2V
0
--
--
--
ns
Operation Recovery Time (1)
TR
TAVAV*
--
--
--
ns
A
TAVEL
HIGH Z
TAVAV
TELEH
E
TAVEH
TEHAX
W
TWLEH
TEHDX
TDVEH
Q
DATA VALID
D
VCC
TR
DATA RETENTION MODE
E
TCDR
E
VDD-0.2V
VDD
4.5V
4.5V
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