1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Dec. 2002 Rev. 1
ECO #15721
EDI8L21664V
FEATURES
n DSP Memory Solution
Texas Instruments TMS320C54x
n 3.3V Operating Supply Voltage
n Access Times of 10, 12 and 15ns
n Single Write Control and Output Enable Lines
n One Chip Enable Line per Memory Bank
n 50% Space Savings vs. Monolithic TSOPs
n Upgrade Path Available in Same Footprint
n Multiple VCC and VSS Pins
n Reduced Inductance and Capacitance
n 74 pin BGA, JEDEC MO-151
TMS320C54x External SRAM Memory Solution
PIN CONFIGURATION
The EDI8L21664VxxBC is a 3.3V, 2x64Kx16 SRAM constructed
with two 64Kx16 die mounted on a multi-layer laminate substrate.
The device is packaged in a 74 lead, 15mm by 15mm, BGA.
Operating with a 3.3V power supply and with access times as fast
as 10ns, the device allows the user to develop a fast external
memory for Texas Instuments' TMS320C54x DSP.
The device consists of two separate banks of 64Kx16 of memory.
Each bank has a separate Chip Enable pin and higher order
address select pin. Bank 'A' is controlled using CE1\ and A15A.
Bank 'B' is controlled using CE2\ and A15B. The two banks have
common I/Os (DQ0-15) and control lines (WE\ and G\).
DESCRIPTION
VSS
VCC
VCC
DQ15 DQ14 VCC
DQ13 DQ11
DQ9
DQ8
N/C
VSS
VCC
VCC
VSS
VSS
VCC
DQ12 DQ10
DQ4
VCC
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VCC
A15A CE1\
DQ3
DQ7
N/C
WE\
DQ5
DQ0
VSS
CE2\
DQ6
DQ1
VSS
A14
VCC
DQ2
N\C
VSS
A12
VCC
A10
A8
VSS
A6
A4
A2
A0
G\
A15B A13
VCC
A11
A9
VSS
A7
VSS
A5
A3
A1
1
2 3 4 5 6 7 8 9
10
11
1
2 3 4 5 6 7 8 9
10
11
A
B
C
D
E
F
G
H
J
K
L
A
B
C
D
E
F
G
H
J
K
L
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Dec. 2002 Rev. 1
ECO #15721
EDI8L21664V
P
IN
D
ESCRIPTIONS
DQ0-DQ15
A0-A14
G\
WE\
CE1\
A15 A
CE2\
A15 B
64K x 16
SRAM
64K x 16
SRAM
BLOCK DIAGRAM
Pin
Symbol
Type
Description
A0-A14
Input
Addresses
A15A
Input
Addresses: A15 on Bank 'A' of memory
A15B
Input
Addresses: A15 on Bank 'B' of memory
WE\
Input
Write Enable: This active LOW input allows a full 16-bit WRITE to occur.
CE1\
Input
Chip Enable: This active LOW input is used to enable the 'A' Bank of the device.
CE2\
Input
Chip Enable: This active LOW input is used to enable the 'B' Bank of the device.
G\
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
Various
DQ0-15
Input/Output Data Inputs/Outputs
Various
Vcc
Supply
Core power supply: +3.3V -5%/+10%
Various
Vss
Ground
Ground
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Dec. 2002 Rev. 1
ECO #15721
EDI8L21664V
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
(f=1.0MHz, VIN=VCC or VSS)
*Stress greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
AC T
EST
C
ONDITIONS
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
C
APACITANCE
Figure 1 - Output Load Equivalent
DC E
LECTRICAL
C
HARACTERISTICS
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Sym
Conditions
Min
Max
Units
Power Supply
ICC1
Device Selected; all inputs VIL or VIH;
-10ns
380
mA
Current: Operating
cycle time tKC MIN;
-12ns
360
VCC=MAX; outputs open
-15ns
260
CMOS Standby
ISB2 Device deselected; VCC=MAX; all inputs VSS +0.2
60
mA
or VCC -0.2; all inputs static; CLK frequency = 0
TTL Standby
ISB3
Device deselected; all inputs VIL or VIH;
120
mA
all inputs static; VCC=MAX; CLK frequency = 0
Input Leakage Current
ILI
0VVINVCC
-5
5
A
Output Leakage Current
ILO
Output(s) disabled, 0VVOUTVCC
--5
5
A
Output High Voltage
VOH
IOH = -4.0mA
2.4
V
Output Low Voltage
VOL
IOL = 4.0mA
0.4
V
Voltage on Vcc Supply Relative to Vss -0.5V to 4.6V
V
IN
-0.5V to Vcc+0.5V
Storage Temperature
-55C to +125C
Junction Temperature
+125C
Power Dissipation
3 Watts
Short Circuit Output Current (per I/O)
50 mA
Parameter
Sym
Max
Unit
Address Lines
CA
8
pF
Data Lines
CD/Q
17
pF
Control Lines
CC
15
pF
Input Pulse Levels
VSS to 3.0V
Input Rise and Fall Times (Max)
1.5ns
Input and Output Timing Levels
1.5V
Output Load
See Figure 1
Description
Sym
Min
Max
Units
Input High Voltage
VIH
2.2
Vcc+0.5
V
Input Low Voltage
VIL
-0.3
0.8
V
Supply Voltage
Vcc
3.0
3.6
V
50
Vt = 1.25V
Output
Z0 = 50
Z0 = 50
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Dec. 2002 Rev. 1
ECO #15721
EDI8L21664V
R
EAD
C
YCLE
2 - W H
IGH
R
EAD
C
YCLE
1 - W H
IGH
, G, E L
OW
AC E
LECTRICAL
C
HARACTERISTICS
ADDRESS 1
ADDRESS 2
TAVAV
DATA 1
DATA 2
TAVQV
TAVQX
A
Q
TGHQZ
TELQV
TELQX
E
G
Q
TEHQZ
A
TAVAV
TGLQV
TGLQX
TAVQV
Symbol
10ns
12ns
15ns
Read Cycle
Min Max
Min
Max Min
Max Units
Read Cycle Time
tAVAV
10
12
15
ns
Address Access Time
tAVQV
10
12
15
ns
Chip Enable Access
tELQV
10
12
15
ns
Output Hold from Address Change
tAVQX
3
4
4
ns
Chip Enable to Output in Low-Z
tELQX
3
4
4
ns
Chip Disable to Output in High-Z
tEHQZ
5
6
7
ns
Output Enable access time
tGLQV
5
6
7
ns
Output Enable to Output in Low-Z
tGLQX
0
0
0
ns
Output Disable to Output in High-Z
tGHQZ
5
6
7
ns
Write Cycle
Write Cycle Time
tAVAV
10
12
15
ns
Chip Enable to End of Write
tELWH
8
8
9
ns
Address valid to End of Write,
with G\ HIGH
tAVGHWH
8
8
9
ns
Address Setup Time
tAVWL
0
0
0
ns
Address Hold from End of Write
tAVWH
0
0
0
ns
Write Pulse Width
tWLWH
10
10
11
ns
Write Pulse Width, with G\ HIGH
tWLGHWH
8
8
9
ns
Data Setup Time
tDVWH
6
6
7
ns
Data Hold Time
tWHDX
0
0
0
ns
Write Disable to Output in Low-Z
tWHQX
3
4
5
ns
Write Enable to Output in High-Z
tWLQZ
5
6
7
ns
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Dec. 2002 Rev. 1
ECO #15721
EDI8L21664V
W
RITE
C
YCLE
2 - E C
ONTROLLED
W
RITE
C
YCLE
1 - W C
ONTROLLED
A
TAVEL
HIGH Z
TAVAV
TELEH
E
TAVEH
TEHAX
W
TWLEH
TEHDX
TDVEH
Q
DATA VALID
D
E
A
TAVAV
TELWH
TAVWH
TWLWH
TAVWL
TWHAX
W
HIGH Z
DATA VALID
TWLQZ
TWHQX
TDVWH
TWHDX
Q
D
PDF 
ZIP