White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002
Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

The WED2ZLRSP01S, Dual Independent Array, NBL-
SSRAM device employs high-speed, Low-Power CMOS
silicon and is fabricated using an advanced CMOS process.
WEDC's 24Mb, Sync Burst SRAM MCP integrates two
totally independent arrays, the fi rst organized as a 512K x
32, and the second a 256K x 32.

All Synchronous inputs pass through registers controlled
by a positive edge triggered, single clock input per array.
The NBL or No Bus Latency Memory provides 100% bus
utilizaton, with no loss of cycles caused by change in modal
operation (Write to Read/Read to Write). All inputs except
for Asynchronous Output Enable and Burst Mode control
are synchronized on the positive or rising edge of Clock.
Burst order control must be tied either HIGH or LOW, Write
cycles are internally self-timed, and writes are initiated on
the rising edge of clock. This feature eliminates the need
for complex off-chip write pulse generation and proved
increased timing fl exibility for incoming signals.

512K x 32/256K x 32 Dual Array
Synchronous Pipeline Burst NBL SRAM

PIN CONFIGURATION

(TOP VIEW)

Fast clock speed: 166, 150, 133, and 100MHz

Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns

Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and
5.0ns

Single +2.5V ± 5% power supply (V

)

Snooze Mode for reduced-standby power

Individual Byte Write control

Clock-controlled and registered addresses, data
I/Os and control signals

Burst control (interleaved or linear burst)

Packaging:

209-bump BGA package

Low capacitive bus loading

Vss

A_DATb

Vss

A_DATa

Vss

A_DATb

Vss

A_DATa

A_ADR

A_OE#

A_ADV

A_BWEb

Vss

A_BWEa

A_ZZ

A_ADR

Vss

A_CKE#

Vcc

A_ADR

A_CK

A_GWE#

Vcc

A_ADR

Vss

A_CS

Vcc

A_ADR

A_CS

A_BWEc

Vss

A_BWEd

A_LBO#

A_ADR

A_DATc

Vss

A_DATd

Vss

A_DATc

Vss

A_DATd

Vss

B_DATb

B_DAT

Vss

B_DATa

Vss

B_DATb

B_DAT

Vss

B_DATa

B_ADR

B_OE#

B_ADV

B_BWEb

Vss

B_BWEa

B_ZZ

B_ADR

Vss

B_CKE#

Vcc

B_ADR

B_CK

B_GWE#

Vcc

B_ADR

Vss

B_CS

Vcc

B_ADR

B_CS

B_BWE

Vss

B_BWEd

B_LBO#

B_ADR

B_DATc

Vss

B_DATd

Vss

B_DATc

Vss

B_DATd

Vss

FEATURES

DESCRIPTION

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002
Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

Write operation occurs when WE# is driven low at the rising
edge of the clock. BW#[d:a] can be used for byte write
operation. The pipe-lined NBL SSRAM uses a late-late write
cycle to utilize 100% of the bandwidth. At the fi rst rising edge
of the clock, WE and address are registered, and the data
associated with that address is required two cycle later.

Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of the
burst seguence is provided by the external address. The
burst address counter wraps around to its initial state upon
completion. The burst sequence is determined by the state
of the LBO# pin. When this pin is low, linear burst sequence
is selected. And when this pin is high, Interleaved burst
sequence is selected.

During normal operation, ZZ must be driven low. When ZZ
is driven high, the SRAM will enter a Power Sleep Mode
after 2 cycles. At this time, internal state of the SRAM is
preserved. When ZZ returns to low, the SRAM operates
after 2 cycles of wake up time.

The WED2ZLRSP01S is an NBL Dual Array SSRAM
designed to sustain 100% bus bandwidth by eliminating
turnaround cycle when there is transition from Read to
Write, or vice versa. All inputs (with the exception of OE#,
LBO# and ZZ) are synchronized to rising clock edges,
and all features are available on each of the independent
arrays.

All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be internally
generated by the burst advance pin (ADV). ADV should
be driven to Low once the device has been deselected in
order to load a new address for next operation.

Clock Enable (CKE#) pin allows the operation of the chip
to be suspended as long as necessary. When CKE# is
high, all synchronous inputs are ignored and the internal
device registers will hold their previous values. NBL
SSRAM latches external address and initiates a cycle
when CKE# and ADV are driven low at the rising edge
of the clock.

Output Enable (OE#) can be used to disable the output
at any given time. Read operation is initiated when at
the rising edge of the clock, the address presented to
the address inputs are latched in the address register,
CKE# is driven low, the write enable input signals WE#
are driven high, and ADV driven low. The internal array is
read between the fi rst rising edge and the second rising
edge of the clock and the data is latched in the output
register. At the second clock edge the data is driven out
of the SRAM. During read operation OE# must be driven
low for the device to drive out the requested data.

NOTE 1: LBO# pin must be tied to High or Low, and Floating State must not be allowed.

LBO# Pin

High

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

BURST SEQUENCE TABLE

FUNCTION DESCRIPTION

(Interleaved Burst, LBO# = High)

(Interleaved Burst, LBO = High)

LBO# Pin

High

Case 1

Case 2

Case 3

Case 4

First Address

Fourth Address

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002
Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

CEx#

ADV

WE#

BWx#

OE#

CKE#

Address Accessed

Operation

N/A

Deselect

N/A

Continue Deselect

External Address

Begin Burst Read Cycle

Next Address

Continue Burst Read Cycle

External Address

NOP/Dummy Read

Next Address

Dummy Read

External Address

Begin Burst Write Cycle

Next Address

Continue Burst Write Cycle

N/A

NOP/Write Abort

Next Address

Write Abort

Current Address

Ignore Clock

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

WRITE TRUTH TABLE

WE#

BWa# BWb#

BWc# BWd#

Operation

Read

Write Byte a

Write Byte b

Write Byte c

Write Byte d

Write All Bytes

Write Abort/NOP

NOTES:
1. X means "Don't Care."
2. All inputs in this table must meet setup and hold time around the rising

edge of CK (

3. Applies to each of the independent arrays.

NOTES:
1. X means "Don't Care."
2. The rising edge of clock is symbolized by (

)

3. A continue deselect cycle can only be entered if a deselect cycle is executed fi rst.
4. WRITE# = L means Write operation in WRITE TRUTH TABLE.

WRITE# = H means Read operation in WRITE TRUTH TABLE.

5. Operation fi nally depends on status of asynchronous input pins (ZZ and OE#).
6. CEx# refers to the combination of CE

#, CE

and CE

7. Applies to each of the independent arrays.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002
Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

ABSOLUTE MAXIMUM RATINGS*

Voltage on Vdd Supply Relative to V

-0.3V to +3.6V

(DQx)

-0.3V to +3.6V

(Inputs)

-0.3V to +3.6V

Storage Temperature (BGA)

-55°C to +125°C

Short Circuit Output Current

100mA

ELECTRICAL CHARACTERISTICS (0°C T

70°C)

*Stress greater than those listed under "Absolute Maximum Ratings": may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this
specifi cation is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.

Description

Symbol

Conditions

Min

Max

Units

Notes

Input High (Logic 1) Voltage

1.7

+0.3

Input Low (Logic 0) Voltage

-0.3

0.7

Input Leakage Current

0V V

-5

µA

Output Leakage Current

Output(s) Disabled, 0V V

-5

µA

Output High Voltage

= -1.0mA

2.0

---

Output Low Voltage

= 1.0mA

---

0.4

Supply Voltage

2.375

2.625

NOTES:
1. All voltages referenced to V

(GND)

2. ZZ pin has an internal pull-up, and input leakage is higher.

DC CHARACTERISTICS

NOTES:
1. I

is specifi ed with no output current and increases with faster cycle times. I

increases with faster cycle times and greater output loading.

2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time.

BGA CAPACITANCE

NOTES:
1. This parameter is sampled.

Description

Symbol

Conditions

Typ

Max

Units

Notes

Control Input Capacitance

= 25°C; f = 1MH

Input/Output Capacitance (DQ)

= 25°C; f = 1MH

Address Capacitance

= 25°C; f = 1MH

Clock Capacitance

= 25°C; f = 1MH

Description

Symbol

Conditions

Typ

166

MHz

150

MHz

133

MHz

100

MHz

Units

Notes

Power Supply
Current: Operating

Device Selected; All Inputs V

or V

; Cycle

Time = t

CYC

MIN; V

= MAX; Output Open

650

600

560

500

1, 2

Power Supply
Current: Standby

SB2

Device Deselected; V

= MAX; All Inputs V

+ 0.2

or V

- 0.2; All Inputs Static; CK Frequency = 0;

ZZ V

Power Supply
Current: Current

SB3

Device Selected; All Inputs V

or V

; Cycle

Time =t

CYC

MIN; V

= MAX; Output Open;

ZZ V

- 0.2V

Clock Running
Standby Current

SB4

Device Deselected; V

= MAX; All Inputs

+ 0.2 or V

- 0.2; Cycle Time = t

CYC

MIN; ZZ V

140

120

100

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002
Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

AC CHARACTERISTICS

NOTES:
1. All Address inputs must meet the specifi ed setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is

sampled valid. All other synchronous inputs must meet the specifi ed setup and hold times whenever this device is chip selected.

2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled.
3. A write cycle is defi ned by WE# low having been registered into the device at ADV Low. A Read cycle is defi ned by WE# High with ADV Low.

Both cases must meet setup and hold times.

4. Applies to each of the independent arrays.

OUTPUT LOAD (A)

OUTPUT LOAD (B)

(for t

LZC

, t

LZOE

, t

HZOE

, and t

HZC

)

Parameter

Symbol

166MHz

150MHz

133MHz

100MHz

Units

Min

Max

Min

Max

Min

Max

Min

Max

Clock Time

CYC

6.0

6.7

7.5

10.0

Clock Access Time

3.5

3.8

4.2

5.0

Output enable to Data Valid

3.5

3.8

4.2

5.0 ns

Clock High to Output Low-Z

LZC

1.5

Output Hold from Clock High

1.5

Output Enable Low to output Low-Z

LZOE

0.0

Output Enable High to Output High-Z

HZOE

3.0

3.5

3.5 ns

Clock High to Output High-Z

HZC

3.0

3.5

3.5 ns

Clock High Pulse Width

2.2

2.5

3.0

Clock Low Pulse Width

2.2

2.5

3.0

Address Setup to Clock High

1.5

CKE# Setup to Clock High

CES

1.5

Data Setup to Clock High

1.5

Write Setup to Clock High

1.5

Address Advance to Clock High

ADVS

1.5 1.5 1.5 1.5 ns

Chip Select Setup to Clock High

CSS

1.5 1.5 1.5 1.5 ns

Address Hold to Clock high

0.5

CKE# Hold to Clock High

CEH

0.5

Data Hold to Clock High

0.5

Write Hold to Clock High

0.5

Address Advance to Clock High

ADVH

0.5

Chip Select Hold to Clock High

CSH

0.5

*Including Scope and Jig Capacitance

AC TEST CONDITIONS

(0 T

70°C, V

= 2.5V ± 5%, Unless Otherwise Specifi ed)

Parameter

Value

Input Pulse Level

0 to 2.5V

Input Rise and Fall Time (Measured at 20% to 80%)

1.0V/ns

Input and Output Timing Reference Levels

1.25V

Output Load

See Output Load (A)

Dout

Zo=50

RL=50

VL=1.25V

30pF*

Dout

1538

5pF*

+2.5V

1667

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002
Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

SNOOZE MODE is a low-current, "power-down" mode
in which the device is deselected and current is reduced
to I

SB2Z

. The duration of SNOOZE MODE is dictated by

the length of time Z is in a HIGH state. After the device
enters SNOOZE MODE, all inputs except ZZ become
gated inputs and are ignored. ZZ is an asynchronous,
active HIGH input that causes the device to enter
SNOOZE MODE.

When ZZ becomes a logic HIGH, I

SB2Z

is guaranteed after

the setup time t

is met. Any READ or WRITE operation

pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore, SNOOZE
MODE must not be initiated until valid pending operations
are completed.

SNOOZE MODE

Description Conditions

Symbol

Min

Max

Units

Notes

Current during SNOOZE MODE

ZZ V

SB2Z

10 mA

ZZ active to input ignored

2(t

)

ZZ inactive to input sampled

RZZ

2(t

)

ZZ active to snooze current

ZZI

2(t

)

ZZ inactive to exit snooze current

RZZI

ns 1

FIG. 2 SNOOZE MODE TIMING DIAGRAM

SUPPLY

CLOCK

ALL INPUTS

(except ZZ)

Output (Q)

ZZI

RZZ

RZZI

HIGH-Z

DESELECT or READ Only

ISB2Z

DON'T CARE

SNOOZE MODE

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002
Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

Clock

CKE#

Address

WRITE#

CEx#

ADV

OE#

Data Out

CYC

CES

CEH

CSS

CSH

ADVS

ADVH

LZOE

HZOE

HZC

Q1-1

Q2-1

Q2-2

Q2-3

Q2-4

Q3-1

Q3-2

Q3-3

Q3-4

Dont Care

Undefined

NOTES:

WRITE# = L means WE# = L, and BWx# = L

CEx# refers to the combination of CE1#, CE2 and CE2#.

FIG. 3 TIMING WAVEFORM OF READ CYCLE

Note:
Applies to both independent arrays.

White Electronic Designs Corporation · (602) 437-1520 · www.wedc.com

White Electronic Designs

WED2ZLRSP01S

April, 2002
Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.

Part Number

Confi guration

tCD
(ns)

Clock
(MHz)

Operating

Range

Temperature

Range

WED2ZLRSP01S35BC

512K x 32/256K x 32

3.5

166

Commercial

0° - 70° C

WED2ZLRSP01S38BC

512K x 32/256K x 32

3.8

150

Commercial

0° - 70°C

WED2ZLRSP01S42BC

512K x 32/256K x 32

4.2

133

Commercial

0° - 70°C

WED2ZLRSP01S50BC

512K x 32/256K x 32

5.0

100

Commercial

0° - 70°C

WED2ZLRSP01S38BI

512K x 32/256K x 32

3.8

150

Industrial

-40° - 85°C

WED2ZLRSP01S42BI

512K x 32/256K x 32

4.2

133

Industrial

-40° - 85°C

WED2ZLRSP01S50BI

512K x 32/256K x 32

5.0

100

Industrial

-40° - 85°C

PACKAGE DIMENSION: 153 BUMP PBGA

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

ORDERING INFORMATION

NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defi ned.

17.00

23.00

3.50

10.00

1.00

18.00

2.5

.60 ± .050

0.50 ± 10

2.33 Max

Commercial Temp Range (0°C to 70°C)

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