NexFlash Technologies, Inc.
1
PRELIMINARY
NXSF036A-0303
08/01/03
PRELIMINARY
AUGUST 2003
NX25P10, NX25P20 AND NX25P40
1M-BIT, 2M-BIT AND 4M-BIT
Serial Flash Memory
2
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
Table of Contents
NX25P10, NX25P20 AND NX25P40
1M-BIT, 2M-BIT AND 4M-BIT Serial Flash Memory ...................................................................................................... 1
FEATURES ..................................................................................................................................................................... 4
GENERAL DESCRIPTION ............................................................................................................................................. 4
Figure 1. NX25P10, NX25P20 and NX25P40 Block Diagram .................................................................................... 5
PIN DESCRIPTIONS ...................................................................................................................................................... 6
Package Types ......................................................................................................................................................... 6
Serial Data Input (DI) ................................................................................................................................................ 6
Serial Data Output (DO) ............................................................................................................................................ 6
Serial Clock (CLK) .................................................................................................................................................... 6
Chip Select (CS) ....................................................................................................................................................... 6
Hold (HOLD) ............................................................................................................................................................. 6
Write Protect (WP) .................................................................................................................................................... 6
Figure 2a. NX25P10, NX25P20 and NX25P40 Pin Assignments, 8-pin SOIC (Package Code N) .............................. 6
Figure 2b. NX25P10, NX25P20 and NX25P40 Pin Assignments, 8-contact MLP (Package Code P) ......................... 6
Table 1. Pin Descriptions .......................................................................................................................................... 6
SPI OPERATION ............................................................................................................................................................ 7
SPI Modes ............................................................................................................................................................... 7
Hold Function ........................................................................................................................................................... 7
WRITE PROTECTION .................................................................................................................................................... 7
Write Protect Features .............................................................................................................................................. 7
STATUS REGISTER ....................................................................................................................................................... 8
BUSY ....................................................................................................................................................................... 8
Write Enable Latch (WEL) ......................................................................................................................................... 8
Figure 4. Status Register Bit Locations ..................................................................................................................... 8
Block Protect Bits (BP2, BP1, BP0) ......................................................................................................................... 8
Reserved Bits ........................................................................................................................................................... 8
Status Register Protect (SRP) .................................................................................................................................. 8
Table 2: Status Register Memory Protection ............................................................................................................. 9
INSTRUCTIONS ........................................................................................................................................................... 10
Table 3: Instruction Set ........................................................................................................................................... 10
Table 4: Manufacturer and Device Identification ...................................................................................................... 10
Write Enable (06h) .................................................................................................................................................... 11
Figure 5. Write Enable Instruction Sequence Diagram ............................................................................................. 11
Write Disable (04h) ................................................................................................................................................... 11
Figure 6. Write Disable Instruction Sequence Diagram ............................................................................................ 11
Read Status Register (05h) ...................................................................................................................................... 12
Figure 7. Read Status Register Instruction Sequence Diagram ............................................................................... 12
Write Status Register (01h) ...................................................................................................................................... 13
Figure 8. Write Status Register Instruction Sequence Diagram ............................................................................... 13
NexFlash Technologies, Inc.
3
PRELIMINARY
NXSF036A-0303
08/01/03
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NX25P10
NX25P20
NX25P40
Table of Contents
Read Data (03h) ........................................................................................................................................................ 14
Figure 9. Read Data Instruction Sequence Diagram ................................................................................................ 14
Fast Read (0Bh) ........................................................................................................................................................ 15
Figure 10. Fast Read Instruction Sequence Diagram ............................................................................................... 15
Page Program (02h) ................................................................................................................................................. 16
Figure 11. Page Program Instruction Sequence Diagram ........................................................................................ 16
Sector Erase (D8h) ................................................................................................................................................... 17
Figure 12. Sector Erase Instruction Sequence Diagram .......................................................................................... 17
Bulk Erase (C7h) ...................................................................................................................................................... 18
Figure 13. Bulk Erase Instruction Sequence Diagram ............................................................................................. 18
Power-down (B9h) .................................................................................................................................................... 19
Figure 14. Deep Power-down Instruction Sequence Diagram ................................................................................... 19
Release Power-down / Device ID (ABh) ................................................................................................................... 20
Figure 15. Release Power-down Instruction Sequence ............................................................................................ 20
Figure 16. Release Power-down / Device ID Instruction Sequence Diagram ............................................................ 20
Read Manufacturer / Device ID (90h) ....................................................................................................................... 21
Figure 17. Read Manufacturer / Device ID Diagram ................................................................................................ 21
SPECIFICATIONS AND TIMING DIAGRAMS ............................................................................................................... 22
Table 5. Absolute Maximum Ratings ....................................................................................................................... 22
Table 6. Operating Ranges ...................................................................................................................................... 22
Table 7. Power-up Timing and Write Inhibit Threshold .............................................................................................. 22
Figure 18. Power-up Timing and Voltage Levels ....................................................................................................... 22
Table 8. DC Electrical Characteristics ..................................................................................................................... 23
Table 9. AC Measurement Conditions ..................................................................................................................... 23
Figure 19. AC Measurement I/O Waveform ............................................................................................................. 23
Table 10. AC Electrical Characteristics ................................................................................................................... 24
Figure 20. Serial Output Timing ............................................................................................................................... 25
Figure 21. Input Timing ........................................................................................................................................... 25
Figure 22. Hold Timing ............................................................................................................................................ 25
PACKAGING INFORMATION ........................................................................................................................................ 26
8-Pin SOIC 150-mil (Package Code N) ....................................................................................................................... 26
8-Contact MLP* 5x6mm (Package Code P) ............................................................................................................... 27
PRELIMINARY DESIGNATION .................................................................................................................................... 28
IMPORTANT NOTICE ................................................................................................................................................... 28
ORDERING INFORMATION ......................................................................................................................................... 28
LIFE SUPPORT POLICY ............................................................................................................................................. 28
TRADEMARKS ............................................................................................................................................................. 28
Document Revision History ........................................................................................................................................ 29
4
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
GENERAL DESCRIPTION
The NX25P10 (1M-bit), NX25P20 (2M-bit) and NX25P40
(4M-bit) Serial Flash memories provide a storage solution
for systems with limited space, pins and power. They are
ideal for code download applications as well as storing
voice, text and data. The devices operate on a single 2.7V
to 3.6V power supply with current consumption as low as
4mA active and 1A for power-down. All devices are offered
in space-saving 8-pin SOIC type packages as shown
below. As part of a family of Serial Flash products,
NexFlash also provides a compatible migration path to 8M/
16M/32M-bit densities.
The NX25P10/20/40 array is organized into 512/1024/2048
programmable pages of 256-bytes each. A single byte or,
up to 256 bytes, can be programmed at a time using the
Page Program instruction. Pages are grouped into 2/4/8
erasable sectors of 256 pages (64KB) each as shown in
figure 1. Both Sector Erase and Bulk (full chip) Erase
instructions are supported.
The Serial Peripheral Interface (SPI) consists of four pins
(Serial Clock, Chip Select, Serial Data In and Serial Data
Out) that support high speed serial data transfers up to
33MHz. A Hold pin, Write Protect pin and programmable
write protect features provide further control flexibility.
Additionally, the device can be queried for manufacturer
and device ID. Special customer ID (for copy authentica-
tion) and factory programming is available, contact Nex-
Flash for more information.
FEATURES
1M / 2M / 4M-bit Serial Flash Memories
Family of Serial Flash Memories
NX25P10: 1M-bit (131KB) 512 pages
NX25P20: 2M-bit (262KB) 1024 pages
NX25P40: 4M-bit (524KB) 2048 pages
256-bytes per programmable page
Compatible migration path to 8M/16M/32M-bit
4-pin SPI Serial Interface
Clock, Chip Select, Data In, Data Out
Easily interfaces to popular microcontrollers
Compatible with SPI Modes 0 and 3
Optional Hold function for SPI flexibility
Low Power Consumption, Wide Temperature Range
Single 2.7 to 3.6V supply
4mA active current, 1A (typ) Power-down
-40 to +85C Operating Range
Fast and Flexible Serial Data Access
Clock operation to 33MHz
Byte-addressable Read and Program
Auto-increment Read capability
Manufacturer and Device ID
Programming Features
Page program up to 256 bytes <2ms
Sector Erase (64KB) 2 seconds
Chip erase: 3 seconds (25P10/20),
5 seconds (25P40)
100,000 erase/write cycles
Ten year data retention
Software and Hardware Write Protection
Write-Protect all or portion of memory via software
Enable/Disable protection with
WP pin
SOIC Compatible Packaging
Tiny 8-pin SOIC
Optional 8-contact MLP (QFN) with SOIC footprint
Ideal for systems with limited pins, space, and power
ASIC and Controller-based serial code-download
Microcontroller systems storing data, text or voice
Battery-operated and portable products
8-Pin SOIC 150-mil
(Package Code N)
8-Contact MLP 5x6mm
(Package Code P)
NexFlash Technologies, Inc.
5
PRELIMINARY
NXSF036A-0303
08/01/03
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NX25P10
NX25P20
NX25P40
000000h 0000FFh
07FF00h 07FFFFh
070000h 0700FFh
06FF00h 06FFFFh
060000h 0600FFh
05FF00h 05FFFFh
050000h 0500FFh
04FF00h 04FFFFh
040000h 0400FFh
03FF00h 03FFFFh
030000h 0300FFh
02FF00h 02FFFFh
020000h 0200FFh
01FF00h 01FFFFh
010000h 0100FFh
00FF00h 00FFFFh
Serial Flash Memory Array
NX25P20
NX25P10
NX25P40
Sector 7
Sector 6
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Sector 0
*
*
Every Sector Consists of 256 Pages of 256 Bytes Each
Wr
ite Protect Logic
Ro
w Decode
Column Decode
and 256 Byte Page Buffer
High-voltage
Generators
Page Address
Latch / Counter
Data
Write Control
Logic
WP
HOLD
Status
Register
SPI
Comand and
Control Logic
Byte Address
Latch / Counter
CLK
CS
DI
DO
Begining
Page Address
Ending
Page Address
Figure 1. NX25P10, NX25P20 and NX25P40 Block Diagram
6
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
Table 1. Pin Descriptions
DI
Data Input
DO
Data Output
CLK
Serial Clock Input
CS
Chip Select Input
WP
Write Protect Input
HOLD
Hold Input
Vcc, GND
Power Supply
PIN DESCRIPTIONS
Package Types
The standard package for the NX25P10/20/40 is an 8-pin
plastic SOIC with 150 mil body (NexFlash package code N).
The pinout for the "N" package is shown in Figure 2a. An
alternative 8-contact MLP (QFN) package is also offered
(NexFlash package code P). The pinout for the "P" package
is shown in Figure 2b. The 8-contact MLP package has the
same basic footprint as the 8-pin SOIC but with a height that
is 40% thinner. It also allows a package migration path to
higher density Serial Flash devices. Package diagrams and
dimensions are illustrated at the end of this data sheet.
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for
instructions, addresses and data to be serially written to
(shifted into) the device. Data is latched on the rising edge
of the Serial Clock (CLK) input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for
data and status to be serially read from (shifted out of) the
device. Data is shifted out on the falling edge of the Serial
Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for
serial input and output operations. ("See SPI "Operations")
Chip Select (
CS
CS
CS
CS
CS)
The SPI Chip Select (
CS) pin enables and disables device
operation. When
CS is high the device is deselected and the
Serial Data Output (DO) pin is at high impedance. When
deselected, the devices power consumption will be at
standby levels unless an internal erase, program or status
register cycle is in progress. When
CS is brought low the
device will be selected, power consumption will increase to
active levels and instructions can be written to and data read
from the device. After power-up,
CS must transition from
high to low before a new instruction will be accepted. The
CS
input must track the Vcc supply level at power-up (see
"Write Protection" and figure 18). If needed a pull-up resister
on
CS can be used to accomplish this.
Hold (
HOLD
HOLD
HOLD
HOLD
HOLD)
The
HOLD pin allows the device to be paused while it is
actively selected. When
HOLD is brought low, while CS is
low, the DO pin will be at high impedance and signals on the
DI and CLK pins will be ignored (don't care). When
HOLD is brought high, device operation can resume. The
hold function can be useful when multiple devices are
sharing the same SPI signals. ("See Hold function")
CS
DO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
CLK
DI
Figure 2a. NX25P10, NX25P20 and NX25P40 Pin
Assignments, 8-pin SOIC (Package Code N)
CS
DO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
CLK
DI
Figure 2b. NX25P10, NX25P20 and NX25P40 Pin
Assignments, 8-contact MLP (Package Code P)
Write Protect (
WP
WP
WP
WP
WP)
The Write Protect (
WP) pin can be used to prevent the
Status Register from being written. Used in conjunction with
the Status Register's Block Protect (BP0 and BP1) bits and
Status Register Protect (SRP) bits, a portion or the entire
memory array can be hardware protected. The
WP pin is
active low.
NexFlash Technologies, Inc.
7
PRELIMINARY
NXSF036A-0303
08/01/03
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NX25P10
NX25P20
NX25P40
SPI OPERATION
SPI Modes
The NX25P10/20/40 is accessed through an SPI compat-
ible bus consisting of four signals: Serial Clock (CLK), Chip
Select (
CS), Serial Data Input (DI) and Serial Data Output
(DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are
supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when
the SPI bus master is in standby and data is not being
transferred to the Serial Flash. For Mode 0 the CLK signal
is normally low. For Mode 3 the CLK signal is normally high.
In either case data input on the DI pin is sampled on the
rising edge of the CLK. Data output on the DO pin is clocked
out on the falling edge of CLK.
Hold Function
The
HOLD signal allows the NX25P10/20/40 operation to be
paused while it is actively selected (when
CS is low). The
hold function may be useful in cases where the SPI data and
clock signals are shared with other devices. For example,
consider if the page buffer was only partially written when a
priority interrupt requires use of the SPI bus. In this case the
hold function can save the state of the instruction and the
data in the buffer so programming can resume where it left
off once the bus is available again.
To initiate a hold condition, the device must be selected with
CS low. A hold condition will activate on the falling edge of
the
HOLD signal if the CLK signal is already low. If the CLK
is not already low the hold condition will activate after the
next falling edge of CLK. The hold condition will terminate
on the rising edge of the hold signal if the CLK signal is
already low. If the CLK is not already low the hold condition
will terminate after the next falling edge of CLK.
During a hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DI) and Serial Clock
(CLK) are ignored. The Chip Select (
CS) signal should be
kept active (low) for the full duration of the hold operation to
avoid resetting the internal logic state of the device.
WRITE PROTECTION
Applications that use non-volatile memory must take into
consideration the possibility of noise and other adverse
system conditions that may compromise data integrity. To
address this concern the NX25P10/20/40 provides several
means to protect data from inadvertent writes.
Write Protect Features
Device resets when Vcc is below threshold.
Time delay write disable after Power-up.
Write enable/disable instructions.
Automatic write disable after program and erase.
Software write protection using Status Register.
Hardware write protection using Status Register and
WP pin.
Write Protection using Power-down instruction.
Upon power-up or at power-down the NX25P10/20/40 will
maintain a reset condition while Vcc is below the threshold
value of V
WI
, (See Power-up Timing and Voltage Levels:
Table 7 and Figure 18). While reset, all operations are
disabled and no instructions are recognized. During power-
up and after the Vcc voltage exceeds V
WI
, all program and
erase related instructions are further disabled for a time
delay of t
PUW
. This includes the Write Enable, Page Pro-
gram, Sector Erase, Bulk Erase and the Write Status
Register instructions. Note that the chip select pin (
CS)
must track the Vcc supply level at power-up until the Vcc-
min level and t
VSL
time delay is reached. If needed a pull-up
resister on
CS can be used to accomplish this.
After power-up the device in automatically placed in a write-
disabled state with the Status Register Write Enable Latch
(WEL) set to a 0. A Write Enable instruction must be issued
before a Page Program, Sector Erase, Bulk Erase or Write
Status Register instruction will be accepted. After complet-
ing a program, erase or write instruction the Write Enable
Latch (WEL) is automatically cleared to a write-disabled state
of 0.
Software controlled write protection is facilitated using the
Write Status Register instruction and setting the Status
Register Protect (SRP) and Block Protect (BP0, BP2) bits.
These Status Register bits allow a portion or all of the
memory to be configured as read only. Used in conjunction
with the Write Protect (
WP) pin, changes to the Status
Register can be enabled or disabled under hardware control.
See Status Register for further information.
Additionally, the Power-down instruction offers an extra
level of write protection as all instructions are ignored
except for the Release Power-down instruction.
8
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
S7 S6 S5 S4 S3 S2 S1 S0
SRP (Reserved) BP2 BP1 BP0 WEL
BUSY
Status RegisterProtect
(Non-volatile)
Block Protect Bits
(Non-volatile)
Write Enable Latch
Device Busy
Erase Program or Write in Progress
Figure 4. Status Register Bit Locations
STATUS REGISTER
The Read Status Register instruction can be used to provide
status on the availability of the Flash memory array, if the
device is write enabled or disabled, and the state of write
protection. The Write Status Register instruction can be
used to configure the devices write protection features. See
Figure 4.
BUSY
BUSY is a read only bit in the status register (S0) that is set
to a 1 state when the device is executing a Page Program,
Sector Erase, Bulk Erase or Write Status Register instruc-
tion. During this time the device will ignore further instruc-
tions except for the Read Status Register instruction (see
t
W
, t
PP
, t
SE
and t
BE
in AC Characteristics). When the
program, erase or write status register instruction has
completed, the BUSY bit will be cleared to a 0 state
indicating the device is ready for further instructions.
Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status
register (S1) that is set to a 1 after executing a Write Enable
Instruction. The WEL status bit is cleared to a 0 when the
device is write disabled. A write disable state occurs upon
power-up or after any of the following instructions: Write
Disable, Page Program, Sector Erase, Bulk Erase and
Write Status Register.
Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile
read/write bits in the status register (S4, S3, S2) that provide
Write Protection control and status. Block Protect bits can
be set using the Write Status Register Instruction (see tW
in AC characteristics). All, none or a portion of the memory
array can be protected from Program and Erase instructions
(see table 2). The factory default setting for the Block
Protection Bits is 0, none of the array protected. The Block
Protect bits can not be written to if the Status Register
Protect (SRP) bit is set to 1 and the Write Protect (
WP) pin
is low. The NX25P20 and NX25P10 do not use BP2.
Reserved Bits
Status register bit locations 5 and 6 are reserved for future
use. Current devices will read 0 for these bit locations. It is
recommended to mask out the reserved bit when testing the
Status Register. Doing this will ensure compatibility with
future devices.
Status Register Protect (SRP)
The Status Register Protect (SRP) bit is a non-volatile read/
write bit in the status register (S7) that can be used in
conjunction with the Write Protect (
WP) pin to disable writes
to the status register. When the SRP bit is set to a 0 state
(factory default) the
WP pin has no control over the status
register. When the SRP pin is set to a 1, the Write Status
Register instruction is locked out while the
WP pin is low.
When the
WP pin is high the Write Status Register instruc-
tion is allowed.
NexFlash Technologies, Inc.
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PRELIMINARY
NXSF036A-0303
08/01/03
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NX25P10
NX25P20
NX25P40
Table 2: Status Register Memory Protection
Status Register
(1)
NX25P40 (4M-bit) Memory Protection
BP2 BP1 BP0
Sector(s)
Addresses
Density
Portion
0
0
0
NONE
NONE
NONE
NONE
0
0
1
7
070000h - 07FFFFh
512K-bit
Upper 1/8
0
1
0
6 and 7
060000h - 07FFFFh
1M-bit
Upper 1/4
0
1
1
4 thru 7
040000h - 07FFFFh
2M-bit
Upper 1/2
1
x
x
ALL
000000h - 07FFFFh
4M-bit
ALL
Status Register
(1)
NX25P20 (2M-bit) Memory Protection
BP2 BP1 BP0
Sector(s)
Addresses
Density
Portion
x
0
0
NONE
NONE
NONE
NONE
x
0
1
3
030000h - 03FFFFh
512K-bit
Upper 1/4
x
1
0
2 and 3
020000h - 03FFFFh
1M-bit
Upper 1/2
x
1
1
ALL
000000h - 03FFFFh
2M-bit
ALL
Status Register
(1)
NX25P10 (1M-bit) Memory Protection
BP2 BP1 BP0
Sector(s)
Addresses
Density
Portion
x
0
x
NONE
NONE
NONE
NONE
x
1
0
NONE
NONE
NONE
NONE
x
1
1
ALL
000000h - 01FFFFh
1M-bit
ALL
Notes:
1. x = don't care.
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NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
Table 3: Instruction Set
(1)
Instruction Name
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Code
Write Enable
06h
Write Disable
04h
Read Status Register
05h
(S7S0)
(1)
(2)
Write Status Register
01h
S7S0
Read Data
03h
A23A16
A15A8
A7A0
(D7D0)
(Next byte)
continuous
Fast Read
0Bh
A23A16
A15A8
A7A0
dummy
(D7D0)
(Next Byte)
continuous
Page Program
02h
A23A16
A15A8
A7A0
(D7D0)
(Next byte)
up to 256 bytes
Sector Erase
D8h
A23A16
A15A8
A7A0
Bulk Erase
C7h
Power-down
B9h
Release Power-down
ABh
dummy
dummy
dummy
(ID7-ID0)
(3)
and Device ID
Manufacturer/Device ID
90h
dummy
dummy
00h
(M7-M0)
(ID7-ID0)
(4)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis "( )" indicate data being read from
the device on the DO pin.
2. The Status Register contents will repeat continuously until
CS terminate the instruction.
3. The Device ID will repeat continuously until
CS terminate the instruction.
4. The Manufacturer ID and Device ID bytes will repeat continuously until
CS terminate the instruction.
Table 4: Manufacturer and Device Identification
Manufacturer ID
(M7-M0)
NexFlash
EFh
Device ID
(ID7-ID0)
NX25P10
10h
NX25P20
11h
NX25P40
12h
INSTRUCTIONS
The instruction set of the NX25P10/20/40 consists of
twelve basic instructions that are fully controlled through the
SPI bus (see Table 3). Instructions are initiated with the
falling edge of Chip Select (
CS). The first byte of data
clocked into the DI input provides the instruction code. Data
on the DI input is sampled on the rising edge of clock with
most significant bit (MSB) first.
Instructions vary in length from a single byte to several
bytes and may be followed by address bytes, data bytes,
dummy bytes (don't care), and in some cases, a combina-
tion. Instructions are completed with the rising edge of edge
CS. Clock relative timing diagrams for each instruction are
included in figures 5 through 17. All read instructions can be
completed after any clocked bit. However, all instructions
that Write, Program or Erase must complete on a byte
boundary (
CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be terminated. This
feature further protects the device from inadvertent writes.
Additionally, while the memory is being programmed or
erased, or when the Status Register is being written, all
instructions except for Read Status Register will be ignored
until the program or erase cycle has completed.
NexFlash Technologies, Inc.
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NXSF036A-0303
08/01/03
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NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7
Instruction (06h)
High Impedance
Mode 0
Mode 3
CS
CLK
DI
DO
Figure 5. Write Enable Instruction Sequence Diagram
0 1 2 3 4 5 6 7
Instruction (04h)
High Impedance
Mode 0
Mode 3
CS
CLK
DI
DO
Figure 6. Write Disable Instruction Sequence Diagram
Write Enable (06h)
The Write Enable instruction (Figure 5) sets the Write
Enable Latch (WEL) bit in the Status Register to a 1. The
WEL bit must be set prior to every Page Program, Sector
Erase, Bulk Erase and Write Status Register instruction.
The Write Enable instruction is entered by driving
CS low,
shifting the instruction code "06h" into the Data Input (DI) pin
on the rising edge of CLK, and then driving
CS high.
Write Disable (04h)
The Write Disable instruction (Figure 6) resets the Write
Enable Latch (WEL) bit in the Status Register to a 0. The
Write Enable instruction is entered by driving
CS low,
shifting the instruction code "04h" into the DI pin and then
driving
CS high. Note that the WEL bit is automatically reset
after Power-up and upon completion of the Write Status
Register, Page Program, Sector Erase, and Bulk Erase
instructions.
12
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7 8 9 10 11
12
13
14
15 16 17
18
19
20
21
22
23
Instruction (05h)
High Impedance
7
Status Register Out
Status Register Out
Mode 0
Mode 3
7 6 5 4 3 2 1 0
*
7 6 5 4 3 2 1 0
*
*
= MSB
CS
CLK
DI
DO
Figure 7. Read Status Register Instruction Sequence Diagram
Read Status Register (05h)
The Read Status Register instruction allows the 8-bit Status
Register to be read. The instruction is entered by
driving
CS low and shifting the instruction code "05h" into the
DI pin on the rising edge of CLK. The status register bits are
then shifted out on the DO pin at the falling edge of CLK with
most significant bit (MSB) first as shown in figure 7. The
Status Register bits are shown in figure 4 and include the
BUSY, WEL, BPO-BP2, and STP bits (see description of
the Status Register earlier in this data sheet).
The Status Register instruction may be used at any time,
even while a Program, Erase or Write Status Register cycle
is in progress. This allows the BUSY status bit to be
checked to determine when the cycle is complete and if the
device can accept another instruction. The Status Register
can be read continuously, as shown in Figure 7. The
instruction is completed by driving
CS high.
NexFlash Technologies, Inc.
13
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7 8 9 10 11
12
13
14
15
Instruction (01h)
High Impedance
Status Register In
Mode 0
Mode 3
7 6 5 4 3 2 1 0
*
= MSB
*
CS
CLK
DI
DO
Figure 8. Write Status Register Instruction Sequence Diagram
Write Status Register (01h)
The Write Status Register instruction allows the Status
Register to be written. A Write Enable instruction must
previously have been executed for the device to accept the
Write Status Register Instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered
by driving
CS low, sending the instruction code "01h", and
then writing the status register data byte as illustrated in
figure 8. The Status Register bits are shown in figure 4 and
described earlier in this data sheet.
For the NX25P40, only non-volatile Status Register bits
STP, BP2, BP1 and BP0 (bits 7, 4, 3 and 2) can be written
to. For the NX25P20 and NX25P10 only Status Register bits
STP, BP1 and BP0 (bits 7, 3 and 2) can be written to. All
other Status Register bit locations are read-only and will not
be affected by the Write Status Register instruction.
The
CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Write Status
Register instruction will not be executed. After
CS is driven
high, the self-timed Write Status Register cycle will com-
mence for a time duration of t
W
(See AC Characteristics).
While the Write Status Register cycle is in progress, the
Read Status Register instruction may still accessed to
check the status of the BUSY bit. The BUSY bit is a 1 during
the Write Status Register cycle and a 0 when the cycle is
finished and ready to accept other instructions again. After
the Write Register cycle has started the Write Enable Latch
(WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block
Protect bits (BP2, BP1 and BP0) to be set for protecting all,
a portion, or none of the memory from erase and program
instructions. Protected areas become read-only (see table
2). The Write Status Register instruction also allows the
Status Register Protect bit (SRP) to be set. This bit is used
in conjunction with the Write Protect (
WP) pin to disable
writes to the status register. When the SRP bit is set to a 0
state (factory default) the
WP pin has no control over the
status register. When the SRP pin is set to a 1, the Write
Status Register instruction is locked out while the
WP pin
is low. When the
WP pin is high the Write Status Register
instruction is allowed.
14
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7 8 9 10 28 29 30
31 32
Instruction (03h)
High Impedance
24-Bit Addess
Data Out 1
Data Out 2
33 34 35 36 37 38 39
7
23 22 21
3 2 1 0
Mode 0
Mode 3
*
*
*
= MSB
7 6 5 4 3 2 1 0
CS
CLK
DI
DO
Figure 9. Read Data Instruction Sequence Diagram
Read Data (03h)
The Read Data instruction allows one our more data bytes
to be sequentially read from the memory. The instruction is
initiated by driving the
CS pin low and then shifting the
instruction code "03h" followed by a 24-bit address (A23-A0)
into the DI pin. The code and address bits are latched on the
rising edge of the CLK pin. After the address is received, the
data byte of the addressed memory location will be shifted
out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of
data is shifted out allowing for a continuous stream of data.
This means that the entire memory can be accessed with
a single instruction as long as the clock continues. The
instruction is completed by driving
CS high. The Read Data
instruction sequence is shown in figure 9. If a Read Data
instruction is issued while an Erase, Program or Write cycle
is in process (BUSY=1) the instruction is ignored and will not
have any effects on the current cycle. The Read Data
instruction allows clock rates from D.C. to a maximum of f
R
( see AC Electrical Characteristics).
NexFlash Technologies, Inc.
15
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7 8 9 10 28
29
30
31
Instruction (0Bh)
Mode 0
Mode 3
24-Bit Address
23
22
21
3 2 1 0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
Data Out 1
Data Out 2
7
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
*
*
*
*
= MSB
CS
CLK
DI
DO
CS
CLK
DI
DO
Figure 10. Fast Read Instruction Sequence Diagram
Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data
instruction except that it can operate at the highest possible
frequency of F
R
(see AC Electrical Characteristics). This is
accomplished by adding a "dummy" byte after the 24-bit
address as shown in figure 10. The dummy byte allows the
devices internal circuits additional time for setting up the
initial address. The dummy byte data value on the DI pin is
a "don't care".
16
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
*
*
0 1 2 3 4 5 6 7 8 9 10
Instruction (02h)
Mode 0
Mode 3
24-Bit Address
Data Byte 1
23 22 21
3 2 1 0
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
28 29 30 31 32 33 34 35 36 37 38 39
*
= MSB
*
*
*
CS
CLK
DI
CS
CLK
DI
2072
2073
2074
2075
2076
2077
2078
2079
Figure 11. Page Program Instruction Sequence Diagram
Page Program (02h)
The Page Program instruction allows up to 256 bytes of data
to be programmed at previously erased to all 1s (FFh)
memory locations. A Write Enable instruction must be
executed before the device will accept the Page Program
Instruction (Status Register bit WEL must equal 1). The
instruction is initiated by driving the
CS pin low then shifting
the instruction code "02h" followed by a 24-bit address (A23-
A0) and at least one data byte, into the DI pin. The
CS pin
must be driven low for the entire length of the instruction
while data is being sent to the device. The Page Program
instruction sequence is shown in figure 11.
If an entire 256 byte page is to be programmed, the last
address byte (the 8 least significant address bits) should be
set to 0. If the last address byte is not zero, and the number
of clocks exceed the remaining page length, the addressing
will wrap to the beginning of the page. Less than 256 bytes
can be programmed without having any effect on other
bytes within the same page. If more than 256 bytes are sent
to the device the addressing will wrap to the beginning of the
page and overwrite previously sent data.
As with the write and erase instructions, the
CS pin must be
driven high after the eighth bit of the last byte has been
latched. If this is not done the Page Program instruction will
not be executed. After
CS is driven high, the self-timed
Page Program instruction will commence for a time duration
of tpp (See AC Characteristics). While the Page Program
cycle is in progress, the Read Status Register instruction
may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Page Program cycle and
becomes a 0 when the cycle is finished and the device is
ready to accept other instructions again. After the Page
Program cycle has started the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Page Program
instruction will not be executed if the addressed page is
protected by the Block Protect (BP2, BP1, BP0) bits (see
Table 2).
NexFlash Technologies, Inc.
17
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7 8 9
29
30
31
Instruction (D8h)
High Impedance
Mode 0
Mode 3
24-Bit Address
23
22
2 1 0
CS
CLK
DI
DO
*
*
= MSB
Figure 12. Sector Erase Instruction Sequence Diagram
Sector Erase (D8h)
The Sector Erase instruction sets all memory within a
specified sector to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will
accept the Erase Sector Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the
CS pin low and shifting the instruction code "D8h" followed
a 24-bit sector address (A23-A0) (see Figure 1). The Sector
Erase instruction sequence is shown in figure 12.
The
CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Sector Erase
instruction will not be executed. After
CS is driven high, the
self-timed Sector Erase instruction will commence for a
time duration of t
SE
(See AC Characteristics). While the
Sector Erase cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Sector Erase
cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the
Sector Erase cycle has started the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Sector
Erase instruction will not be executed if the addressed page
is protected by the Block Protect (BP2, BP1, BP0) bits (see
Table 2).
18
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7
Instruction (C7h)
High Impedance
Mode 0
Mode 3
CS
CLK
DI
DO
Figure 13. Bulk Erase Instruction Sequence Diagram
Bulk Erase (C7h)
The Bulk Erase instruction sets all memory within the
device to the erased state of all 1s (FFh). A Write Enable
instruction must be executed before the device will accept
the Bulk Erase Instruction (Status Register bit WEL must
equal 1). The instruction is initiated by driving the
CS pin low
and shifting the instruction code "C7h". The Bulk Erase
instruction sequence is shown in figure 13.
The
CS pin must be driven high after the eighth bit has been
latched. If this is not done the Bulk Erase instruction will not
be executed. After
CS is driven high, the self-timed Bulk
Erase instruction will commence for a time duration of t
BE
(See AC Characteristics). While the Bulk Erase cycle is in
progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY
bit is a 1 during the Bulk Erase cycle and becomes a 0 when
finished and the device is ready to accept other instructions
again. After the Bulk Erase cycle has started the Write
Enable Latch (WEL) bit in the Status Register is cleared to
0. The Bulk Erase instruction will not be executed if any
page is protected by the Block Protect (BP2, BP1, BP0) bits
(see Table 2).
NexFlash Technologies, Inc.
19
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7
Instruction (B9h)
t
DP
High Impedance
Stand-by Current
Power-down Current
Mode 0
Mode 3
CS
CLK
DI
DO
Figure 14. Deep Power-down Instruction Sequence Diagram
Power-down (B9h)
Although the standby current during normal operation is
relatively low, standby current can be further reduced with
the Power-down instruction. The lower power consumption
makes the Power-down instruction especially useful for
battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the
CS pin low and shifting the instruction code "B9h" as shown
in figure 14.
The
CS pin must be driven high after the eighth bit has been
latched. If this is not done the Power-down instruction will
not be executed. After
CS is driven high, the power-down
state will entered within the time duration of t
DP
(See AC
Characteristics). While in the power-down state only the
Release from Power-down / Device ID instruction, which
restores the device to normal operation, will be recognized.
All other instructions are ignored. This includes the Read
Status Register instruction, which is always available
during normal operation. Ignoring all but one instruction
makes the Power Down state a useful condition for securing
maximum write protection. The device always powers-up in
the normal operation with the standby current of ICC1.
20
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7
Instruction (ABh)
t
RES1
High Impedance
Power-down Current
Stand-by Current
Mode 0
Mode 3
CS
CLK
DI
DO
Figure 15. Release Power-down Instruction Sequence
0 1 2 3 4 5 6 7 8 9 10
28
29
30
31
32
33
34
35
36
37 38
Instruction (ABh)
3 Dummy Bytes
t
RES2
High Impedance
Stand-by Current
Power-down Current
Device ID
**
Mode 0
Mode 3
CS
CLK
DI
DO
7 6 5 4 3 2 1 0
*
= MSB
**
= See Table 4
*
23 22 21
3 2 1 0
*
Figure 16. Release Power-down / Device ID Instruction Sequence Diagram
Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a
multi-purpose instruction. It can be used to release the
device from the power-down state, obtain the devices
electronic identification (ID) number or do both.
When used only to release the device from the power-down
state, the instruction is issued by driving the
CS pin low,
shifting the instruction code "ABh" and driving
CS high as
shown in figure 15. After the time duration of t
RES
1
(See AC
Characteristics) the device will resume normal operation
and other instructions will be accepted. The
CS pin must
remain high during the t
RES
1
time duration.
When used only to obtain the Device ID while not in the
power-down state, the instruction is initiated by driving the
CS pin low and shifting the instruction code "ABh" followed
by 3-dummy bytes. The Device ID bits are then shifted out
on the falling edge of CLK with most significant bit (MSB)
first as shown in figure 16. The Device ID values for the
NX25P10, NX25P20, and NX25P40 are listed in Table 4.
The Device ID can be read continuously. The instruction is
completed by driving
CS high.
When used to release the device from the power-down state
and obtain the Device ID, the instruction is the same as
previously described, and shown in figure 14, except that
after
CS is driven high it must remain high for a time duration
of t
RES
2
(See AC Characteristics). After this time duration
the device will resume normal operation and other instruc-
tions will be accepted.
If the Release from Power-down / Device ID instruction is
issued while an Erase, Program or Write cycle is in process
(when BUSY equals 1) the instruction is ignored and will not
have any effects on the current cycle.
NexFlash Technologies, Inc.
21
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
0 1 2 3 4 5 6 7 8 9 10
28
29
30
31
Instruction (90h)
Address (000000h)
High Impedance
Mode 0
Mode 3
CS
CLK
DI
DO
*
= MSB
**
= See Table 4
23 22 21
3 2 1 0
*
32 33 34 35 36 37 38
39 40 41 42 43 44 45
Manufacturer ID (
EFh)
Device ID (
**
)
CS
CLK
DI
DO
7 6 5 4 3 2 1 0
*
Figure 17. Read Manufacturer / Device ID Diagram
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alterna-
tive to the Release from Power-down / Device ID instruction
that provides both the JEDEC assigned manufacturer ID
and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar
to the Release from Power-down / Device ID instruction.
The instruction is initiated by driving the
CS pin low and
shifting the instruction code "90h" followed by a 24-bit
address (A23-A0) of 000000h. After which, the Manufac-
turer ID for NexFlash (EFh) and the Device ID are shifted out
on the falling edge of CLK with most significant bit (MSB)
first as shown in figure 17. The Device ID values for the
NX25P10, NX25P20, and NX25P40 are listed in Table 4. If
the 24-bit address is initially set to 000001h the Device ID
will be read first and then followed by the Manufacturer ID.
The Manufacturer and Device IDs can be read continuously,
alternating from one to the other. The instruction is com-
pleted by driving
CS high.
22
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
Table 5. Absolute Maximum Ratings
(1)
Symbol
Parameters
Conditions
Range
Unit
Vcc
Supply Voltage
0.6 to +4.0
V
V
IO
Voltage Applied to Any Pin
Relative to Ground
0.6 to Vcc +4.0
V
T
STG
Storage Temperature
65 to +150
C
T
LEAD
Lead Temperature
Soldering 20 Seconds
(2)
+235
C
V
ESD
Electrostatic Discharge Voltage
Human Body Model
(3)
2000 to +2000
V
Note:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is
not guaranteed. Exposure beyond absolute maximum ratings (listed above) may cause permanent damage.
2. IPC/JEDEC J-STD-020A.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
Table 6. Operating Ranges
Symbol
Parameter
Conditions
Min
Max
Unit
Vcc
Supply Voltage
(1)
5.0V programing
2.7
3.6
V
T
A
Ambient Temperature, Operating
Industrial
40
+85
C
Note:
1. Vcc voltage during Read can operate across the min and max range but should not exceed 10% of the programming
(erase/write) voltage.
Table 7. Power-up Timing and Write Inhibit Threshold
Symbol
Parameter
Min
Max
Unit
t
VSL
(1)
VCC(min) to
CS Low
10
s
t
PUW
(1)
Time Delay Before Write Instruction
1
10
ms
V
WI
(1)
Write Inhibit Threshold Voltage
1
2
V
Note:
1. These parameters are characterized only.
Vcc
Vcc
(max)
Vcc
(min)
V
WI
Reset
State
t
PUW
t
VSL
Read Instructions
Allowed
Device is Fully
Accessible
Program, Erase and Write Instructions are Ignored
CS Must Track Vcc
Time
Figure 18. Power-up Timing and Voltage Levels
SPECIFICATIONS AND TIMING DIAGRAMS
NexFlash Technologies, Inc.
23
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
Table 8. DC Electrical Characteristics (Preliminary)
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
(2)
6
pf
Cout
Output Capacitance
V
OUT
= 0V
(2)
8
pf
I
LI
Input Leakage
2
A
I
LO
I/O Leakage
2
A
I
CC1
Standby Current
CS = VCC, VIN = GND or VCC
50
A
I
CC2
Power-down Current
CS = VCC, VIN = GND or VCC
1
5
A
I
CC3
Operating Current
C = 0.1VCC / 0.9.VCC at 25 MHz
4
mA
Read Data
DO = Open
I
CC4
Operating Current
CS = VCC
15
mA
Page Program
I
CC5
Operating Current
CS = VCC
15
mA
Write Status Register
I
CC6
Operating Current
CS = VCC
15
mA
Sector Erase
I
CC7
Operating Current
CS = VCC
15
mA
Bulk Erase
V
IL
Input Low Voltage
0.5
Vccx0.3
V
V
IH
Input High Voltage
Vccx0.7
Vcc +0.4
V
V
OL
Output Low Voltage
I
OL
= 1.6 mA
0.4
V
V
OH
Output High Voltage
I
OH
= 100 A
V
CC
0.2
V
Notes:
1. See Preliminary Designation.
2. Tested on sample basis and specified through design and characterization data. TA=25 C, Vcc 3V, Frequency 20MHz.
0.8 Vcc
0.7 Vcc
0.3 Vcc
0.2 Vcc
Input Levels
Input and Output
Timing Reference Levels
Figure 19. AC Measurement I/O Waveform
Table 9. AC Measurement Conditions
Symbol
Parameter
Min
Max
Unit
C
L
Load Capacitance
30
30
pF
T
R
, T
F
Input Rise and Fall Times
5
ns
V
IN
Input Pulse Voltages
0.2VCC to
0.8VCC
V
O
UT
Output Timing Reference Voltages
0.3VCC to
0.7VCC
V
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.
24
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
Table 10. AC Electrical Characteristics (Preliminary)
(5)
Symbol
Alt
Description
Min
Typ
Max
Unit
F
R
f
C
Clock Frequency, for Fast Read(0Bh)
D.C.
33
MHz
and all other instructions except Read Data (03h)
f
R
Clock Frequency for Read Data instruction
D.C.
20
MHz
t
CH
(1)
t
CLH
, t
CLL
Clock High, Clock Low Time, for Fast Read (0Bh)
12
ns
and all other instructions except Read Data (03h)
t
CL
(1)
t
CRLH
, t
CRLL
Clock High, Clock Low Time
18
ns
for Read Data instruction
t
CLCH
(2)
Clock Rise Time (peak to peak)
0.1
V/ns
t
CHCL
(2)
Clock Fall Time (peak to peak)
0.1
V/ns
t
SLCH
t
CSS
CS Active Setup Time (relative to CLK)
10
ns
t
CHSL
CS Not Active Hold Time (relative to CLK)
10
ns
t
DVCH
t
DSU
Data In Setup Time
5
ns
t
CHDX
t
DH
Data In Hold Time
5
ns
t
CHSH
CS Active Hold Time (relative to CLK)
10
ns
t
SHCH
CS Not Active Setup Time (relative to CLK)
10
ns
t
SHSL
t
CSH
CS Deselect Time
100
ns
t
SHQZ
(2)
t
DIS
Output Disable Time
15
ns
t
CLQV
t
V
Clock Low to Output Valid
15
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
HLCH
HOLD Setup Time (relative to CLK)
10
ns
t
CHHH
HOLD Hold Time (relative to CLK)
10
ns
t
HHCH
HOLD Setup Time (relative to CLK)
10
ns
t
CHHL
HOLD Hold Time (relative to CLK)
10
ns
t
HHQX
(2)
t
LZ
HOLD to Output Low-Z
15
ns
t
HLQZ
(2)
t
HZ
HOLD to Output High-Z
20
ns
t
WHSL
(4)
Write Protect Setup Time
20
ns
t
SHWL
(4)
Write Protect Hold Time
100
ns
t
DP
(2)
CS High to Power-down Mode
3
s
t
RES1
(2)
CS High to Standby Mode without Electronic
3
s
Signature Read
t
RES2
(2)
CS High to Standby Mode with Electronic
1.8
s
Signature Read
t
W
Write Status Register Cycle Time
5
15
ms
t
PP
Page Program Cycle Time
2
5
ms
t
SE
Sector Erase Cycle Time
2
3
s
t
BE
Bulk Erase Cycle Time 25P10 and 25P20
3
6
s
Bulk Erase Cycle Time 25P40
5
10
s
Notes:
1. t
CH
+ t
CL
must be less than or equal to 1/ f
C
.
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set at 1.
5. See Preliminary Designation page 31.
NexFlash Technologies, Inc.
25
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
CS
CLK
DO
LSB OUT
DI
tQLQH
tQHQL
*
LEAST SIGNIFICANT ADDRESS BIT (LSB) IN
tCLQV
tCLQX
tSHQZ
tCL
tCH
tCLQX
tCLQV
*
Figure 20. Serial Output Timing
Figure 21. Input Timing
(High Impedance)
tCLCH
MSB IN
LSB IN
tCHSL
tSHSL
tCHCL
tDVCH
tSLCH
tCHDX
tCHSH
tSHCH
CS
CLK
DI
DO
CS
HOLD
CLK
DO
DI
tCHHL
tHLCH
tCHHH
tHHQX
tHHCH
tHLQZ
Figure 22. Hold Timing
26
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
PACKAGING INFORMATION
8-Pin SOIC 150-mil (Package Code N)
1
D
E1 E
A
SEATING PLANE
A1
L
C
e
b
CP
Package Dimensions
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
1.524
1.727
0.060
0.068
A1
0.102
0.249
0.004
0.0098
b
0.351
0.508
0.0138
0.0201
C
0.190
0.250
0.0075
0.0098
D
4.801
4.953
0.189
0.195
E
5.842
6.198
0.230
0.244
E1
3.784
3.887
0.147
0.153
e
1.27BSC
0.050 BSC
h
0.254
0.406
0.010
0.016
L
0.406
0.889
0.016
0.035
0
o
8
o
0
o
8
o
CP
0.10
0.004
Notes:
1. Controlling dimensions: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and should be measured from the
bottom of the package.
4. Formed leads shall be planar with respect to one
another within .0004 inches at the seating plane.
NexFlash Technologies, Inc.
27
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
E
D
L
A
SEATING PLANE
A3
e
b
A2
A1
D1
E1
Notes:
1. Advanced Packaging Information;
please contact NexFlash for the
latest minimum and maximum
specifications.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should
be measured from the bottom of the
package.
8-Contact MLP* 5x6mm (Package Code P)
Package Dimensions
Millimeters
Inches
Symbol
Typ.
Min
Max
Typ.
Min
Max
A
0.90
0.80
1.00
0.0354
0.0315
0.0394
A1
0.00
0.05
0.0000
0.0203
A2
0.65
0.0256
A3
0.20
0.0079
b
0.40
0.35
0.45
0.0157
0.0138
0.0189
D
6.00
0.2362
D1
3.95
0.1560
E
5.00
0.1870
E1
4.19
0.1650
e
1.27 BSC
0.0500 BSC
L
0.73
0.68
0.78
0.0288
0.0268
0.0308
* Also refered to as VFQFP, QFN, and SON
28
NexFlash Technologies, Inc.
PRELIMINARY
NXSF036A-0303
08/01/03
NX25P10
NX25P20
NX25P40
PRELIMINARY DESIGNATION
The "Preliminary" designation on a
NexFlash data sheet
indicates that the product is not fully characterized. The
specifications are subject to change and are not g
ua
ran-
teed.
NexFlash or an authorized sales representative
should be consulted for current information before using this
product.
IMPORTANT NOTICE
NexFlash reserves the right to make changes to the
products contained in this publication in order to improve
design, performance or reliability.
NexFlash assumes no
responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and
makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect
representative operating parameters, and may vary de-
pending upon a user's specific application. While the
information in this publication has been carefully checked,
NexFlash shall not be liable for any damages arising as a
result of any error or omission.
LIFE SUPPORT POLICY
NexFlash does not recommend the use of any of it's
products in life support applications where the failure or
malfunction of the product can reasonably be expected to
cause failure in the life support system or to significantly
affect its safety or effectiveness. Products are not
authorized for use in such applications unless
NexFlash
receives written assurances, to it's satisfaction, that:
(a)
the risk of injury or damage has been minimized;
(b)
the user assumes all such risks; and
(c)
potential liability of
NexFlash is adeq
ua
tely pro-
tected under the circumstances.
TRADEMARKS
NexFlash is a trademark of NexFlash Technologies, Inc. All
other marks are the property of their respective owner.
ORDERING INFORMATION
Order Part No.
Density
Voltage
Package
Temperature
NX25P10-VNI
1M-bit
2.7V-3.6V
8-pin SOIC 150mil
-40 to +85C
NX25P10-VPI
1M-bit
2.7V-3.6V
8-contact MLP 5x6mm
-40 to +85C
NX25P20-VNI
2M-bit
2.7V-3.6V
8-pin SOIC 150mil
-40 to +85C
NX25P20-VPI
2M-bit
2.7V-3.6V
8-contact MLP 5x6mm
-40 to +85C
NX25P40-VNI
4M-bit
2.7V-3.6V
8-pin SOIC 150mil
-40 to +85C
NX25P40-VPI
4M-bit
2.7V-3.6V
8-contact MLP 5x6mm
-40 to +85C
NexFlash Technologies, Inc.
29
PRELIMINARY
NXSF036A-0303
08/01/03
1
2
3
4
5
6
7
8
9
10
11
12
NX25P10
NX25P20
NX25P40
Document Revision History
Date
Rev
Description of Revision
04/29/03
A
Document Written
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