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Электронный компонент: W2465S

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W2465
8K
8 CMOS STATIC RAM
Publication Release Date: April 1997
- 1 -
Revision A8
GENERAL DESCRIPTION
The W2465 is a slow-speed, low-power CMOS static RAM organized as 8192
8 bits that operates
on a single 5-volt power supply. This device is manufactured using Winbond's high performance
CMOS technology.
FEATURES
Low power consumption:
-
Active: 250 mW (max.)
-
Standby: 100
W (max.)(LL-version)
250
W (max.)(L-version)
Access time: 70/100 nS (max.)
Single +5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Available packages: 28-pin 600 mil DIP,
330 mil SOP and 300 mil skinny DIP
PIN CONFIGURATION
A8
A9
1
2
3
4
5
25
26
27
28
NC
A7
A6
A5
A12
A4
A3
A2
A1
6
7
8
9
20
21
22
23
A11
A10
I/O8
I/O7
I/O6
I/O5
10
11
12
13
16
17
18
19
A0
I/O2
I/O3
I/O1
14
15
I/O4
CS
CS
OE
WE
V
DD
V
SS
24
BLOCK DIAGRAM
A0
.
CS1
A12
WE
I/O1
I/O8
OE
V
V
.
.
DATA I/O
ARRAY
DECODER
CORE
CS2
.
CONTROL
DD
SS
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A12
Address Inputs
I/O1
-
I/O8
Data Inputs/Outputs
CS1, CS2
Chip Select Inputs
WE
Write Enable Input
OE
Output Enable Input
V
DD
Power Supply
V
SS
Ground
NC
No Connection
W2465
- 2 -
TRUTH TABLE
CS1
CS2
OE
WE
MODE
I/O1
-
I/O8
V
DD
CURRENT
H
X
X
X
Not Selected
High Z
I
SB
, I
SB
1
X
L
X
X
Not Selected
High Z
I
SB
, I
SB
1
L
H
H
H
Output Disable
High Z
I
DD
L
H
L
H
Read
Data Out
I
DD
L
H
X
L
Write
Data In
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Supply Voltage to V
SS
Potential
-0.5 to +7.0
V
Input/Output to V
SS
Potential
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to +150
C
Operating Temperature
0 to +70
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(V
DD
= 5V
10%, V
SS
= 0V, T
A
= 0 to 70
C)
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input Low Voltage
V
IL
-
-0.5
-
+0.8
V
Input High Voltage
V
IH
-
+2.2
-
V
DD
+0.5
V
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-2
-
+2
A
Output Leakage
Current
I
LO
V
I/O
= V
SS
to V
DD
CS1
= V
IH
(min.) or CS2
= V
IL
(max.) or
OE
= V
IH
(min.) or
WE
= V
IL
(max.)
-2
-
+2
A
Output Low Voltage
V
OL
I
OL
= +4.0 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -1.0 mA
2.4
-
-
V
Operating Power
Supply Current
I
DD
CS1
= V
IL
(max.),
CS2 = V
IH
(min.)
70
-
-
70
mA
I/O = 0 mA,
Cycle = min.
Duty = 100%
100
-
-
60
mA
Standby Power Supply
Current
I
SB
CS1
= V
IH
(min.) or CS2
= V
IL
(max.), Cycle = min.
Duty = 100%
-
-
3
mA
I
SB
1
CS1
V
DD
-0.2V
LL
-
-
20
A
or CS2
0.2V
L
-
-
50
A
Note: Typical characteristics are at V
DD
= 5 V, T
A
= 25
C.
W2465
Publication Release Date: April 1997
- 3 -
Revision A8
CAPACITANCE
(V
DD
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
8
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0.6V to 2.4V
Input Rise and Fall Times
5 nS
Input and Output Timing Reference Level
1.5V
Output Load
C
L
= 100 pF, I
OH
/I
OL
= -1 mA/4 mA
AC Test Loads and Waveform
90%
90%
5 nS
10%
5 nS
10%
R1 1000 ohm
5V
OUTPUT
R2
660 ohm
100 pF
Including
Jig and
Scope
2.4V
0.6V
5V
OUTPUT
R1 1000 ohm
5 pF
Including
Jig and
Scope
R2
660 ohm
(For T
CLZ1, CLZ2, OLZ, CHZ1, CHZ2, OHZ, WHZ, OW
T
T
T
T
T
T
T
)
W2465
- 4 -
AC Characteristics, continued
(V
DD
= 5V
10%, V
SS
= 0V, T
A
= 0 to 70
C)
Read Cycle
PARAMETER
SYM.
W2465-70
W2465-10
UNIT
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
T
RC
70
-
100
-
nS
Address Access Time
T
AA
-
70
-
100
nS
Chip Select Access Time
CS1
T
ACS
1
-
70
-
100
nS
CS2
T
ACS
2
-
70
-
100
nS
Output Enable to Output Valid
T
AOE
-
35
-
50
nS
Chip Selection to Output in Low Z
CS1
T
CLZ1
*
5
-
10
-
nS
CS2
T
CLZ2
*
5
-
10
-
nS
Output Enable to Output in Low Z
T
OLZ
*
5
-
5
-
nS
Chip Deselection to Output in High Z
CS1
T
CHZ1
*
-
30
-
35
nS
CS2
T
CHZ2
*
-
30
-
35
nS
Output Disable to Output in High Z
T
OHZ
*
-
30
-
35
nS
Output Hold from Address Change
T
OH
10
-
10
-
nS
* These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER
SYM.
W2465-70
W2465-10
UNIT
MIN.
MAX.
MIN.
MAX.
Write Cycle Time
T
WC
70
-
100
-
nS
Chip Selection to End of Write
CS1
T
CW1
60
-
80
-
nS
CS2
T
CW2
60
-
80
-
nS
Address Valid to End of Write
T
AW
60
-
80
-
nS
Address Setup Time
T
AS
0
-
0
-
nS
Write Pulse Width
T
WP
45
-
60
-
nS
Write Recovery Time
CS1
,
WE
T
WR1
0
-
0
-
nS
CS2
T
WR2
0
-
0
-
nS
Data Valid to End of Write
T
DW
30
-
40
-
nS
Data Hold from End of Write
T
DH
0
-
0
-
nS
Write to Output in High Z
T
WHZ
*
-
30
-
30
nS
Output Disable to Output in High Z
T
OHZ
*
-
30
-
30
nS
Output Active from End of Write
T
OW
0
-
0
-
nS
* These parameters are sampled but not 100% tested.
W2465
Publication Release Date: April 1997
- 5 -
Revision A8
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
D
OUT
OH
T
AA
T
RC
T
OH
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
D
OUT
T
ACS1
T
ACS2
T
CLZ1
T
CLZ2
T
CHZ1
T
CHZ2
Read Cycle 3
(Output Enable Controlled)
Address
OE
CS1
CS2
D
OUT
T
CLZ2
T
ACS2
T
CLZ1
T
OLZ
T
ACS1
T
AOE
T
AA
T
RC
T
OH
T
CHZ1
T
OHZ
T
CHZ2
W2465
- 6 -
Timing Waveforms, continued
Write Cycle 1
Address
OE
CS1
CS2
WE
(1, 4)
D
OUT
D
IN
T
WR1
T
WC
T
CW1
T
CW2
T
WR2
T
WP
T
AS
T
OHZ
T
DW
T
DH
T
AW
Write Cycle 2
(OE = V
IL
Fixed)
Address
CS1
CS2
WE
(2)
(3)
D
OUT
D
IN
T
DW
T
DH
T
OW
T
OH
T
WR2
T
WC
T
CW1
T
WR1
T
CW2
T
AW
T
WP
T
AS
T
WHZ(1, 4)
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from D
OUT
are the same as the data written to D
IN
during the write cycle.
3. D
OUT
provides the read data for the next address.
4. Transition is measured
500 mV from steady state with C
L
= 5 pF. This parameter is guaranteed but not 100% tested.
W2465
Publication Release Date: April 1997
- 7 -
Revision A8
DATA RETENTION CHARACTERISTICS
(T
A
= 0 to 70
C)
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
for Data Retention
V
DR
CS1
V
DD
-0.2V, or
CS2
0.2V
2.0
-
-
V
Data Retention Current
I
DDDR
CS1
V
DD
-0.2V, or
CS2
0.2V
LL
-
-
10
A
V
DD
= 3V
L
-
-
20
A
Chip Deselect to Data
Retention Time
T
CDR
See data retention
waveforms
0
-
-
nS
Operation Recovery Time
T
R
T
RC
*
-
-
nS
T
RC
* = Read Cycle Time
DATA RETENTION WAVEFORMS
4.5V
V
> 2V
DATA RETENTION MODE
CS1
4.5V
CS2 < 0.2V
CS2
=
=
=
DR
- 0.2V
CS1 > V
DD
V
DD
T
R
T
CDR
V
IH
V
IL
V
IH
V
IL
ORDERING INFORMATION
PART NO.
ACCESS TIME
(nS)
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (
A)
PACKAGE
W2465-70LL
70
70
20
600 mil DIP
W2465-10L
100
60
50
600 mil DIP
W2465S-70LL
70
70
20
330 mil SOP
W2465S-10L
100
60
50
330 mil SOP
W2465K-70LL
70
70
20
300 mil Skinny
W2465K-10L
100
60
50
300 mil Skinny
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
W2465
- 8 -
BONDING PAD DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
20
22
23
24
25
26
X
Y
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
O4
O5
O6
19
O7
CS1
A10
OE
A11
A9
A8
CS2
WE
V
SS
V
SS
V
DD
27S-1
27S-2
21
V
DD
18
13S-1
13S-2
03
PAD NO.
X
Y
1
-226.95
1526.15
2
-350.95
1526.15
3
-484.10
1526.15
4
-608.10
1526.15
5
-739.75
1526.15
6
-741.75
1315.10
7
-741.75
-1231.85
8
-741.75
-1456.30
9
-610.60
-1456.30
10
-481.50
-1466.30
11
-343.80
-1466.30
12
-206.10
-1466.30
13S-1
-73.00
-1401.10
13S-2
-8.35
-1212.80
14
60.10
-1466.30
15
193.30
-1466.30
16
332.40
-1466.30
17
465.60
-1466.30
18
603.30
-1466.30
19
738.15
-1456.30
20
740.15
-1221.45
21
740.15
1310.80
22
738.15
1526.15
23
606.50
1526.15
24
482.50
1526.15
25
349.35
1526.15
26
225.35
1526.15
27S-1
94.20
1526.15
27S-2
-50.40
1456.10
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to V
DD
or left floating in the PCB layout.
W2465
Publication Release Date: April 1997
- 9 -
Revision A8
PACKAGE DIMENSIONS
28-pin P-DIP
Seating Plane
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
1.63
1.47
0.064
0.058
Notes:
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
B
c
D
e
A
L
S
A
A
1
2
E
0.060
1.52
0.210
5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.540
0.550
0.545
13.72
13.97
13.84
17.02
15.24
14.99
15.49
0.600
0.590
0.610
2.29
2.54
2.79
0.090
0.100
0.110
B
1
1
e
E
1
a
1.460
1.470
37.08
37.34
0
15
0.090
2.29
0.650
0.630
16.00
16.51
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
15
0
e
A
2
A
a
c
E
Base Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
28
1
15
14
28-pin P-DIP Skinny
1.63
1.47
0.064
0.058
Symbol
Min.
Nom.
Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
B
c
D
e
A
L
S
A
A
1
2
E
0.060
1.52
0.175
4.45
0.010
0.125
0.016
0.130
0.018
0.135
0.022
3.18
0.41
0.25
3.30
0.46
3.43
0.56
0.008
0.120
0.370
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.293
0.288
0.283
7.44
7.32
7.19
9.40
7.87
7.62
8.13
0.310
0.300
0.320
2.29
2.54
2.79
0.090
0.100
0.110
B
1
1
e
E
1
a
1.388
1.400
35.26
35.56
0
15
0.055
1.40
0.350
0.330
8.38
8.89
15
0
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
Notes:
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
e
A
A
a
c
E
Base Plane
Mounting Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
28
15
1
14
2
W2465
- 10 -
Package Dimensions, continued
28-pin SO Wide Body
1. Dimension D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimension D & E include mold mismatch
and determined at the mold parting line.
.
0.25
0.20
0.010
0.008
Notes:
Symbol
Min. Nom.
Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
b
c
D
e
H
E
L
y
A
A
L
E
1
2
E
0.014
0.36
0.112
2.85
0.004
0.093
0.014
0.098
0.016
0.103
0.020
2.36
0.36
0.10
2.49
0.41
2.62
0.51
0.059
0.004
0
10
0.713
0.067
0.733
0.075
1.50
18.11
1.70
18.62
1.91
0.477
0.465
0.453
12.12
11.81
11.51
10
0
0.10
8.53
8.41
8.28
0.336
0.331
0.326
0.71
0.91
1.12
0.028
0.036
0.044
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
1.12
1.27
1.42
0.044
0.050
0.056
S
1.19
0.047
2
1
A
28
15
14
1
e
S
E
H
b
Seating Plane
A A
y
L
L
e
c
See Detail F
D
E
E
1
1
e
Detail F
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792647
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
Note: All data and specifications are subject to change without notice.