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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision
1.0
-1 -
W6692A
PCI Bus ISDN S/T-Controller
Data Sheet
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision
1.0
-2 -
The information described in this document is the exclusive intellectual property of Winbond
Electronics Corp and shall not be reproduced without permission from Winbond.
Winbond is providing this document only for reference purposes for W6692A-based system design.
Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to
change without notice.
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision
1.0
-3 -
TABLE OF CONTENTS
1. GENERAL DESCRIPTION................................................................................................................................................. 8
2. FEATURES............................................................................................................................................................................ 8
3. PIN CONFIGURATION ..................................................................................................................................................... 9
4. PIN DESCRIPTION........................................................................................................................................................... 12
5
. SYSTEM DIAGRAM AND APPLICATIONS ................................................................................................................ 15
6. BLOCK DIAGRAM ........................................................................................................................................................... 16
7. FUNCTIONAL DESCRIPTIONS..................................................................................................................................... 17
7.1 M
AIN
B
LOCK
F
UNCTIONS
................................................................................................................................................... 17
7.2 L
AYER
1 F
UNCTIONS
D
ESCRIPTIONS
................................................................................................................................... 18
7.2.1 S/T Interface Transmitter/Receiver ............................................................................................................................ 18
7.2.2 Receiver Clock Recovery And Timing Generation...................................................................................................... 22
7.2.3 Layer 1 Activation/Deactivation ................................................................................................................................ 22
7.2.3.1 States Descriptions And Command/Indication Codes .......................................................................................... 22
7.2.3.2 State Transition Diagrams................................................................................................................................... 24
7.2.4 D Channel Access Control ......................................................................................................................................... 28
7.2.5 Frame Alignment ....................................................................................................................................................... 28
7.2.5.1 FAinfA_1fr ......................................................................................................................................................... 29
7.2.5.2 FAinfB_1fr ......................................................................................................................................................... 29
7.2.5.3 FAinfD_1fr ......................................................................................................................................................... 29
7.2.5.4 FAinfA_kfr ......................................................................................................................................................... 29
7.2.5.5 FAinfB_kfr ......................................................................................................................................................... 29
7.2.5.6 FAinfD_kfr ......................................................................................................................................................... 30
7.2.5.7 Faregain.............................................................................................................................................................. 30
7.2.6 Multiframe Synchronization....................................................................................................................................... 30
7.2.7 Test Functions ........................................................................................................................................................... 31
7.3 S
ERIAL
I
NTERFACE
B
US
..................................................................................................................................................... 33
7.4 B C
HANNEL
S
WITCHING
.................................................................................................................................................... 33
7.6 D C
HANNEL
HDLC C
ONTROLLER
...................................................................................................................................... 35
7.6.1 D Channel Message Transfer Modes.......................................................................................................................... 36
7.6.2 Reception of Frames in D Channel ............................................................................................................................ 36
7.6.3 Transmission of Frames in D Channel ....................................................................................................................... 37
7.7 B C
HANNEL
HDLC C
ONTROLLER
...................................................................................................................................... 38
7.7.1 Reception of Frames in B Channel
...................................................................................................................... 38
7.7.2 Transmission of Frames in B Channel........................................................................................................................ 39
7.8 GCI M
ODE
S
ERIAL
I
NTERFACE
B
US
.................................................................................................................................... 40
7.8.1 GCI Mode C/I0 Channel Handling ............................................................................................................................ 41
7.8.2 GCI Mode Monitor Channel Handling....................................................................................................................... 41
7.9 PCI/MP I
NTERFACE
C
IRCUIT
............................................................................................................................................. 42
7.9.1 PCI Slave Mode And Configuration Serial EEPROM ................................................................................................ 42
7.9.2 8-bit Microprocessor Interface .................................................................................................................................. 44
7.10 P
ERIPHERAL
C
ONTROL
..................................................................................................................................................... 44
8. REGISTER DESCRIPTIONS ............................................................................................................................................. 46
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision
1.0
-4 -
8.1 C
HIP
C
ONTROL AND
D_
CH
HDLC
CONTROLLER
................................................................................................................. 46
8.1.1 D_ch receive FIFO
D_RFIFO Read Address 00H/00H ........................................................................................ 48
8.1.2 D_ch transmit FIFO
D_XFIFO Write Address 04H/01H ...................................................................................... 48
8.1.3 D_ch command register
D_CMDR Write Address 08H/02H ............................................................................... 49
8.1.4 D_ch Mode Register
D_MODE Read/Write Address 0CH/03H ............................................................................... 49
8.1.5 Timer 1 Register
TIMR1 Read/Write Address 10H/04H ...................................................................................... 50
8.1.6 Interrupt Status Register
ISTA Read_clear Address 14H/05H ...................................................................... 51
8.1.7 Interrupt Mask Register
IMASK Read/Write Address 18H/06H ............................................................................... 52
8.1.8 D_ch Extended Interrupt Register
D_EXIR Read_clear Address 1CH/07H ............................................................. 52
8.1.9 D_ch Extended Interrupt Mask Register
D_EXIM Read/Write Address 20H/08H .................................................... 53
8.1.10 D_ch Status Register
D_XSTA Read Address 24H/09H .................................................................................. 53
8.1.11 D_ch Receive Status Register
D_RSTA Read Address 28H/0AH ....................................................................... 54
8.1.12 D_ch SAPI Address Mask
D_SAM Read/Write Address 2CH/0BH..................................................................... 54
8.1.13 D_ch SAPI1 Register
D_SAP1 Read/Write Address 30H/0CH ............................................................................ 55
8.1.14 D_ch SAPI2 Register
D_SAP2 Read/Write Address 34H/0DH .............................................................................. 55
8.1.15 D_ch TEI Address Mask
D_TAM Read/Write Address 38H/0EH .......................................................................... 55
8.1.16 D_ch TEI1 Register
D_TEI1 Read/Write Address 3CH/0FH............................................................................. 55
8.1.17 D_ch TEI2 Register
D_TEI2 Read/Write Address 40H/10H.............................................................................. 56
8.1.18 D_ch Receive Frame Byte Count High
D_RBCH Read Address 44H/11H ......................................................... 56
8.1.19 D_ch Receive Frame Byte Count Low
D_RBCL Read Address 48H/12H........................................................... 56
8.1.20 Timer 2
TIMR2 Write Address 4CH/13H.......................................................................... 57
8.1.21 Layer 1_Ready Code
L1_RC Read/Write Address 50H/14H................................................. 57
8.1.22 Control Register
CTL Read/Write Address 54H/15H............................................................................................. 57
8.1.23 Command/Indication Receive Register
CIR Read Address 58H/16H ................................................................. 58
8.1.24 Command/Indication Transmit Register
CIX Read/Write Address 5CH/17H ..................................................... 59
8.1.25 S/Q Channel Receive Register
SQR Read Address 60H/18H ......................................................................... 59
8.1.26 S/Q Channel Transmit Register
SQX Read/Write Address 64H/19H.............................................................. 60
8.1.27 Peripheral Control Register
PCTL Read/Write Address 68H/1AH ............................................................. 60
8.1.28 Monitor Receive Channel 0
MO0R Read Address 6CH/1BH ...................................................................... 61
8.1.29 Monitor Transmit Channel 0
MO0X Read/Write Address 70H/1CH ........................................................... 61
8.1.30 Monitor Channel 0 Interrupt Register
MO0I Read_clear Address 74H/1DH .............................................. 62
8.1.31 Monitor Channel 0 Control Register
MO0C Read/Write Address 78H/1EH ...................................................... 62
8.1.32 GCI Mode Control/Status Register
GCR Read/Write Address 7CH/1FH.................................. 62
8.1.33 Peripheral Address Register
XADDR Read/Write Address F4H/3DH......................................................... 64
8.1.34 Peripheral Data Register
XDATA Read/Write Address F8H/3EH .............................................................. 65
8.1.35 Serial EEPROM Control Register
EPCTL Read/Write Address FCH/3FH.......................................................... 65
8.1.36 Monitor Receive Channel 1 Register
MO1R Read Address 6DH/40H ............................................................. 66
8.1.37 Monitor Transmit Channel 1 Register
MO1X Read/Write Address 71H/41H .................................................. 66
8.1.38 Monitor Channel 1 Interrupt Register
MO1I Read_clear Address 75H/42H ............................................... 66
8.1.39 Monitor Channel 1 Control Register
MO1C Read/Write Address 79H/43H....................................................... 67
8.1.40 GCI IC1 Receive Register
IC1R Read Address 6EH/44H ........................................................................ 67
8.1.41 GCI IC1 Transmit Register
IC1X Read/Write Address 72H/45H.............................................................. 67
8.1.42 GCI IC2 Receive Register
IC2R Read Address 6FH/46H......................................................................... 68
8.1.43 GCI IC2 Transmit Register
IC2X Read/Write Address 73H/47H.............................................................. 68
8.1.44 GCI CI1 Indication Register
CI1R Read Address 7DH/48H .................................................................... 68
8.1.45 GCI CI1 Command Register
CI1X Read/Write Address 7EH/49H ........................................................... 68
8.1.46 GCI Extended Interrupt Register
GCI_EXIR Read_clear Address 76H/4AH ......................................................... 69
8.1.47 GCI Extended Interrupt Mask Register
GCI_EXIM Read/Write Address 7AH/4BH ............................................... 69
8.2 B1 HDLC
CONTROLER
...................................................................................................................................................... 69
8.2.1 B1_ch receive FIFO
B1_RFIFO Read Address 80H/20H ............................................................................... 71
8.2.2 B1_ch transmit FIFO
B1_XFIFO Write Address 84H/21H .......................................................................... 71
8.2.3 B1_ch command register
B1_CMDR Read/Write Address 88H/22H ............................................................... 71
8.2.4 B1_ch Mode Register
B1_MODE Read/Write Address 8CH/23H........................................................................ 72
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision
1.0
-5 -
8.2.5 B1_ch Extended Interrupt Register
B1_EXIR Read_clear Address 90H/24H........................................................... 73
8.2.6 B1_ch Extended Interrupt Mask Register
B1_EXIM Read/Write Address 94H/25H ................................................. 74
8.2.7 B1_ch Status Register
B1_STAR Read Address 98H/26H.................................................................................... 74
8.2.8 B1_ch Address Mask Register 1
B1_ADM1 Read/Write Address 9CH/27H ......................................................... 75
8.2.9 B1_ch Address Mask Register 2
B1_ADM2 Read/Write Address A0H/28H ......................................................... 75
8.2.10 B1_ch Address Register 1
B1_ADR1 Read/Write Address A4H/29H ................................................................. 76
8.2.11 B1_ch Address Register 2
B1_ADR2 Read/Write Address A8H/2AH................................................................. 76
8.2.12 B1_ch Receive Frame Byte Count Low
B1_RBCL Read Address ACH/2BH .......................................................... 76
8.2.13 B1_ch Receive Frame Byte Count High
B1_RBCH Read Address B0H/2CH ......................................................... 76
8.2.14 B1_ch Transmit Idle Pattern
B1_IDLE Read/Write Address B4H/2DH ................................................................. 77
8.3 B2 HDLC
CONTROLLER
.................................................................................................................................................... 77
8.4 PCI C
ONFIGURATION
R
EGISTER
......................................................................................................................................... 78
8.4.1 Device/Vendor ID Register
Read Address 00
H
........................................................................................... 79
8.4.2 Status/Command Register
Read/Write Address 04
H
..................................................................................... 80
8.4.3 Class Code/Revision ID Register
Read Address 08
H
.................................................................................... 81
8.4.4 Header Type/Latency Timer Register
Read Address 0C
H
............................................................................... 82
8.4.5 Base Address Register 0
Read/Write Address 10
H
.................................................................................... 82
8.4.6 Base Address Register 1
Read/Write Address 14
H
....................................................................................... 84
8.4.7 Subsystem/Subsystem Vendor ID Register
Read Address 2C
H
...................................................................... 84
8.4.8 Interrupt Line Register
Read/Write Address 3C
H
........................................................................................ 84
8.4.9 Capability Pointer
Read Address 34
H
......................................................................................................... 85
8.4.10 Power Management Capability
Read Address 40
H
.................................................................................... 85
8.4.11 Power Management Control/Status
Read/Write Address 44
H
.................................................................... 86
9. ELECTRICAL CHARACTERISTICS ............................................................................................................................... 88
9.1 A
BSOLUTE
M
AXIMUM
R
ATING
........................................................................................................................................... 88
9.2 P
OWER
S
UPPLY
.................................................................................................................................................................. 88
9.3 DC C
HARACTERISTICS
....................................................................................................................................................... 88
9.4 P
RELIMINARY
S
WITCHING
C
HARACTERISTICS
..................................................................................................................... 90
9.4.1 PCM Interface Timing ............................................................................................................................................... 90
9.4.2 Serial EEPROM Timing............................................................................................................................................. 91
9.4.3 Peripheral Interface Timing....................................................................................................................................... 92
9.4.5 8-bit Microprocessor Timing...................................................................................................................................... 92
9.5 AC T
IMING
T
EST
C
ONDITIONS
........................................................................................................................................... 95
10. ORDERING INFORMATION .......................................................................................................................................... 95
11. PACKAGE SPECIFICATIONS ........................................................................................................................................ 96
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