Preliminary W742C810

4-BIT MICROCONTROLLER

Publication Release Date: May 1999

- 1 -

Revision A1

Table of Contents-

1. GENERAL DESCRIPTION ..........................................................................................................................3

2. FEATURES..................................................................................................................................................3

3. PIN CONFIGURATION ................................................................................................................................4

4. PIN DESCRIPTION......................................................................................................................................5

4.1 Pad List ..................................................................................................................................................6

5. BLOCK DIAGRAM .......................................................................................................................................8

6. FUNCTIONAL DESCRIPTION ....................................................................................................................9

6.1 Program Counter (PC) ...........................................................................................................................9

6.2 Stack Register (STACK) ........................................................................................................................9

6.3 Program Memory (ROM) .......................................................................................................................9

6.3.1 ROM Page Register (ROMPR) ................................................................................................10

6.4 Data Memory (RAM) ............................................................................................................................10

6.4.1 Architecture ..............................................................................................................................10

6.4.2 Page Register (PAGE) .............................................................................................................11

6.4.3 WR Page Register (WRP) .......................................................................................................12

6.4.4 Data Bank Register (DBKR).....................................................................................................12

6.5 Accumulator (ACC) ..............................................................................................................................13

6.6 Arithmetic and Logic Unit (ALU)...........................................................................................................13

6.7 Main Oscillator......................................................................................................................................13

6.8 Sub-Oscillator.......................................................................................................................................13

6.9 Dividers ................................................................................................................................................13

6.10 Dual-clock operation...........................................................................................................................14

6.11 Watchdog Timer (WDT).....................................................................................................................15

6.12 Timer/Counter ....................................................................................................................................15

6.12.1 Timer 0 (TM0).........................................................................................................................15

6.12.2 Timer 1 (TM1).........................................................................................................................16

6.12.3 Mode Register 0 (MR0) ..........................................................................................................17

6.12.4 Mode Register 1 (MR1) ..........................................................................................................17

6.13 Interrupts ............................................................................................................................................18

6.14 Stop Mode Operation .........................................................................................................................19

6.14.1 Stop Mode Wake-up Enable Flag for RC Port (SEF).............................................................19

Preliminary W742C810

- 2 -

6.15 Hold Mode Operation .........................................................................................................................19

6.15.1 Hold Mode Release Enable Flag (HEF) .................................................................................20

6.15.2 Interrupt Enable Flag (IEF) .....................................................................................................21

6.15.3 Port Enable Flag (PEF) ..........................................................................................................21

6.15.4 Hold Mode Release Condition Flag (HCF) .............................................................................22

6.15.5 Event Flag (EVF) ....................................................................................................................22

6.16 Reset Function ...................................................................................................................................23

6.17 Input/Output Ports RA, RB & RD .......................................................................................................23

6.17.1 Port Mode 0 Register (PM0)...................................................................................................24

6.17.2 Port Mode 1 Register (PM1)...................................................................................................24

6.17.3 Port Mode 2 Register (PM2)...................................................................................................25

6.17.4 Port Mode 5 Register (PM5)...................................................................................................25

6.18 Input Ports RC....................................................................................................................................25

6.18.1 Port Status Register 0 (PSR0) ...............................................................................................26

6.19 Output Port RE & RF .........................................................................................................................27

6.20 DTMF Output Pin (DTMF)..................................................................................................................27

6.20.1 DTMF register.........................................................................................................................28

6.20.2 Dual Tone Control Register (DTCR).......................................................................................28

6.21 MFP Output Pin (MFP).......................................................................................................................28

6.22 LCD Controller/Driver.........................................................................................................................30

6.22.1 LCD RAM addressing method................................................................................................31

6.22.2 The output waveforms for the LCD driving mode ...................................................................31

7. ABSOLUTE MAXIMUM RATINGS ............................................................................................................33

8. DC CHARACTERISTICS...........................................................................................................................33

9. AC CHARACTERISTICS ...........................................................................................................................34

10. INSTRUCTION SET TABLE ....................................................................................................................35

11. PACKAGE DIMENSIONS........................................................................................................................41

Preliminary W742C810

Publication Release Date: May 1999

- 3 -

Revision A1

1. GENERAL DESCRIPTION

The W742C810 is a high-performance 4-bit microcontroller (

�

C) that provides an LCD driver. The

device contains a 4-bit ALU, two 8-bit timers, two dividers (for two oscillators) in dual-clock operation,
a 40

�

4 LCD driver, six 4-bit I/O ports (including 1 output port for LED driving), and one channel

DTMF generator. There are also five interrupt sources and 8-level subroutine nesting for interrupt
applications. The W742C810 operates on very low current and has one power reduction mode, that is
the dual-clock slow operation, which helps to minimize power dissipation.

2. FEATURES

�

Operating voltage: 2.4V

3.6V

�

Dual-clock operation

�

Main oscillator

Connect to 3.58 MHz crystal only

�

Sub-oscillator

Connect to 32768 Hz crystal only

�

Memory

8192 x 16 bit program ROM (including 32K x 4 bit look-up table)

1024 x 4 bit data RAM (including 16 nibbles x 16 pages working registers)

40 x 4 LCD data RAM

�

24 input/output pins

Port for input only: 1 ports/4 pins

Input/output ports: 3 ports/12 pins

High sink current output port for LED driving: 1 port /4 pins

Port for output only: 1 port/ 4 pins

�

Power-down mode

Hold function: no operation (main oscillator and sub-oscillator still operate)

Stop function: no operation (only main oscillator stops but sub-oscillator still operates)

Dual-clock slow mode: system is operated by the sub-oscillator (F

OSC

= Fs and Fm is stopped)

�

Five types of interrupts

Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1)

One external interrupt (RC Port)

�

LCD driver output

40 segments x 4 commons

1/4 duty 1/3 bias driving mode

Clock source should be the sub-oscillator clock in the dual-clock operation mode

�

MFP output pin

Output is software selectable as modulating or nonmodulating frequency

Works as frequency output specified by Timer 1

Preliminary W742C810

- 4 -

�

DTMF output pin

Output is one channel Dual Tone Multi-frequency signal for dialling

�

Two built-in 14-bit frequency dividers

Divider0: the clock source is the output of the main oscillator

Divider1: the clock source is the output of the sub-oscillator

�

Two built-in 8-bit programmable countdown timers

Timer 0: one of two internal clock frequencies (F

OSC

/4 or F

OSC

/1024) can be selected

Timer 1: with auto-reload function, and one of three internal clock frequencies (F

OSC,

OSC

/64 or

Fs) can be selected by MR1 register; the specified frequency can be delivered to MFP pin

�

Built-in 18/15-bit watchdog timer selectable for system reset; enable the watch dog timer or not is
determined by code option

�

Powerful instruction set: 131 instructions

�

8-level subroutine (include interrupt) nesting

3. PIN CONFIGURATION

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62

9 10 11 12 13 14 15 16 17 18 19

RC1

RC0

RB3

RB2

RB1

RB0

RA3

RA1

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

R
E
1

R
E

SEG22

SEG21

SEG20

SEG19

RA0

MFP

RA2

20 21 22 23 24

61 60 59 58 57

N
C

SEG32

RD0

RC3

RC2

25 26 27 28 29

56 55 54 53 52

RD2

RD1

100

RE0

RD3

SEG18

SEG17

SEG16

SEG15

SEG14

N
C

R
E
3

R
F
0

F
1

F
2

R
F
3

V
S
S

S
E
G
0

S
E
G
1

S
E

S
E
G
3

S
E
G
4

S
E
G
5

S
E

S
E
G
7

S
E
G
8

S
E
G
9

S
E

1
0

S
E
G
1
1

S
E
G
1
2

S
E

1
3

N
C

S
E
G
3
3

S
E

3
4

S
E
G
3
5

S
E
G
3
6

S
E
G
3
7

S
E
G
3
8

S
E
G
3
9

C
O

V
D
D
2

V
D
D
1

D
H
2

D
H
1

U
T
2

N
2

V
D
D

X
O
U
T
1

N
1

D
T

R
E
S

N
C

Preliminary W742C810

Publication Release Date: May 1999

- 5 -

Revision A1

4. PIN DESCRIPTION

SYMBOL

I/O

FUNCTION

XIN2

Input pin for sub-oscillator.
Connected to 32.768 Khz crystal only.

XOUT2

Output pin for sub-oscillator with internal oscillation capacitor. Connected
to 32.768 Khz crystal only.

XIN1

Input pin for main-oscillator.
Connected to 3.58MHz crystal to generate system clock.

XOUT1

Output pin for main-oscillator.
Connected to 3.58MHz crystal to generate system clock.

RA0-RA3

I/O

Input/Output port.
Input/output mode specified by port mode 1 register (PM1).

RB0-RB3

I/O

Input/Output port.
Input/output mode specified by port mode 2 register (PM2).

RC0-RC3

4-bit port for input only.

Each pin has an independent interrupt capability.

RD0-RD3

I/O

Input/Output port

Input/Output mode specified by port mode 5 register (PM5)

RE0-RE3

Output port only. With high sink current capacity for the LED application.

RF0-RF3

Output port only.

MFP

Output pin only.
This pin can output modulating or nonmodulating frequency, or Timer 1
clock output specified by mode register 1 (MR1).

DTMF

This pin can output dual-tone multifrequency signal for dialling.

RES

System reset pin with pull-high resistor.

SEG0-

SEG39

LCD segment output pins.

COM0-

COM3

LCD common signal output pins.

DH1, DH2

Connection terminals for voltage doubler (halver) capacitor.

DD1

DD2

Positive (+) supply voltage terminal.

Refer to Functional Description.

Positive power supply (+).

Negative power supply (-).

Preliminary W742C810

- 6 -

4.1 Pad List

** Shrink factor: 1.000000; Date: 1997/12/31; Time: 14:46:10
** Window: (xl = -1410.00, yl = -1595.00), (xh = 1410.00, yh = 1595.00)
** Windows size: width = 2820.00, length = 3190.00

PAD NO.

PAD NAME

PIN NAME

RE1

-1302.45

1336.70

RE2

-1302.45

1205.53

RE3

-1302.45

1075.53

RF0

-1302.45

944.00

RF1

-1302.45

817.58

RF2

-1302.45

693.58

RF3

-1302.45

569.58

VSS

-1302.45

407.95

SEG<0>

-1302.45

283.95

SEG<1>

-1302.45

159.95

SEG<2>

-1302.45

35.95

SEG<3>

-1302.45

-88.05

SEG<4>

-1302.45

-212.05

SEG<5>

-1302.45

-336.05

SEG<6>

-1302.45

-460.05

SEG<7>

-1302.45

-584.05

SEG<8>

-1302.45

-708.05

SEG<9>

-1302.45

-832.05

SEG<10>

-1302.45

-956.38

SEG<11>

-1302.45

-1086.40

SEG<12>

-1302.45

-1216.40

SEG<13>

-1302.45

-1350.40

SEG<14>

-1302.45

-1486.30

SEG<15>

-1025.28

-1489.60

SEG<16>

-895.28

-1489.60

SEG<17>

-765.28

-1489.60

SEG<18>

-635.28

-1489.60

SEG<19>

-505.28

-1489.60

SEG<20>

-375.28

-1489.60

SEG<21>

-251.28

-1489.60

Preliminary W742C810

Publication Release Date: May 1999

- 7 -

Revision A1

Pad List, continued

PAD NO.

PAD NAME

PIN NAME

SEG<22>

-127.28

-1489.60

SEG<23>

-3.28

-1489.60

SEG<24>

120.73

-1489.60

SEG<25>

244.73

-1489.60

SEG<26>

368.73

-1489.60

SEG<27>

498.73

-1489.60

SEG<28>

628.73

-1489.60

SEG<29>

758.73

-1489.60

SEG<30>

888.73

-1489.60

SEG<31>

1018.73

-1489.60

SEG<32>

1301.23

-1486.30

SEG<33>

1301.23

-1356.30

SEG<34>

1301.23

-1222.30

SEG<35>

1301.23

-1100.30

SEG<36>

1301.23

-970.30

SEG<37>

1301.23

-840.30

SEG<38>

1301.23

-716.30

SEG<39>

1301.23

-592.30

COM<2>

1301.23

-319.90

COM<1>

1301.23

-179.10

COM<0>

1301.23

-38.30

VDD2

1301.23

118.90

VDD1

1301.23

263.55

DH2

1301.23

411.73

DH1

1301.23

535.73

XOUT2

1301.23

659.73

XIN2

1301.23

783.73

VDD

1301.23

907.73

XOUT1

1301.23

1075.50

XIN1

1301.23

1205.50

DTMF

1301.23

1336.68

RES

1301.23

1466.70

MFP

1024.38

1470.00

RA0

894.38

1470.00

Preliminary W742C810

- 8 -

Pad List, ontinued

PAD NO.

PAD NAME

PIN NAME

RA1

764.38

1470.00

RA2

634.38

1470.00

RA3

504.38

1470.00

RB0

374.38

1470.00

RB1

250.38

1470.00

RB2

126.38

1470.00

RB3

2.38

1470.00

RC0

-121.63

1470.00

RC1

-245.63

1470.00

RC2

-369.63

1470.00

RC3

-499.63

1470.00

RD0

-629.63

1470.00

RD1

-759.63

1470.00

RD2

-889.63

1470.00

RD3

-1019.63

1470.00

RE0

-1302.45

1466.70

5. BLOCK DIAGRAM

LCD DRIVER

STACK
(8 Levels)

RAM

(1024*4)

ALU

Timer 0

(8 Bit)

Timing Generator

PORT RA

PORT RB

Modulation
Frequency
Pulse

SEG0~SEG39

COM0~COM4

RA0-3

RB0-3

MFP

XIN2 XOUT2 XIN1 XOUT1

VDD

VSS

ROM

(8192*16)

(look_up table
32K*4)

Timer 1

(8 Bit)

ACC

RES

Divider 0

(14 Bit)

Watch Dog Timer

(4 Bit)

HCF

PEF

HEF

IEF

Central Control

Unit

EVF

SEF

PSR0

SCR

MR0

MR1

MUL

SEL

+1(+2)

PM0

Divider 1

(12/14 Bit)

DTMF

Generator

PORT RC

RC0-3

DTMF

PORT RD

PORT RE

RD0-3

RE0-3

PORT RF

RF0-3

VDD1~VDD2,DH1~2

Preliminary W742C810

Publication Release Date: May 1999

- 9 -

Revision A1

6. FUNCTIONAL DESCRIPTION

6.1 Program Counter (PC)

Organized as a 13-bit binary counter (PC0 to PC12), the program counter generates the addresses of
the 8192

�

16 on-chip ROM containing the program instruction words. Before the jump or subroutine

call instructions are to be executed, the destination ROM page must be determined first. The
confirmation of the ROM page can be done by executing the MOV ROMPR, #I or MOV ROMPR, R
instruction. When the interrupt or initial reset conditions are to be executed, the corresponding
address will be loaded into the program counter directly. The format used is shown below.

Table 1 Vector address and interrupt priority

ITEM

ADDRESS

INTERRUPT PRIORITY

Initial Reset

0000H

INT 0 (Divider0)

0004H

1st

INT 1 (Timer 0)

0008H

2nd

INT 2 (Port RC)

000CH

3rd

INT 3 (Divider1)

0014H

4th

INT 4 (Timer 1)

0020H

5th

JP Instruction

XXXXH

Subroutine Call

XXXXH

6.2 Stack Register (STACK)

The stack register is organized as 13 bits x 8 levels (first-in, last-out). When either a call subroutine or
an interrupt is executed, the program counter will be pushed onto the stack register automatically. At
the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed
to pop the contents of the stack register into the program counter. When the stack register is pushed
over the eighth level, the contents of the first level will be lost. In other words, the stack register is
always eight levels deep.

6.3 Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 32768

�

4 bits. The program ROM is divided into four pages; the size of each page is 2048

�

16 bits. Total

ROM size is therefore 8192

�

16 bits. Before the jump or subroutine call instructions are to be

executed, the destination ROM page must be determined first. The ROM page can be selected by
executing the MOV ROMPR, #I or MOV ROMPR, R instruction. However, the branch decision
instructions (e.g. JB0, SKB0, JZ, JC, ...) must jump to the same ROM page which the branch decision
instructions are located in. The whole ROM range can store both instruction codes and the look-up
table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to
32768 elements. Instruction MOVC R is used to read the look-up table content and transfer table data
to the RAM. But before reading the addressed look-up table content, the content of the look-up table
pointer (TAB) must be determined first. The address of the look-up table element is allocated by the
content of TAB. The MOV TAB0 (TAB1, TAB2, TAB3), R instructions are used to allocate the address
of the wanted look-up table element. The TAB0 register stores the LSB 4 bits of the look-up table
address. The organization of the program memory is shown in Figure 6-1.

Preliminary W742C810

- 10 -

0000H

16 bits

8192 * 16 bits

07FFH

0400H

Each element (4 bits) of the look-up table

03FFH

0800H

0FFFH

0C00H

0BFFH

1st page

1000H

17FFH

1400H

13FFH

1C00H

1BFFH

1800H

1FFFH

2nd page

3rd page

4th page

Look-up Table address:

0000H

0FFFH

Look-up Table address:

1000H

1FFFH

Look-up Table address:

2000H

2FFFH

Look-up Table address:

3000H

3FFFH

Look-up Table address:

4000H

4FFFH

Look-up Table address:

5000H

5FFFH

Look-up Table address:

6000H

6FFFH

Look-up Table address:

7000H

7FFFH

Figure 6-1 Program Memory Organization

6.3.1 ROM Page Register (ROMPR)

The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows:

R/W

ROMPR

Note: R/W means read/write available.

Bit 3 & Bit 2 is reserved.

Bit 1, Bit 0 ROM page preselect bits:

00 = ROM page 0 (0000H - 07FFH)
01 = ROM page 1 (0800H - 0FFFH)
10 = ROM page 2 (1000H - 17FFH)
11 = ROM page 3 (1800H - 1FFFH)

6.4 Data Memory (RAM)

6.4.1 Architecture

The static data memory (RAM) used to store data is arranged as 1024

�

4 bits. The data RAM is

divided into eight banks; each bank has 128

�

4 bits. Executing the MOV DBKR,WR or MOV

DBKR,#I instruction can determine which data bank is used. The data memory can be addressed

Preliminary W742C810

Publication Release Date: May 1999

- 11 -

Revision A1

directly or indirectly. However, the data bank must be confirmed first; the page in the data bank will
be done in the indirect addressing mode, too. In indirect addressing mode, each data bank will be
divided into eight pages. Before the data memory is addressed indirectly, the page which the data
memory is located in must be confirmed. The organization of the data memory is shown in Figure 6-
2.

1st data bank

1024

address

000H

4 bits

1024 * 4 bits

07FH
080H

0FFH

2nd data bank

380H

3FFH

8th data bank

(or Working Registers bank)

00H

0FH
10H

1FH
20H

2FH

70H

7FH

:
:

1st data RAM page

(or 1st WR page)

2nd data RAM page

(or 2nd WR page)

8th data RAM page

(or 8th WR page)

3rd data RAM page

(or 3rd WR page)

(or Working Registers bank)

Figure 6-2 Data Memory Organization

The 1st and 2nd data bank (00H to 7FH & 80H to FFH) in the data memory can also be used as the
working registers (WR). This is also divided into sixteen pages. Each page contains 16 working
registers. When one page is used as WR, the others can be used as the normal data memory. The
WR page can be switched by executing the MOV WRP,R or MOV WRP,#I instruction. The data
memory cannot operate directly with immediate data, but the WR can do so. The relationship
between data memory locations and the page register (PAGE) in indirect addressing mode is
described in the next sub-section.

6.4.2 Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

R/W

PAGE

Note: R/W means read/write available.

Bit 3 is reserved.

Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits in one data bank:

000 = Page 0 (00H - 0FH)
001 = Page 1 (10H - 1FH)
010 = Page 2 (20H - 2FH)
011 = Page 3 (30H - 3FH)
100 = Page 4 (40H - 4FH)
101 = Page 5 (50H - 5FH)
110 = Page 6 (60H - 6FH)
111 = Page 7 (70H - 7FH)

Preliminary W742C810

- 12 -

6.4.3 WR Page Register (WRP)

The WR page register is organized as a 4-bit binary register. The bit descriptions are as follows:

R/W

WRP

Note: R/W means read/write available.

Bit 3, Bit 2, Bit 1, Bit 0 Working registers page preselect bits:

0000 = WR Page 0 (00H - 0FH)
0001 = WR Page 1 (10H - 1FH)
0010 = WR Page 2 (20H - 2FH)
0011 = WR Page 3 (30H - 3FH)
0100 = WR Page 4 (40H - 4FH)
0101 = WR Page 5 (50H - 5FH)
0110 = WR Page 6 (60H - 6FH)
0111 = WR Page 7 (70H - 7FH)
1000 = WR Page 8 (80H - 8FH)
1001 = WR Page 9 (90H - 9FH)
1010 = WR Page A (A0H - AFH)
1011 = WR Page B (B0H - BFH)
1100 = WR Page C (C0H - CFH)
1101 = WR Page D (D0H - DFH)
1110 = WR Page E (E0H - EFH)
1111 = WR Page F (F0H - FFH)

6.4.4 Data Bank Register (DBKR)

The data bank register is organized as a 4-bit binary register. The bit descriptions are as follows:

R/W

DBKR

Note: R/W means read/write available.

Bit 3 is reserved.

Bit 2, Bit 1, Bit 0 Data memory bank preselect bits:

000 = Data bank 0 (000H - 07FH)
001 = Data bank 1 (080H - 0FFH)
010 = Data bank 2 (100H - 17FH)
011 = Data bank 3 (180H - 1FFH)
100 = Data bank 4 (200H - 27FH)
101 = Data bank 5 (280H - 2FFH)
110 = Data bank 6 (300H - 37FH)
111 = Data bank 7 (380H - 3FFH)

Preliminary W742C810

Publication Release Date: May 1999

- 13 -

Revision A1

6.5 Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data
between the memory, I/O ports, and registers.

6.6 Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following
functions:

�

Logic operations: ANL, XRL, ORL

�

Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,
SKB3

�

Shift operations: SHRC, RRC, SHLC, RLC

�

Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is
stored in the internal registers. CF can be read out by executing MOV R, CF.

6.7 Main Oscillator

The W742C810 provides a crystal oscillation circuit to generate the system clock through external
connections. The 3.58 MHz crystal must be connected to XIN1 and XOUT1, and a capacitor must be
connected to XIN1 and VSS if an accurate frequency is needed.

XIN1

XOUT1

Crystal

3.58MHz

Figure 6-3 System clock oscillator Configuration

6.8 Sub-Oscillator

The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, only the
32768 Hz crystal can be connected to XIN2 and XOUT2, and a capacitor must be connected to XIN2
and V

if an accurate frequency is needed. The sub-oscillator will be oscillatory continuously in

STOP mode.

6.9 Dividers

Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts.
When the main oscillator starts action, the Divider0 is incremented by each clock (F

OSC

). When an

overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable
flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been
set (HEF.0 = 1), the hold state is terminated. The last 4-stage of the Divider0 can be reset by
executing CLR DIVR0 instruction. If the main oscillator is connected to the 32768 Hz crystal, the
EVF.0 will be set to 1 periodically at the period of 500 mS.

If the sub-oscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow
occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has
been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set
(HEF.4 = 1), the hold state is terminated. The last 4-stage of the Divider1 can be reset by executing
CLR DIVR1 instruction. The same as with EVF.0, the EVF.4 is set to 1 periodically. However, there

Preliminary W742C810

- 14 -

are two period times (125 mS & 500 mS) that can be selected by setting the SCR.3 bit. When SCR.3
= 0 (default), the 500 mS period time is selected; SCR.3 = 1, the 125 mS period time is selected.

6.10 Dual-clock operation

In the dual-clock mode, the clock source of the LCD frequency selector should be the sub-oscillator
clock (32768 Hz) only. So when the STOP instruction is executing, the LCD will keep working in the
dual-clock mode.

In this dual-clock mode, the normal operation is performed by generating the system clock from the
main-oscillator clock (Fm). The slow operation can be performed as required by generating the
system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow
operation is performed by resetting or setting the bit 0 of the System clock Control Register (SCR). If
the SCR.0 is reset to 0, the clock source of the system clock generator is main-oscillator clock; if the
SCR.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. In the dual-
clock mode, the main-oscillator can stop oscillating when the STOP instruction is executing or the
SCR.1 is set to 1.

When the SCR is set or reset, we must be careful in the following cases:

1. X000B

X011B: we should not exchange the F

OSC

from Fm into Fs and disable Fm

simultaneously. We can first exchange the F

OSC

from Fm into Fs, then disable the main-oscillator.

So the order should be X000B

X001B

X011B.

2. X011B

X000B: we should not enable Fm and exchange the F

OSC

from Fs into Fm

simultaneously. We can first enable the main-oscillator; the 2nd step is calling a delay subroutine
to wait until the main-oscillator is oscillating stably; then the last step is to exchange the F

OSC

from

Fs into Fm. So the order should be X011B

X001B

delay the Fm oscillating stably time

X000B.

We must remember that the X010B state is inhibitive, because it will induce the system shutdown.

The organization of the dual-clock operation mode is shown in Figure 6-4.

System Clock

Generator

Main Oscillator

XIN1

XOUT1

Sub-oscillator

XIN2

XOUT2

Fosc

Divider 0

SCR: System clock Control Register ( default = 00H )

Bit0

Bit1

Bit2

Bit3

0 : Fosc = Fm

1 : Fosc = Fs

0 : Fm enable

1 : Fm disable

0 : WDT input clock is Fosc/2048
1 : WDT input clock is Fosc/16384

enable/disable

SCR.1

STOP

HOLD

SCR.0

LCD Frequency

Selector

LCD

Divider 1

INT4

HCF.4

SCR.3(14/12 bit)

1 : 12 bit

0 : 14 bit

Daul clock operation mode:

- SCR.0 = 0, Fosc = Fm; SCR.0 = 1, Fosc = Fs
- Flcd = Fs, In STOP mode LCD work continue.

Figure 6-4 Organization of the dual-clock operation mode

Preliminary W742C810

Publication Release Date: May 1999

- 15 -

Revision A1

6.11 Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from
unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled,
and if the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
F

OSC

/2048. The input clock of the WDT can be switched to F

OSC

/16384 (or F

OSC

/2048) by setting

SCR.2 to 1 (or clearing SCR.2 to 0). The contents of the WDT can be reset by the instruction CLR
WDT. In normal operation, the application program must reset WDT before it overflows. A WDT
overflow indicates that operation is not under control and the chip will be reset. The WDT overflow
period is 1S when the system clock (F

OSC

) is 32 KHz and WDT clock input is F

OSC

/2048. When the

corresponding option code bit of the WDT set to 0, the WDT function is disabled. The organization of
the Divider0 and watchdog timer is shown in Figure 6-5.

Q10 Q11 Q12

Q14

Q13

Fosc

HEF.0

IEF.0

1. Reset

2. CLR EVF,#01H

EVF.0

Hold mode release (HCF.0)

Divider interrupt (INT0)

...

Overflow signal

WDT

Enable

Disable

SCR.2

Fosc/2048

Fosc/16384

Option code is reset to "0"

Qw1

Qw2

Qw4

Qw3

Divider0

System Reset

1. Reset

2. CLR WDT

3. CLR DIVR0

Option code is set to "1"

Figure 6-5 Organization of Divider0 and watchdog timer

6.12 Timer/Counter

6.12.1 Timer 0 (TM0)

Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TMOH),R instructions
are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to
0, and the specified value can be loaded into TM0. We can then set MR0.3 to 1; this will cause the
event flag 1 (EVF.1) to be reset, and the TM0 will start to count. When it decrements to FFH, Timer 0
stops operating and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag
has been set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set
(HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as F

OSC

/1024 or F

OSC

by setting MR0.0 to 1 or resetting MR0.0 to 0. The default timer value is F

OSC

/4. The organization of

Timer 0 is shown in Figure 6-6.

If the Timer 0 clock input is F

OSC

/4:

Desired Timer 0 interval = (preset value +1)

�

1/ F

OSC

If the Timer 0 clock input is F

OSC

/1024:

Desired Timer 0 interval = (preset value +1)

�

1024

�

1/ F

OSC

Preset value: Decimal number of Timer 0 preset value

OSC

: Clock oscillation frequency

Preliminary W742C810

- 16 -

Fosc/4

Fosc/1024

Enable

Disable

1. Reset

2. CLR EVF,#02H

8-Bit Binary

Down Counter

S
R

HEF.1

IEF.1

Hold mode release (HCF.1)

Timer 0 interrupt (INT1)

1. Reset

2. CLR EVF,#02H

EVF.1

MR0.0

(Timer 0)

Set MR0.3 to 1

3. Reset MR0.3 to 0

3.Set MR0.3 to 1

MOV TM0H,R

MOV TM0L,R

4.MOV TM0L,R or MOV TM0H,R

Figure 6-6 Organization of Timer 0

6.12.2 Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6-7. Timer 1 can
be used as to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of
three sources: F

OSC

/64, F

OSC

or FS. The source can be selected by setting bit 0 and bit1 of mode

OSC

. When the MOV TM1L, R or MOV

TM1H,R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1
down-counting will keep going on. If the bit 3 of MR1 is set (MR1.3 = 1), the content of the auto-
reload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event
flag 7 is reset (EVF.7 = 0). When the timer decrements to FFH, it will generate an underflow (EVF.7 =
1) and be auto-reloaded with the specified data, after which it will continue to count down. Then, if
interrupt enable flag 7 has been set to 1 (IEF.7 = 1), an interrupt is executed; if hold mode release
enable flag 7 is set to 1 (HEF.7 = 1), the hold state is terminated. The specified frequency of Timer 1
can be delivered to the MFP output pin by programming bit2 of MR1. Bit 3 of MR1 can be used to
make Timer 1 stop or start counting.

In a case where Timer 1 clock input is FT:
Desired Timer 1 interval = (preset value +1) / FT

Desired frequency for MFP output pin = FT

�

(preset value + 1)

�

2 (Hz)

Preset value: Decimal number of Timer 1 preset value
F

OSC

: Clock oscillation frequency

Auto-reload buffer

8 bits

Set MR1.3 to 1

Underflow signal

EVF.7

MFP

MFP signal

MR1.2

output pin

8-Bit Binary

Down Counter

circuit

Reset

Disable

Enable

Fosc/64

Fosc

MR1.0

(Timer 1)

1. Reset
2. INT7 accept
3. CLR EVF, #80H

4. Set MR1.3 to 1

MOV TM1H,R

MOV TM1L,R

Set MR1.3 to 1

MR1.1

Figure 6-7 Organization of Timer 1

Preliminary W742C810

Publication Release Date: May 1999

- 17 -

Revision A1

For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will
output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between
the tone frequency and the preset value of TM1 is shown in the table below.

Table2 The relation between the tone frequency and the preset value of TM1

C
C

TM1 preset value
& MFP frequency

3rd octave

4th octave

5th octave

261.63

277.18

293.66

311.13

329.63

349.23

369.99

392.00

415.30

440.00

466.16

493.88

523.25

554.37

587.33

622.25

659.26

698.46

739.99

783.99

830.61

880.00

932.23

987.77

260.06

277.69

292.57

309.13

327.68

372.36

390.09

420.10

443.81

442.81

3EH

3AH

37H

34H

31H

2EH

2BH

29H

26H

22H

24H

20H

468.11

496.48

1EH

1CH

1BH

19H

18H

16H

15H

14H

13H

12H

11H

10H

528.51

564.96

585.14

630.15

655.36

712.34

744.72

780.19

819.20

862.84

910.22

963.76

130.81

138.59

146.83

155.56

164.81

174.61

185.00

196.00

207.65

220.00

233.08

246.94

7CH

75H

6FH

68H

62H

5DH

58H

53H

4EH

45H

49H

41H

131.07

138.84

146.28

156.03

165.49

174.30

184.09

195.04

207.39

221.40

234.05

248.24

Tone

frequency

Tone

frequency

TM1 preset value
& MFP frequency

Tone

frequency

TM1 preset value
& MFP frequency

Note: Central tone is A4 (440 Hz).

6.12.3 Mode Register 0 (MR0)

Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to
control the operation of Timer 0. The bit descriptions are as follows:

MR0

Note: W means write only.

Bit 0 = 0 The fundamental frequency of Timer 0 is F

OSC

/4.

= 1 The fundamental frequency of Timer 0 is F

OSC

/1024.

Bit 1 & Bit 2 are reserved

Bit 3 = 0 Timer 0 stops down-counting.
= 1 Timer 0 starts down-counting.

6.12.4 Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control
the operation of Timer 1. The bit descriptions are as follows:

MR1

Note: W means write only.

Preliminary W742C810

- 18 -

Bit 0 = 0 The internal fundamental frequency of Timer 1 is F

OSC

= 1 The internal fundamental frequency of Timer 1 is F

OSC

/64.

Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.

= 1 The fundamental frequency source of Timer 1 is the sub-oscillator frequency FS

(32.768 KHz).

Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP pin.

= 1 The specified frequency of Timer 1 is delivered at MFP pin.

Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

6.13 Interrupts

The W742C810 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and
one external interrupt source (port RC). Vector addresses for each of the interrupts are located in the
range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to
control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF
have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts
are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can also be
disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold
mode will be released momentarily and interrupt subroutine will be executed. After the RTN
instruction is executed in an interrupt subroutine, the

�

C will enter hold mode again. The operation

flow chart is shown in Figure 6-9. The control diagram is shown below.

IEF.0

IEF.1

Interrupt

Process

Circuit

Interrupt

Vector

Generator

004H

008H

014H

IEF.2

Initial Reset

MOV IEF, #I

Enable

EN INT

EVF.1

EVF.0

EVF.2

Initial Reset
CLR EVF, #I instruction

DIS INT instruction

Disable

Divider 0

overflow signal

Timer 0

underflow signal

Port RC

signal change

Timer 1

underflow signal

IEF.4

EVF.4

IEF.7

EVF.7

00CH

020H

Divider 1

overflow signal

Figure 6-8 Interrupt event control duagram

Preliminary W742C810

Publication Release Date: May 1999

- 19 -

Revision A1

6.14 Stop Mode Operation

In stop mode, all operations of the

�

C cease (excluding the operation of the sub-oscillator and Divider

1 and LCD driver), and MFP pin is kept to high state. The

�

C enters stop mode when the STOP

instruction is executed and exits stop mode when an external trigger is activated (by a falling signal
on the RC). When the designated signal is accepted, the

�

C awakens and executes the next

instruction. To prevent erroneous execution, the NOP instruction should follow the STOP command.
However, in the dual-clock slow operation mode, the STOP instruction will disable the main-oscillator;
the

�

C system is still operated by the sub-oscillator.

6.14.1 Stop Mode Wake-up Enable Flag for RC Port (SEF)

The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3).
Before port RC may be used to make the device exit the stop mode, the content of the SEF must be
set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:

SEF

Note: W means write only.

SEF.0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0
SEF.1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1
SEF.2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2
SEF.3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3

6.15 Hold Mode Operation

In hold mode, all operations of the

�

C cease, except for the operation of the oscillator, Timer, Divider,

LCD driver, DTMF generator and MFP generator. The

�

C enters hold mode when the HOLD

instruction is executed. The hold mode can be released in one of five ways: by the action of timer 0,
timer 1, divider 0, divider 1, or the RC port. Before the device enters the hold mode, the HEF, PEF,
and IEF flags must be set to define the hold mode release conditions. For more details, refer to the
instruction-set table and the following flow chart.

Preliminary W742C810

- 20 -

Divider 0, Divider 1, Timer
0, Timer 1, Signal Change
at RC Port

HOLD
Mode?

IEF

Flag Set?

PC <- (PC+1)

IEF

Flag Set?

Yes

HOLD

HEF

Flag Set?

Reset EVF Flag

Execute

Interrupt Service Routine

Reset EVF Flag

Execute

Interrupt Service Routine

Interrupt

Enable?

Interrupt

Enable?

Yes

Disable interrupt

(Note)

Note: The bit of EVF corresponding to the interrupt signal will be reset.

Figure 6-9 Hold Mode and Interrupt Operation Flow Chart

6.15.1 Hold Mode Release Enable Flag (HEF)

The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The
HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I
instruction. The bit descriptions are as follows:

HEF

Note: W means write only.

HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released.

HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released.

HEF.2 = 1 Signal change at port RC causes Hold mode to be released.

Preliminary W742C810

Publication Release Date: May 1999

- 21 -

Revision A1

HEF.3 is reserved.

HEF.4 = 1 Overflow from the Divider 1 causes Hold mode to be released.

HEF.5 & HEF.6 are reserved.

HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released.

6.15.2 Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used
to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or
EN INT is executed again. Otherwise, these interrupts can be disabled by executing DIS INT
instruction. The bit descriptions are as follows:

IEF

Note: W means write only.

IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0.

IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.

IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC.

IEF.3 is reserved.

IEF.4 = 1 Interrupt 0 is accepted by overflow from the Divider 1.

IEF.5 & IEF.6 are reserved.

IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

6.15.3 Port Enable Flag (PEF)

The port enable flag is organized as a 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or preform interrupt function, the content of the PEF must be set first.
The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:

PEF

Note: W means write only.

PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt.

PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt.

PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt.

PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.

Preliminary W742C810

- 22 -

6.15.4 Hold Mode Release Condition Flag (HCF)

The hold mode release condition flag is organized as an 8-bit binary register (HCF.0 to HCF.7). It
indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The
HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF
bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset
by the CLR EVF or MOV HEF,#I (HEF = 0) instructions. When EVF and HEF have been reset, the
corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows:

HCF

Note: R means read only.

HCF.0 = 1 Hold mode was released by overflow from the divider 0.
HCF.1 = 1 Hold mode was released by underflow from the timer 0.
HCF.2 = 1 Hold mode was released by a signal change at port RC.
HCF.3 is reserved.
HCF.4 = 1 Hold mode was released by overflow from the divider 1.
HCF.5 = 1 Hold mode was released by underflow from the timer 1.
HCF.6 and HCF.7 are reserved.

6.15.5 Event Flag (EVF)

The event flag is organized as an 8-bit binary register (EVF.0 to EVF.7). It is set by hardware and
reset by CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows:

EVF

Note: W means write only.

EVF.0 = 1 Overflow from divider 0 occurred.
EVF.1 = 1 Underflow from timer 0 occurred.
EVF.2 = 1 Signal change at port RC occurred.
EVF.3 is reserved.
EVF.4 = 1 Overflow from divider 1 occurred.
EVF.5 & EVF.6 are reserved.
EVF.7 = 1 Underflow from Timer 1 occurred.

Preliminary W742C810

Publication Release Date: May 1999

- 23 -

Revision A1

6.16 Reset Function

The W742C810 is reset either by a power-on reset or by using the external RES pin. The initial state
of the W742C810 after the reset function is executed is described below.

Program Counter (PC)

000H

TM0, TM1

Reset

MR0, MR1, PAGE registers

Reset

PSR0, SCR registers

Reset

IEF, HEF, HCF, PEF, EVF, SEF flags

Reset

WRP, DBKR register

Reset

Timer 0 input clock

OSC

Timer 1 input clock

OSC

MFP output

Low

DTMF output

Hi-Z

Input/output ports RA,RB, RD

Input mode

Output port RE & RF

High

RA, RB & RD ports output type

CMOS type

RC ports pull-high resistors

Disable

Input clock of the watchdog timer

OSC

/2048

LCD display

OFF

Table 3 The initial state after the reset function is executed

6.17 Input/Output Ports RA, RB & RD

Port RA consists of pins RA.0 to RA.3. Port RB consists of pins RB.0 to RB.3. Port RD consists of
pins RD.0 to RD.3. At initial reset, input/output ports RA, RB and RD are all in input mode. When RA,
RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0
register. But when RD is used as output port, the output type is just fixed to be CMOS output type.
Each pin of port RA, RB and RD can be specified as input or output mode independently by the PM1,
PM2 and PM5 registers. The MOVA R, RA or MOVA R, RB or MOVA R, RD instructions operate the
input functions and the MOV RA, R or MOV RB, R or MOV RD, R operate the output functions. For
more details, refer to the instruction table and Figure 6-10 and Figure 6-11.

Input/Output Pin of the RA(RB)

I/O PIN

RA.n(RB.n)

DATA

BUS

Buffer

Output

PM0.0(PM0.1)

PM1.n (PM2.n)

MOVA R,RA(MOVA R,RB) instruction

MOV RA,R(MOV RB,R)

instruction

Enable

Figure 6-10 Architecture of RA (RB) Input/Output Pins

Preliminary W742C810

- 24 -

Input/Output Pin of the RD

I/O PIN

RD.n

DATA

BUS

Buffer

Output

PM5.n

MOVA R,RD instruction

MOV RD,R instruction

Enable

Figure 6-11 Architecture of RD Input/Output pins

6.17.1 Port Mode 0 Register (PM0)

The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used
to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction.
The bit descriptions are as follows:

PM0

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type.
Bit 1 = 0 RB port is CMOS output type. Bit 1 = 1 RB port is NMOS open drain output type.
Bit 2 = 0 RC port pull-high resistor is disabled. Bit 2 = 1 RC port pull-high resistor is enabled.
Bit 3 is reserved.

6.17.2 Port Mode 1 Register (PM1)

The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used
to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit
descriptions are as follows:

PM1

Note: W means write only.

Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin
Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin
Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin
Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin
At initial reset, port RA is input mode (PM1 = 1111B).

Preliminary W742C810

Publication Release Date: May 1999

- 25 -

Revision A1

6.17.3 Port Mode 2 Register (PM2)

The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used
to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit
descriptions are as follows:

PM2

Note: W means write only.

Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin
Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin
Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin
Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin

At initial reset, the port RB is input mode (PM2 = 1111B).

6.17.4 Port Mode 5 Register (PM5)

The port mode 5 register is organized as a 4-bit binary register (PM5.0 to PM5.3). PM5 can be used
to control the input/output mode of port RD. PM5 is controlled by the MOV PM5, #I instruction. The bit
descriptions are as follows:

PM5

Note: W means write only.

Bit 0 = 0 RD.0 works as output pin; Bit 0 = 1 RD.0 works as input pin
Bit 1 = 0 RD.1 works as output pin; Bit 1 = 1 RD.1 works as input pin
Bit 2 = 0 RD.2 works as output pin; Bit 2 = 1 RD.2 works as input pin
Bit 3 = 0 RD.3 works as output pin; Bit 3 = 1 RD.3 works as input pin

At initial reset, the port RD is input mode (PM5 = 1111B).

6.18 Input Ports RC

Port RC consists of pins RC.0 to RC.3. Each pin of port RC can be connected to a pull-up resistor,
which is controlled by the port mode 0 register(PM0). When the PEF, HEF, and IEF corresponding to
the RC port are set, a signal change at the specified pins of port RC will execute the hold mode
release or interrupt subroutine. Port status register 0 (PSR0) records the status of ports RC, i.e., any
signal changes on the pins that make up the ports. PSR0 can be read out and cleared by the MOV R,
PSR0, and CLR PSR0 instructions. In addition, the falling edge signal on the pin of port RC specified
by the instruction MOV SEF, #I will cause the device to exit the stop mode. Refer to Figure 6-12 and
the instruction table for more details.

Preliminary W742C810

- 26 -

Signal

change

detector

PEF.0

PSR0.0

PSR0.2

DATA BUS

RC.0

PSR0.3

PEF.3

Reset

CLR PSR0

HCF.2

INT 2

Reset

CLR EVF, #I

EVF.2

HEF.2

IEF.2

Falling

Edge

detector

Falling

Edge

detector

Falling

Edge

detector

Falling

Edge

detector

SEF.0

SEF.1

SEF.2

SEF.3

To Wake Up Stop Mode

Signal

change

detector

PSR0.1

RC.1

PEF.1

Signal

change

detector

PEF.2

RC.2

Signal

change

detector

RC.3

PM0.2

MOV PEF, #I

Figure 6-12 Architecture of Input Ports RC

6.18.1 Port Status Register 0 (PSR0)

Port status register 0 is organized as a 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or
cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

PSR0

Note: R means read only.

Preliminary W742C810

Publication Release Date: May 1999

- 27 -

Revision A1

Bit 0 = 1 Signal change at RC.0

Bit 1 = 1 Signal change at RC.1

Bit 2 = 1 Signal change at RC.2

Bit 3 = 1 Signal change at RC.3

6.19 Output Port RE & RF

Output port RE is used as an output of the internal RT port. When the MOV RE, R instruction is
executed, the data in the RAM will be output to port RT through port RE. It provides a high sink
current to drive an LED. RF port is just used as an output port. When the MOV RF, R instruction is
executed, the data in the RAM will be output to RF.

6.20 DTMF Output Pin (DTMF)

This pin should output the dual tone multi-frequency signal from the DTMF generator. There is a
DTMF register that can specify the wanted low/high frequency, and the Dual Tone Control Register
(DTCR) can control whether the dual tone will be output or not. The tones are divided into two groups
(low group and high group); one tone from each group is selected to represent a digit. The relation
between the DTMF signal and the corresponding touch tone keypad is shown in Figure 6-13.

Row/Col

Frequency

697 Hz

770 Hz

852 Hz

941 Hz

1209 Hz

1336 Hz

1477 Hz

1633 Hz

Figure 6-13 The relation between the touch tone keypad and the frequency

Preliminary W742C810

- 28 -

6.20.1 DTMF register

DTMF register is organized as a 4-bit binary register. By controlling the DTMF register, one tone of
the low/high group can be selected. The MOV DTMF,R instruction can specify the wanted tones. The
bit descriptions are as follows:

DTMF

Note: W means write only.

Selected tone

1209 Hz

High

1336 Hz

group

1477 Hz

1633 Hz

697 Hz

Low

770 Hz

group

852 Hz

941 Hz

Note: X means this bit do not care.

6.20.2 Dual Tone Control Register (DTCR)

Dual tone control register is organized as a 4-bit binary register. The output of the dual or single tone
will be controlled by this register. The MOV DTCR,#I instruction can specify the wanted status. The bit
descriptions are as follows:

DTCR

Note: W means write only.

Bit 0 = 1 Low group tone output is enabled.

Bit 1 = 1 High group tone output is enabled.

Bit 2 = 1 DTMF output is enabled. When Bit 2 is reset to 0, the DTMF output pin will be Hi-Z state.

Bit 3 is reserved.

6.21 MFP Output Pin (MFP)

The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is
determined by mode register 1 (MR1). The organization of MR1 is shown in Figuer 6-7. When bit 2 of
MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal
from among DC, 4096Hz, 2048Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2
Hz, or 1 Hz (when using a 32.768 KHz crystal). The MOV MFP, #I instruction is used to specify the
modulation output combination. The data specified by the 8-bit operand and the MFP output pin are
shown on the next page.

Preliminary W742C810

Publication Release Date: May 1999

- 29 -

Revision A1

Table 4 The relation between the MFP output frequncy and the data specified by 8-bit operand

(Fosc = 32.768 KHz)

R7 R6

FUNCTION

Low level

128 Hz

64 Hz

0 0

8 Hz

4 Hz

2 Hz

1 Hz

High level

128 Hz

64 Hz

0 1

8 Hz

4 Hz

2 Hz

1 Hz

2048 Hz

2048 Hz * 128 Hz

2048 Hz * 64 Hz

1 0

2048 Hz * 8 Hz

2048 Hz * 4 Hz

2048 Hz * 2 Hz

2048 Hz * 1 Hz

4096 Hz

4096 Hz * 128 Hz

4096 Hz * 64 Hz

1 1

4096 Hz * 8 Hz

4096 Hz * 4 Hz

4096 Hz * 2 Hz

4096 Hz * 1 Hz

Preliminary W742C810

- 30 -

6.22 LCD Controller/Driver

The W742C810 can directly drive an LCD with 40 segment output pins and 4 common output pins for
a total of 40

�

4 dots. The LCD driving mode is 1/3 bias 1/4 duty. The alternating frequency of the

LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. The structure of the LCD alternating frequency
(FLCD) is shown in Figure 6-14.

Selector

Fw/512

Fw/256

Fw/128

Fw/64

Sub-oscillator clock

LCD

Figure 6-14 LCD alternating frequency (FLCD) circuit diagram

Fw = 32.768 KHz, the LCD frequency is as shown in the table below.

Table 5 The relartionship between the F

LCD

and the duty cycle

LCD Frequency

Fw/512 (64 Hz)

Fw/256 (128Hz)

Fw/128 (256 Hz)

Fw/64 (512 Hz)

1/4 duty

16 Hz

32 Hz

64 Hz

128 Hz

Corresponding to the 40 LCD drive output pins, there are 40 LCD data RAM segments. Instructions
such as MOV LPL,R, MOV LPH,R, MOV @LP,R, and MOV R,@LP are used to control the LCD data
RAM. The data in the LCD data RAM are transferred to the segment output pins automatically without
program control. When the bit value of the LCD data RAM is "1," the LCD is turned on. When the bit
value of the LCD data RAM is "0," LCD is turned off. The contents of the LCD data RAM (LCDR) are
sent out through the segment0 to segment39 pins by a direct memory access. The relation between
the LCD data RAM and segment/common pins is shown below.

Table 6 The relation between the LCDR and segment/common pins used as LCD drive output pins

COM3

COM2

COM1

COM0

LCD DATA RAM

OUTPUT PIN

BIT 3

BIT 2

BIT 1

BIT 0

LCDR00

SEG0

0/1

LCDR01

SEG1

0/1

LCDR26

SEG38

0/1

LCDR27

SEG39

0/1

Preliminary W742C810

Publication Release Date: May 1999

- 31 -

Revision A1

The LCDON instruction turns on the LCD display (even in HOLD mode), and the LCDOFF instruction
turns off the LCD display. At initial reset, all the LCD segments are unlit. When the initial reset state
ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON
must be executed.

6.22.1 LCD RAM addressing method

There are 40 LCD RAMs (LCDR00 - LCDR27) that should be indirectly addressed. The LCD RAM
pointer (LP) is used to point to the address of the wanted LCD RAM. The LP is organized as 6-bit
binary register. The MOV LPL,R and MOV LPH,R instructions can load the LCD RAM address to the
LP from R. The MOV @LP,R and MOV R,@LP instructions can access the pointed LCD RAM
content.

6.22.2 The output waveforms for the LCD driving mode

1/3 bias 1/4 duty Lighting System (Example)

Normal Operating Mode

COM0

VDD2
VDD1
VSS

VDD

VDD2
VDD1
VSS

VDD

COM1

COM2

VDD2
VDD1
VSS

VDD

VDD2
VDD1
VSS

VDD

COM3

VDD2
VDD1
VSS

VDD

VDD2
VDD1
VSS

VDD

LCD driver
outputs for
only seg. on
COM0 side
being lit

LCD driver
outputs for
only seg. on
COM1 side
being lit

Preliminary W742C810

Publication Release Date: May 1999

- 33 -

Revision A1

7. ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

UNIT

Supply Voltage to Ground Potential

-0.3 to +7.0

Applied Input/Output Voltage

-0.3 to +7.0

Power Dissipation

120

Ambient Operating Temperature

0 to +70

�

Storage Temperature

-55 to +150

�

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

8. DC CHARACTERISTICS

-V

= 3.0 V, Fm = 3.58 MHz, Fs = 32.768 KHz, T

= 25

�

C, LCD on; unless otherwise specified)

PARAMETER

SYM.

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Op. Voltage

2.4

3.6

Op. Current (Crystal type)

OP1

No load (Ext-V)

In dual-clock normal
operation

0.7

1.0

Op. Current (Crystal type)

OP3

No load (Ext-V)

In dual-clock slow
operation and when Fm
is stopped

�

Hold Current (Crystal
type)

HM1

Hold mode No load
(Ext-V)

In dual-clock normal
operation

450

�

Hold Current (Crystal
type)

HM3

Hold mode No load
(Ext-V)

In dual-clock slow
operation and when Fm
is stopped

�

Stop Current (Crystal
type)

SM1

Stop mode No load
(Ext-V)

In dual-clock normal
operation

�

Input Low Voltage

0.3 V

Input High Voltage

0.7 V

Preliminary W742C810

- 34 -

DC Characteristics, continued

PARAMETER

SYM.

CONDITIONS

MIN.

TYP.

MAX.

UNIT

MFP Output Low Voltage

= 3.5 mA

0.4

MFP Output High Voltage

= 3.5 mA

2.4

Port RA, RB, RD and RF
Output Low Voltage

ABL

= 2.0 mA

0.4

Port RA, RB, RD and RF
Output high Voltage

ABH

= 2.0 mA

2.4

LCD Supply Current

LCD

All Seg. ON

�

SEG0-SEG39 Sink Current
(Used as LCD output)

OL1

= 0.4V

LCD

= 0.0V

�

SEG0-SEG39 Drive
Current
(Used as LCD output)

OH1

= 2.4V

LCD

= 3.0V

�

Port RE Sink Current

= 0.9V

Port RE Source Current

= 2.4V

0.4

1.2

DTMF Output DC level

TDC

= 5K

= 2.5 to 3.8V

1.1

2.8

DTMF Distortion

= 5K

= 2.5 to 3.8V

-30

-23

DTMF Output Voltage

Low group, R

= 5K

130

150

170

mVrms

Pre-emphasis

Col/Row

DTMF Output Sink Current

= 0.5V

0.2

Pull-up Resistor

Port RC

100

350

1000

RES Pull-up Resistor

RES

100

500

9. AC CHARACTERISTICS

PARAMETER

SYM.

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Op. Frequency

OSC

Crystal type

3.58

MHz

Instruction cycle time

One machine cycle

4/F

OSC

Reset Active Width

RAW

OSC

= 32.768 KHz

�

Interrupt Active Width

IAW

OSC

= 32.768 KHz

�

Preliminary W742C810

Publication Release Date: May 1999

- 35 -

Revision A1

10. INSTRUCTION SET TABLE

Symbol Description

ACC:

Accumulator

ACC.n:

Accumulator bit n

WR:

Working Register

WRP:

WR Page register

PAGE:

Page Register

DBKR:

Data Bank Register

ROMPR:

ROM Page Register

MR0:

Mode Register 0

MR1:

Mode Register 1

PM0:

Port Mode 0

PM1:

Port Mode 1

PM2:

Port Mode 2

PM5:

Port Mode 5

PSR0:

Port Status Register 0

Memory (RAM) of address R

LP:

LCD data RAM pointer

LPL:

Low nibble of the LCD data RAM pointer

LPH:

High nibble of the LCD data RAM pointer

R.n:

Memory bit n of address R

Constant parameter

Branch or jump address

CF:

Carry Flag

ZF:

Zero Flag

PC:

Program Counter

TM0L:

Low nibble of the Timer 0 counter

TM0H:

High nibble of the Timer 0 counter

TM1L:

Low nibble of the Timer 1 counter

TM1H:

High nibble of the Timer 1 counter

TAB0:

Look-up table address buffer 0

TAB1:

Look-up table address buffer 1

TAB2:

Look-up table address buffer 2

TAB3:

Look-up table address buffer 3

IEF.n:

Interrupt Enable Flag n

Preliminary W742C810

- 36 -

Instruction Set Table, continued

HCF.n:

HOLD mode release Condition Flag n

HEF.n:

HOLD mode release Enable Flag n

SEF.n:

STOP mode wake-up Enable Flag n

PEF.n:

Port Enable Flag n

EVF.n:

Event Flag n

DTMF:

DTMF Register

DTCR:

DTMF Control Register

! =:

Not equal

AND

EX:

Exclusive OR

Transfer direction, result

[PAGE*10H+()]:

Contents of address PAGE(bit2, bit1, bit0)*10H+()

[P()]:

Contents of port P

Machine code

Mnemonic

Function

Flag affected

W/C

Arithmetic

0001 1000 0xxx xxxx

ADD

R, ACC

ACC

(R) + (ACC)

ZF, CF

1/1

0001 1100 i i i i nnnn

ADD

WRn, #I

ACC

(WRn) + I

ZF, CF

1/1

0001 1001 0xxx xxxx

ADDR

R, ACC

ACC, R

(R) + (ACC)

ZF, CF

1/1

0001 1101 i i i i nnnn

ADDR

WRn, #I

ACC, WRn

(WRn) + I

ZF, CF

1/1

0000 1000 0xxx xxxx

ADC

R, ACC

ACC

(R) + (ACC) + (CF)

ZF, CF

1/1

0000 1100 i i i i nnnn

ADC

WRn, #I

ACC

(WRn) + I + (CF)

ZF, CF

1/1

0000 1001 0xxx xxxx

ADCR

R, ACC

ACC, R

(R) + (ACC) + (CF)

ZF, CF

1/1

0000 1101 i i i i nnnn

ADCR

WRn, #I

ACC, WRn

(WRn) + I + (CF)

ZF, CF

1/1

0010 1000 0xxx xxxx

ADU

R, ACC

ACC

(R) + (ACC)

1/1

0010 1100 i i i i nnnn

ADU

WRn, #I

ACC

(WRn) + I

1/1

0010 1001 0xxx xxxx

ADUR

R, ACC

ACC, R

(R) + (ACC)

1/1

0010 1101 i i i i nnnn

ADUR

WRn, #I

ACC, WRn

(WRn) + I

1/1

0001 1010 0xxx xxxx

SUB

R, ACC

ACC

(R) - (ACC)

ZF, CF

1/1

0001 1110 i i i i nnnn

SUB

WRn, #I

ACC

(WRn) - I

ZF, CF

1/1

0001 1011 0xxx xxxx

SUBR

R, ACC

ACC, R

(R) - (ACC)

ZF, CF

1/1

0001 1111 i i i i nnnn

SUBR

WRn, #I

ACC, WR

(WR) - I

ZF, CF

1/1

0000 1010 0xxx xxxx

SBC

R, ACC

ACC

(R) - (ACC) - (CF)

ZF, CF

1/1

0000 1110 i i i i nnnn

SBC

WRn, #I

ACC

(WRn) - I - (CF)

ZF, CF

1/1

0000 1011 0xxxxxxx

SBCR

R, ACC

ACC, R

(R) - (ACC) - (CF)

ZF, CF

1/1

Preliminary W742C810

Publication Release Date: May 1999

- 37 -

Revision A1

Instruction set, continued

Machine code

Mnemonic

Function

Flag affected

W/C

0000 1111 i i i i nnnn

SBCR

WRn, #I

ACC, WRn

(WRn) - I - (CF)

ZF, CF

1/1

0100 1010 0xxx xxxx

INC

ACC, R

(R) + 1

ZF, CF

1/1

0100 1010 1xxx xxxx

DEC

ACC, R

(R) - 1

ZF, CF

1/1

Logic

0010 1010 0xxx xxxx

ANL

R, ACC

ACC

(R) & (ACC)

1/1

0010 1110 i i i i nnnn

ANL

WRn, #I

ACC

(WRn) & I

1/1

0010 1011 0xxx xxxx

ANLR

R, ACC

ACC, R

(R) & (ACC)

1/1

0010 1111 i i i i nnnn

ANLR

WRn, #I

ACC, WRn

(WRn) & I

1/1

0011 1010 0xxx xxxx

ORL

R, ACC

ACC

(R)

(ACC)

1/1

0011 1110 i i i i nnnn

ORL

WRn, #I

ACC

(WRn)

1/1

0011 1011 0xxx xxxx

ORLR

R, ACC

ACC, R

(R)

(ACC)

1/1

0011 1111 i i i i nnnn

ORLR

WRn, #I

ACC, WRn

(WRn)

1/1

0011 1000 0xxx xxxx

XRL

R, ACC

ACC

(R) EX (ACC)

1/1

0011 1100 i i i i nnnn

XRL

WRn, #I

ACC

(WRn) EX I

1/1

0011 1001 0xxx xxxx

XRLR

R, ACC

ACC, R

(R) EX (ACC)

1/1

0011 1101 i i i i nnnn

XRLR

WRn, #I

ACC, WRn

(WRn) EX I

1/1

Branch

0111 0

aaa aaaa aaaa

JMP

PC12~PC0

(ROMPR)

�

800H+L10~L0

1/1

1000 0

aaa aaaa aaaa

JB0

PC10~PC0

L10~L0; if ACC.0 = "1"

1/1

1001 0

aaa aaaa aaaa

JB1

PC10~PC0

L10~L0; if ACC.1 = "1"

1/1

1010 0

aaa aaaa aaaa

JB2

PC10~PC0

L10~L0; if ACC.2 = "1"

1/1

1011 0

aaa aaaa aaaa

JB3

PC10~PC0

L10~L0; if ACC.3 = "1"

1/1

1110 0

aaa aaaa aaaa

PC10~PC0

L10~L0; if ACC = 0

1/1

1100 0

aaa aaaa aaaa

JNZ

PC10~PC0

L10~L0; if ACC ! = 0

1/1

1111 0

aaa aaaa aaaa

PC10~PC0

L10~L0; if CF = "1"

1/1

1101 0

aaa aaaa aaaa

JNC

PC10~PC0

L10~L0; if CF != "1"

1/1

0100 1000 0xxx xxxx

DSKZ

ACC, R

(R) - 1; PC

(PC) + 2 if ACC = 0

ZF, CF

1/1

0100 1000 1xxx xxxx

DSKNZ

ACC, R

(R) - 1; PC

(PC) + 2 if ACC != 0

ZF, CF

1/1

1010 1000 0xxx xxxx

SKB0

(PC) + 2 if R.0 = "1"

1/1

1010 1000 1xxx xxxx

SKB1

(PC) + 2 if R.1 = "1"

1/1

1010 1001 0xxx xxxx

SKB2

(PC) + 2 if R.2 = "1"

1/1

1010 1001 1xxx xxxx

SKB3

(PC) + 2 if R.3 = "1"

1/1

Subroutine

0110 0

aaa aaaa aaaa

CALL

STACK

(PC)+1;

PC12 ~ PC0

(ROMPR)

�

800H+L10 ~ L0

1/1

0000 0001 0000 0000

RTN

(PC)

STACK

1/1

Preliminary W742C810

- 38 -

Instruction set, continued

Machine code

Mnemonic

Function

Flag affected W/C

Data move

1110 1nnn nxxx xxxx

MOV

WRn, R

WRn

(R)

1/1

1111 1nnn nxxx xxxx

MOV

R, WRn

(WRn)

1/1

0110 1nnn nxxx xxxx

MOVA

WRn, R

ACC, WRn

(R)

1/1

0111 1nnn nxxx xxxx

MOVA

R, WRn

ACC, R

(WRn)

1/1

0101 1001 1xxx xxxx

MOV

R, ACC

(ACC)

1/1

0100 1110 1xxx xxxx

MOV

ACC, R

ACC

(R)

1/1

1011 1 i i i i xxx xxxx

MOV

R, #I

1/1

1100 1nnn n000 qqqq

MOV

WRn, @WRq

WRn

[(DBKR)

�

80H+(PAGE)x10H +(WRq)]

1/2

1101 1nnn n000 qqqq

MOV

@WRq, WRn

[(DBKR)

�

80H+(PAGE)x10H +(WRq)]

WRn

1/2

1000 1100 0xxx xxxx

MOV

TAB0, R

TAB0

(R)

1/1

1000 1100 1xxx xxxx

MOV

TAB1, R

TAB1

(R)

1/1

1000 1110 0xxx xxxx

MOV

TAB2, R

TAB2

(R)

1/1

1000 1110 1xxx xxxx

MOV

TAB3, R

TAB3

(R)

1/1

1000 1101 0xxx xxxx

MOVC

[(TAB3)

�

1000H+(TAB2)

�

100H+(TAB1)

x10H + (TAB0)]

1/2

Input & Output

0101 1011 0xxx xxxx

MOVA

R, RA

ACC, R

[RA]

1/1

0101 1011 1xxx xxxx

MOVA

R, RB

ACC, R

[RB]

1/1

0100 1011 0xxx xxxx

MOVA

R, RC

ACC, R

[RC]

1/1

0100 1011 1xxx xxxx

MOVA

R, RD

ACC, R

[RD]

1/1

0101 1010 0xxx xxxx

MOV

RA, R

[RA]

(R)

1/1

0101 1010 1xxx xxxx

MOV

RB, R

[RB]

(R)

1/1

1010 1100 1xxx xxxx

MOV

RD, R

[RD]

(R)

1/1

0101 1110 0xxx xxxx

MOV

RE, R

[RE]

(R)

1/1

1010 1110 0xxx xxxx

MOV

RF, R

[RF]

(R)

1/1

0001 0010 i i i i i i i i

MOV

MFP, #I

[MFP]

1/1

Flag & Register

0101 1111 1xxx xxxx

MOVA

R, PAGE

ACC, R

PAGE (Page Register)

1/1

0101 1110 1xxx xxxx

MOV

PAGE, R

PAGE

(R)

1/1

0101 0110 1000 0i i i

MOV

PAGE, #I

PAGE

1/1

1001 1101 1xxx xxxx

MOV

R, WRP

WRP

1/1

1001 1100 1xxx xxxx

MOV

WRP, R

WRP

(R)

1/1

0011 0101 1000 i i i i

MOV

WRP, #I

WRP

1/1

Preliminary W742C810

Publication Release Date: May 1999

- 39 -

Revision A1

Instruction set, continued

Machine code

Mnemonic

Function

Flag affected

W/C

1001 1101 0000nnnn

MOV

WRn,DBKR

WRn

DBKR

1/1

1001 1100 0000nnnn

MOV

DBKR, WRn

DBKR

WRn

1/1

0011 0101 0000 0i i i

MOV

DBKR, #I

DBKR

1/1

0011 0100 0000 00i i

MOV

ROMPR, #I

ROMPR

1/1

1000 1000 0xxx xxxx

MOV

ROMPR, R

ROMPR

(R)

1/1

1000 1001 0xxx xxxx

MOV

R, ROMPR

(ROMPR)

1/1

0001 0011 1000 i 0 0 i

MOV

MR0, #I

MR0

1/1

0001 0011 0000 i i i i

MOV

MR1, #I

MR1

1/1

0101 1001 0xxx xxxx

MOVA

R, CF

ACC.0, R.0

1/1

0101 1000 0xxx xxxx

MOV

CF, R

(R.0)

1/1

0100 1001 0xxx xxxx

MOVA

R, HCFL

ACC, R

HCF.0~HCF.3

1/1

0100 1001 1xxx xxxx

MOVA

R, HCFH

ACC, R

HCF.4~HCF.7

1/1

0101 0011 0000 i i i i

MOV

PM0, #I

Port Mode 0

1/1

0101 0111 0000 i i i i

MOV

PM1, #I

Port Mode 1

1/1

0101 0111 1000 i i i i

MOV

PM2, #I

Port Mode 2

1/1

0011 0111 1000 i i i i

MOV

PM5, #I

Port Mode 5

1/1

0100 0000 i 0 0 i 0i i i

CLR

EVF, #I

Clear Event Flag if In = 1

1/1

0100 0001 i 0 0 i 0 i i i

MOV

HEF, #I

Set/Reset HOLD mode release Enable Flag

1/1

0101 0001 i 0 0 i 0i i i

MOV

IEF, #I

Set/Reset Interrupt Enable Flag

1/1

0100 0011 0000 i i i i

MOV

PEF, #I

Set/Reset Port Enable Flag

1/1

0101 0010 0000 i i i i

MOV

SEF, #I

Set/Reset STOP mode wake-up Enable Flag
for RC port

1/1

0101 0100 0000 i i i i

MOV

SCR, #I

SCR

1/1

0100 1111 0xxx xxxx

MOVA

R, PSR0

ACC, R

Port Status Register 0

1/1

0100 0010 0000 0000

CLR

PSR0

Clear Port Status Register 0

1/1

0101 0000 0100 0000

SET

Set Carry Flag

1/1

0101 0000 0000 0000

CLR

Clear Carry Flag

1/1

0001 0111 0000 0000

CLR

DIVR0

Clear the last 4-bit of the Divider 0

1/1

0101 0101 1000 0000

CLR

DIVR1

Clear the last 4-bit of the Divider 1

1/1

0001 0111 1000 0000

CLR

WDT

Clear WatchDog Timer

1/1

Shift & Rotate

0100 1101 0xxx xxxx

SHRC

ACC.n, R.n

(R.n+1);

ACC.3, R.3

0; CF

R.0

ZF, CF

1/1

Preliminary W742C810

- 40 -

Instruction set, continued

Machine code

Mnemonic

Function

Flag affected

W/C

0100 1101 1xxx xxxx

RRC

ACC.n, R.n

(R.n+1);

ACC.3, R.3

CF; CF

R.0

ZF, CF

1/1

0100 1100 0xxx xxxx

SHLC

ACC.n, R.n

(R.n-1);

ACC.0, R.0

0; CF

R.3

ZF, CF

1/1

0100 1100 1xxx xxxx

RLC

ACC.n, R.n

(R.n-1);

ACC.0, R.0

CF; CF

R.3

ZF, CF

1/1

LCD

1001 1000 0xxx xxxx

MOV

LPL, R

LPL

(R)

1/1

1001 1000 1xxx xxxx

MOV

LPH, R

LPH

(R)

1/1

1001 1010 0xxx xxxx

MOV

@LP, R

[(LPH)

�

10H+(LPL)]

(R)

1/1

1001 1011 0xxx xxxx

MOV

R, @LP

[

(LPH)

�

10H+(LPL)]

1/1

0000 0010 0000 0000

LCDON

LCD ON

1/1

0000 0010 1000 0000

LCDOFF

LCD OFF

1/1

DTMF

1001 1110 1xxx xxxx

MOV

DTMF, R

DTMF

(R)

1/1

0011 0100 1000 0 i i i

MOV

DTCR, #I

DTCR

1/1

Timer

1010 1010 0xxx xxxx

MOV

TM0L, R

TM0L

(R)

1/1

1010 1010 1xxx xxxx

MOV

TM0H, R

TM0H

(R)

1/1

1010 1011 0xxx xxxx

MOV

TM1L, R

TM1L

(R)

1/1

1010 1011 1xxx xxxx

MOV

TM1H, R

TM1H

(R)

1/1

Other

0000 0000 1000 0000

HOLD

Enter Hold mode

1/1

0000 0000 1100 0000

STOP

Enter Stop mode

1/1

0000 0000 0000 0000

NOP

No operation

1/1

0101 0000 1100 0000

INT

Enable interrupt function

1/1

0101 0000 1000 0000

DIS

INT

Disable interrupt function

1/1

Электронный компонент: W742C810