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W86L488
Winbond Host Interface
SD/SDIO/MMC
Memory Card Bridge
Preliminary W86L488
W86L488 Data Sheet Revision History
Pages Dates
Version
Version
on Web
Main Contents
1 08/2002
0.50
First
published.
2
12/2002
0.60
Add QFN package.
3
P6, P8, P10, P11,
P24, P25, P26,
P41, P42, P43,
P44, P45, P46
03/2003 0.70
1.Modify pin function of CLK, ACLK,
BCLK, XASN, XDRQN,
2.Revised function description of Data
Access Request & Interrupt.
3.Revised Reference Schematic
4
P30
05/2003
0.8
Revise access time to 70ns
5
P36
06/2003
0.81
Revise 48-QFN package dimension
6 P36,
P37 05/02/04
0.82
Revise 48, 64 QFN package
dimension
7
8
9
10
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of
these products can reasonably be expected to result in personal injury. Winbond customers using or selling
these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
Preliminary W86L488
Publication Release Date: February 5, 2004
- I -
Revision 0.82
Table of Content:
1.
GENERAL DESCRIPTION ......................................................................................................... 1
2.
FEATURES ................................................................................................................................. 1
3.
PIN CONFIGURATIONS ............................................................................................................ 2
3.1
W86L488Y Pin Configuration ......................................................................................... 2
3.2
W86L488AY Pin Configuration....................................................................................... 3
4.
PIN DESCRIPTIONS .................................................................................................................. 4
4.1
W86L488Y Pin Descriptions........................................................................................... 4
4.2
W86L488AY Pin Descriptions ........................................................................................ 7
5.
BLOCK DIAGRAM .................................................................................................................... 11
5.1
W86L488Y Block Diagram ........................................................................................... 11
5.2
W86L488AY Block Diagram ......................................................................................... 12
6.
REGISTER................................................................................................................................ 13
6.1
W86L488Y Register...................................................................................................... 13
6.2
W86L488AY Register ................................................................................................... 16
7.
FUCNTIONAL DESCRIPTION ................................................................................................. 19
7.1
Host Interface ............................................................................................................... 19
7.2
Card Inserting and Removing....................................................................................... 24
7.3
Reset Action.................................................................................................................. 25
7.4
Clock Source ................................................................................................................ 25
8.
ELECTRICAL CHARACTERISTICS......................................................................................... 26
8.1
Absolute Maximum Ratings*......................................................................................... 26
8.2
Recommended Operating Conditions .......................................................................... 26
8.3
Power Supply Characteristics....................................................................................... 26
8.4
Digital Characteristics ................................................................................................... 27
8.5
Timing Characteristics .................................................................................................. 27
9.
HOW TO READ THE TOP MARKING...................................................................................... 33
10.
PACKAGE DIMENSIONS......................................................................................................... 34
10.1
W86L488Y Package Dimensions ................................................................................. 34
10.2
W86L488AY Package Dimensions............................................................................... 35
11.
REFERENCE SCHEMATIC...................................................................................................... 36
11.1
W86L488Y Reference Schematic ................................................................................ 36
11.2
W86L488AY Reference Schematic .............................................................................. 39
Preliminary W86L488 Data Sheet
WINBOND HOST INTERFACE SD/SDIO/MMC
MEMORY CARD BRIDGE
Publication Release Date: February 5, 2004
- 1 -
Revision 0.82
1. GENERAL DESCRIPTION
The W86L488 is a SD/SDIO/MMC interface bridge between microprocessor and SD/SDIO/MMC
device. The data width of microprocessor is 8 or 16-bits. W86L488 supports synchronous or
asynchronous type of host interface. It also supports DMA and Interrupt type of transfer mode to
improve data transfer performance. The signals on the SD bus are captured or driven by W86L488.
W86L488 is monitored and controlled by microprocessor via internal registers. W86L488 fits for most
of IA devices, such as PDA, Cellular Phone, DSC, and MP3 player.
2. FEATURES
Compliant with SD spec. Version 1.01. (Support SDIO)
Compliant with MMC spec. Version 3.2.
Simultaneously access two ports of SD/SDIO/MMC supported. (W86L488AY only)
Support physical layer commands of SD/SDIO/MMC interface.
Support SD/MMC and SPI mode for SD/SDIO/MMC interface.
Support Keitaide-Music MMC card commands in SPI mode.
Support SDIO interrupt and bus suspend/resume operation.
Built-in 128 bytes data buffer for data transmit (send/receive).
Support two types of Host microprocessor Interface access synchronous and asynchronous.
DMA and Interrupt transfer mode supported.
Host microprocessor Interface support (Such as: Motorola's Dragon Ball series;Intel's Strong
ARM, ARM series; Hitachi's SH2 series; Fujisui's FR30)
Support 8/16 bits data bus of Microprocessor I/F.
Built-in 3.58 to 25MHz crystal driver circuit, support external oscillator or crystal clock.
Operation voltage: 2.7
~3.6V for SD/SDIO/MMC, 2.5/3.3V for Host CPU interface.
48/64-pin QFN package.
Ordering Information
PART NUMBER
DESCRIPTION
PACKAGE TYPE
PRODUCTION FLOW
W86L488Y
1Port SD/SDIO
48-PIN QFN
Commercial, 0
o
C to +70
o
C
W86L488AY
2Port SD/SDIO
64-PIN QFN
Commercial, 0
o
C to +70
o
C
Preliminary W86L488
Publication Release Date: February 5, 2004
- 2 -
Revision 0.82
3. PIN CONFIGURATIONS
3.1 W86L488Y Pin Configuration
Fig. 3-1 W86L488Y Pin Assignment (48-pin QFN).
XDA
KN/
XA
S
N
GIO3
GIO4
A3
DAT0/CDO
DAT1/I
A2
A1
XTYP2
D15/A0
D14
VDDH
D13
VSS
D12
D11
D10
D9
CLK
VDD3
VSS
CMD/CDI
DAT3/C
DAT2
XTO
XTI
D8
D7
D6
D5
D4
VSS
D3
D2
D1
D0
XI
NT
N
RS
T
N
XC
SN
XW
RL
N/
XB
E
1
XW
RHN/
XBE
0
XRDN/
XRW
N
VSS
XD
R
Q
N/
X
R
D
Y
N
HCKI
GI
O0
GI
O1
GI
O2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
RQ
S
Preliminary W86L488
Publication Release Date: February 5, 2004
- 3 -
Revision 0.82
3.2 W86L488AY Pin Configuration
Fig. 3-2 W86L488AY Pin Assignment (64-pin QFN).
XD
A
K
N
/
XA
S
N
GIO4
A3
BDAT0/BCDO
BDAT1
A2
A1
XTYP2
D15/A0
D14
VDDH
D13
VSS
D12
D11
D10
D9
BCLK
VDD3
VSS
BCMD/
ADAT3
BDAT2
XTO
D8
D7
D6
D5
D4
VSS
D3
D2
D1
D0
XI
N
T
N
RS
TN
XC
S
N
XW
R
L
N/XB
E
1
X
W
R
H
N/XB
E
0
XR
D
N
/
X
R
W
N
VS
S
X
D
RQN/XR
DY
N
HC
K
I
GI
O
0
GI
O
1
GI
O
2
1
2
3
4
5
6
7
8
9
10 11 12
17
18
19
20
21
22
23
24
33
34
35
36
49
/BIRQ
BCDI
/ACS
XT
I
GI
O
6
GI
O
3
ADAT1
ADAT0
ACLK
ACMD
BDAT3
ADAT2
A4
13 14 15 16
25
26
27
28
29
30
31
32
37
38
39
40
41
42
43
44
45
46
47
48
/AIRQ
/ACDO
/ACDI
/BCS
50
51
52
53
54
55
56
57
58
59
50
60
61
62
63
64
TEST
GI
O5
GIO7
GIO8
GIO9
GI
O
1
0
GI
O
1
1
Preliminary W86L488
Publication Release Date: February 5, 2004
- 4 -
Revision 0.82
4. PIN DESCRIPTIONS
4.1 W86L488Y Pin Descriptions
PIN NAME TYPE
DESCRIPTION
SD/SDIO/MMC Interface (VDD3 powered):
21 DAT0/CDO
DO/DI
SD/MMC mode:
Data line bit 0 signal for SD/SDIO card, data signal for MMC
card.
SPI mode:
Card data output in SPI mode.
22 DAT1/IRQ
DO/DI
SD/MMC mode:
Data line bit 1 signal for SD/SDIO card or interrupt request for
SDIO.
SPI mode:
No use.
15 DAT2
DO/DI
SD/MMC mode:
Data line bit 2 signal for SD/SDIO card or read wait for SDIO.
SPI mode:
No use.
16 DAT3/CS
DO/DI
SD/MMC mode:
Data line bit 3 or Card detect for SD/SDIO card.
SPI mode:
Card select.
17 CMD/CDI
DO/DI
SD/MMC mode:
Command response for SD/SDIO card or MMC card.
SPI mode:
Card data input.
This pin will tri-state when the command is not driven.
20 CLK DO
Clock output signal for SD/SDIO card or MMC card. This pin
will stay at high or low when card clock is not needed depends
on the state of CKDH bit setting.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 5 -
Revision 0.82
4.1
W86L488Y Pin Descriptions, continued
PIN NAME TYPE
DESCRIPTION
Crystal Driver (VDD3 powered):
13 XTI DI
Clock driver input signal, may be used as external clock input.
14
XTO
DO
Clock driver output signal.
Host Interface Signal (VDDH powered):
28
HCKI
DI
Host clock input.
35
XCSN
DI
Chip select input pin, active low.
36:38
A[3:1]
DI
Address input pins.
40 D15/A0 DI/DO
Data bus D15 pin, D[15:8] is the high byte of the data bus,
D15 also used as A0 when 8-bit CPU data size.
In 8-bit mode, internal register high byte (D15:8) will accessed
at data bus [7:0] when A0 = 1, low byte (D7:0) will accessed at
data bus [7:0] when A0 = 0.
41 D14 DI/DO
Data bus D14 pin.
44:48
D[13:9]
DI/DO
Data bus D[13:9] pins.
1:5
D[8:4]
DI/DO
Data bus D[8:4] pins, D[7:0] is the low byte of the data bus.
7:10
D[3:0]
DI/DO
Data bus D[3:0] pins.
33 XWRHN/
XBE0
DI
Type 1:
High byte (D15 to D8) write control pin, active low.
Type 2:
High byte (D15 to D8) data valid pin, active low.
34 XWRLN/
XBE1
DI
Type 1:
Low byte (D7 to D0) write control pin, active low.
Type 2:
Low byte (D7 to D0) data valid pin, active low.
11
XINTN
DO
Interrupt request pin, active low.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 6 -
Revision 0.82
4.1
W86L488Y Pin Descriptions, continued
PIN NAME TYPE
DESCRIPTION
32 XRDN/
XRWN
DI
Type 1:
Read control pin, active low.
Type 2:
Read write control pin,
1: read
0: write
30 XASN DI
Type 1:
None.
Type 2:
Bus access cycle start pin, active low.
29 XDRQN/
XRDYN
DO Type
1:
Data Access request pin, active low.
Type 2:
Bus cycle complete pin, active low.
39 XTYP2 DI
Host interface type 2 select pin,
0: type 1 mode.
1: type 2 mode.
General I/O Port Signal (VDD3 powered):
27:23 GIO[0:4] DI/DO
5-bit
general
input
output port signals. GIO0 pin can be used
as dedicate card insert detect. Input and active low in default.
Other Signal (VDDH powered):
12
RSTN
DI
Reset input, hardware reset input, active low.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 7 -
Revision 0.82
4.1
W86L488Y Pin Descriptions, continued
Pin Name Type
Description
Power:
19
VDD3
DP
Power supply 3.3V.
43
VDDH
DP
Power supply 2.5V or 3.3V for Host I/F. *
1
6, 18,
31, 42
VSS x4
DP
Ground (4 pins).
Type: DP is Power, DI is Digital Input, DO is Digital Output.
Note*1: When Host I/F voltage is 2.5V, VDDH connects to 2.5V.
When Host I/F voltage is 3.3V, VDDH connects to 3.3V
.
4.2 W86L488AY Pin Descriptions
PIN NAME TYPE
DESCRIPTION
SD/SDIO/MMC Interface (VDD3 powered):
27
30
ADAT0/ACDO
BDAT0/BCDO
DO/DI
SD/MMC mode:
Data line bit 0 signal for SD/SDIO card, data signal for MMC
card.
SPI mode:
Card data output in SPI mode.
28
31
ADAT1/AIRQ
BDAT1/BIRQ
DO/DI
SD/MMC mode:
Data line bit 1 signal for SD/SDIO card or interrupt request for
SDIO.
SPI mode:
No use.
21
18
ADAT2
BDAT2
DO/DI
SD/MMC mode:
Data line bit 2 signal for SD/SDIO card or read wait for SDIO.
SPI mode:
No use.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 8 -
Revision 0.82
4.2 W86L488AY Pin Descriptions, continued
PIN NAME TYPE
DESCRIPTION
22
19
ADAT3/ACS
BDAT3/BCS
DO/DI
SD/MMC mode:
Data line bit 3 or Card detect for SD/SDIO card.
SPI mode:
Card select.
23
20
ACMD/ACDI
BCMD/BCDI
DO/DI
SD/MMC mode:
Command response for SD/SDIO card or MMC card.
SPI mode:
Card data input.
This pin will tri-state when the command is not driven.
26
29
ACLK
BCLK
DO
Clock output signal for SD/SDIO card or MMC card. This pin
will stay at high or low when card clock is not needed depends
on the state of CKDH bit setting.
Crystal Driver (VDD3 powered):
16 XTI DI
Clock driver input signal, may be used as external clock input.
17
XTO
DO
Clock driver output signal.
Host Interface Signal (VDDH powered):
38
HCKI
DI
Host clock input.
45
XCSN
DI
Chip select input pin, active low.
47:50 A[4:1]
DI
Address input pins.
54 D15/A0 DI/DO
Data bus D15 pin, D[15:8] is the high byte of the data bus,
D15 also used as A0 when 8-bit CPU data size.
In 8-bit mode, internal register high byte (D15:8) will accessed
at data bus [7:0] when A0 = 1, low byte (D7:0) will accessed at
data bus [7:0] when A0 = 0.
55 D14 DI/DO
Data bus D14 pin.
60:64
D[13:9]
DI/DO
Data bus D[13:9] pins.
1:5
D[8:4]
DI/DO
Data bus D[8:4] pins, D[7:0] is the low byte of the data bus.
9:12
D[3:0]
DI/DO
Data bus D[3:0] pins.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 9 -
Revision 0.82
4.2 W86L488AY Pin Descriptions, continued
Pin Name Type
Description
43 XWRHN/
XBE0
DI
Type 1:
High byte (D15 to D8) write control pin, active low.
Type 2:
High byte (D15 to D8) data valid pin, active low.
44 XWRLN/
XBE1
DI
Type 1:
Low byte (D7 to D0) write control pin, active low.
Type 2:
Low byte (D7 to D0) data valid pin, active low.
42 XRDN/
XRWN
DI
Type 1:
Read control pin, active low.
Type 2:
Read write control pin,
1: read
0: write
13
XINTN
DO
Interrupt request pin,active low.
40
XASN
DI
Type 1:
None.
Type 2:
Bus access cycle start pin, active low.
39 XDRQN/
XRDYN
DO
Type 1:
Data Access request pin, active low.
Type 2:
Bus cycle complete pin, active low.
52 XTYP2 DI
Host interface type 2 select pin,
0: type 1 mode.
1: type 2 mode.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 10 -
Revision 0.82
4.2 W86L488AY Pin Descriptions, continued
PIN NAME TYPE
DESCRIPTION
General I/O Port Signal:
46,
32:36
GIO[5:0]
DI/DO
6-bit general input output port signals of port A. GIO0 pin can
be used as dedicate card insert detection of port A. Input and
active low in default (GIO[4:0] powered by VDD3, GIO5
powered by VDDH).
7, 6,
59,
53,
51,37
GIO[11:6]
DI/DO
6-bit general input output port signals of port B. GIO6 pin can
be used as dedicate card insert detection of port B. Input,
active low in default (GIO6 powered by VDD3, GIO[11:7]
powered by VDDH).
Other Signal (VDDH powered):
14
RSTN
DI
Reset input, hardware-reset input, active low.
57
TEST
DI
Test input, must connected to V
SS
.
Power:
25
VDD3
DP
Power supply 3.3V.
58
VDDH
DP
Power supply 2.5V or 3.3V for Host I/F. *
2
8, 24,
41, 56
VSS x4
DP
Ground (4 pins).
Type: DP is Power, DI is Digital Input, DO is Digital Output.
Note*2: When Host I/F voltage is 2.5V, VDDH connects to 2.5V.
When Host I/F voltage is 3.3V, VDDH connects to 3.3V
.
Preliminary W86L488
Fig. 5-1 Block Diagram of W86L488Y.
XTI
XTO
VDD
VSS
Address
Decode
Read
/Write
Controller
Data Packing
Circuit
General Port
Registers
SD/SDIO/MMC
Access Circuit
Serial to Parallel
or
Parallel to Serial
128 Bytes
Data FIFO
DMA Circuit
Interrupt Circuit
Register File
A[3:1]
XTYP2
XWRLN/XBE1
XWRHN/XBE0
XRDN/XRWN
D[15:0]/
D[7:0]
A0
CLK
CMD
Crystal
Driver
RSTN
XINTN
XDRQN
XCSN
XDAKN
XRDYN
XASN
Host I/F
Type Select
HCKI
Command
Response
Data
Packing
Circuit
DAT[3:0]
6 Bytes
CMD Reg
17 Bytes
Rsp Reg
Serial to Parallel
or
Parallel to Serial
Clock
Divider
System clock
SD Bus
Control
Publication Release Date: February 5, 2004
- 11 -
Revision 0.82
5. BLOCK DIAGRAM
5.1 W86L488Y Block Diagram
GIO[4:0]
Preliminary W86L488
Fig. 5-2 Block Diagram of W86L488AY.
XTI
XTO
VDD3
VSS
Address
Decode
Read
/Write
Controller
Data Packing
Circuit
General Port
Register
SD/SDIO/MMC
Access Circuit
Serial to Parallel
or
Parallel to Serial
128 Bytes
Data FIFO
DMA Circuit
Interrupt Circuit
Register File
A[4:1]
XTYP2
XWRLN/XBE1
XWRHN/XBE0
XRDN/XRWN
D[15:0]/
D[7:0]
A0
ACLK
ACMD
Crystal
Driver
RSTN
XINTN
XDRQN
XCSN
XDAKN
XRDYN
XASN
Host I/F
Type Select
HCKI
Command
Response
Data
Packing
Circuit
ADAT[3:0]
6 Bytes
CMD Reg
17 Bytes
Rsp Reg
Serial to Parallel
or
Parallel to Serial
Clock
Divider
SD Bus
Control
Global
Sts & Ctrl Reg.
VDDH
Publication Release Date: February 5, 2004
- 12 -
Revision 0.82
5.2 W86L488AY Block Diagram
GIO[5:0]
BDAT[3:0]
BCMD
BCLK
GIO[11:6]
Preliminary W86L488
Publication Release Date: February 5, 2004
- 13 -
Revision 0.82
6. REGISTER
The registers in the W86L488Y/AY are direct access registers and indirect access registers. The
direct access registers and indirect access registers are listed as follows:
6.1 W86L488Y Register
Addr
Content (note 2)
A[3:1]
Register
Name
(note 1)
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Direct Access Registers:
Command pipe registers / Response registers
000
Comman
d Pipe
Reg.
(WO)
Response
Reg. (RO)
0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0
Status
001
Status
Reg. (RO) 0 0 0 0 1 0 0 0
- - - -
- - - -
Control
001
Control
Reg.
(bit 8 WO,
R/W)
- - - - -
- -
0 0 0 0 0
0 0 0 1
Receive data buffer
010
Receive
Data
Buffer
(R/O)
0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0
Transmit data buffer
010
Transmit
Data
Buffer
(WO)
X X X X X
X X X X X X X
X X X X
Interrupt status
011
Interrupt
Status
Reg. (RO) 0 0 0 0 0
0 0 0
- - - -
- - - -
Interrupt enable
011
Interrupt
Enable
Reg.
(R/W)
- - - - -
- - -
0 0 0 0
0 1 1 0
GIO
data
100
General
I/O Port
Data Reg.
(
R/W)
0 0 0 X X X X X
- - - -
- - - -
Preliminary W86L488
Publication Release Date: February 5, 2004
- 14 -
Revision 0.82
GIO
control
100
General
I/O Port
Control
Reg.
(
R/W)
- - - - -
- - -
0 0 0 0
0 0 0 0
GIO interrupt status
101
General IP Interrupt
Status Reg. (
RC)
0 0 0 0 0 0 0 0
- - - - - - - -
GIO interrupt
enable
101
General IP Interrupt
Enable Reg. (
R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
Index
address
110
Index Address Reg.
(
R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
Index data register
111
Index Data Register
X X X X X X X X X X X X X
X X X
Indirect Access Registers:
Extend status
0000
Extend Status Reg.
(RO)
0 0 0 0 0 X - -
- - - - - - - -
Setting register
0000
Setting Reg. (R/W)
-
-
-
-
-
-
0 0 0 1 0 0 0 0 0 1
M_Fn S_Fn
0001
SDIO Bus Function
Reg. (RO)
1 1 1 1 1 1 1 1
- - - - - - - -
SDIO bus control
0001
SDIO Bus Control
Reg. (bit[7:6] RO,
R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
-
-
Data length (master)
0010
Master Data Format
Register (R/W)
0 0 0 0 0 0 1 0 0 0 0 0
0
0 0 0
-
-
-
-
-
-
Block count (master)
0011
Master Block Count
Register (R/W)
0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 1
-
-
Data length (slave)
0100
Slave Data Format
Register (R/W)
0 0 0 0 0 0 1 0 0 0 0 0
0
0 0 0
-
-
-
-
-
-
Block count (slave)
0101
Slave Block Count
Register (R/W)
0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 1
Nac time out register
0110
Nac Time-out
Register (R/W)
0 1 1 1 1 1 1 1 1 1 1 1
1
1 1 1
0111
Error Status Reg.
Error status
-
-
-
-
-
-
Preliminary W86L488
Publication Release Date: February 5, 2004
- 15 -
Revision 0.82
(RO)
0 0 0 0 0 0 0 0 0 0
Blv
Buffer service length
1000
Buffer Service Length Register
(RO)
0 0 0
0 0 0
0 0
- - - - - - - -
F - - - - - - d8
1000
Ready & Data Size Register
(R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
Test register
1001
Test Register (R/W)
0 0 0
0 0 0
0 0 0 0 0 0 0 0 0 0
ID Code register
1010
ID Code Register (RO)
0 1 0
0 1 0
0 0 1 0 0 0 1 1 0 0
Note 1: R/W means the register can be read and write.
RO means the register is read only.
RC means the register is read only and read clear.
WO means the register is write only.
Note 2: The data bit in the content is the initial value during hardware reset.
0: the bit value is 0.
1: the bit value is 1.
X: the bit value is unknow.
-: Undefined bit in the register and the value will read 0.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 16 -
Revision 0.82
6.2 W86L488AY Register
Addr
Content (note 2)
A[4:1]
Register
Name
(Note 1)
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Global Registers:
Global status register
1000
Global Status
Reg. (RO)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Global control register
1001
Global Control
Reg. (bit[9:8]
RO,R/W)
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
F - - - - - - d8
1010
Ready & Data
Size Register
(R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
Direct Access Registers:
Command pipe registers / Response registers
0000
Command Pipe
Reg. (WO)
Response Reg.
(RO)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Status
0001
Status Reg.
(RO)
0 0 0 0 1 0 0 0
- - - - - - - -
Control
0001
Control Reg.
(bit 8 WO,
R/W)
- - - - - - -
0
1/1
0 0 0 0 0 0 1
Receive data buffer
0010
Receive Data
Buffer (R/O)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Transmit data buffer
0010
Transmit Data
Buffer (WO)
X X X X X X X X X X X X X X X X
Interrupt status
0011
Interrupt Status
Reg. (RO)
0 0 0 0 0 0 0 0
- - - - - - - -
Interrupt enable
0011
Interrupt
Enable Reg.
(R/W)
- - - - - - - -
0 0 0 0 0 1 1 0
GIO
data
0100
General I/O
Port Data Reg.
(
R/W)
0 0 X X X X X X
- - - - - - - -
GIO
control
0100
General I/O
Port Control
Reg. (
R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
Preliminary W86L488
Publication Release Date: February 5, 2004
- 17 -
Revision 0.82
GIO interrupt status
0101
General IP
Interrupt Status
Reg. (
RC)
0 0 0 0 0 0 0 0
- - - - - - - -
GIO interrupt enable
0101
General IP
Interrupt
Enable Reg.
(
R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
Index
address
0110
Index Address
Reg. (
R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
Index data register
0111
Index Data
Register
X X X X X X X X X X X X X X X X
Indirect Access Registers:
Extend status
0000
Extend Status
Reg. (RO)
0 0 0 0 0 X - -
- - - - - - - -
Setting register
0000
Setting Reg.
(R/W)
- - - - - -
0 0 0 1 0 0 0 0 0 1
M_Fn S_Fn
0001
SDIO Bus
Function Reg.
(RO)
1 1 1 1 1 1 1 1
- - - - - - - -
SDIO bus control
0001
SDIO Bus
Control Reg.
(bit[7:6] RO,
R/W)
- - - - - - - -
0 0 0 0 0 0 0 0
-
-
Data length (master)
0010
Master Data
Format
Register (R/W)
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
-
- - - - -
Block
count
(master)
0011
Master Block
Count Register
(R/W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
-
-
Data length (slave)
0100
Slave Data
Format
Register (R/W)
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
-
- - - - -
Block
count
(slave)
0101
Slave Block
Count Register
(R/W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Nac time out register
0110
Nac Time-out
Register (R/W)
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0111
Error Status
Error
status
- - - - - -
Preliminary W86L488
Publication Release Date: February 5, 2004
- 18 -
Revision 0.82
Reg.
(RO)
0 0 0 0 0 0 0 0 0 0
Blv
Buffer service length
1000
Buffer Service
Length
Register (RO)
0 0 0 0 0 0 0 0
- - - - - - - -
F - - - - - - d8
1000
Ready & Data
Size Register
(RO)
- - - - - - - -
0 0 0 0 0 0 0 0
Test register
1001
Test Register
(R/W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Code register
1010
ID Code
Register (RO)
0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0
Note 1: R/W means the register can be read and write.
RO means the register is read only.
RC means the register is read only and read clear.
WO means the register is write only.
Note 2: The data bit in the content is the initial value during hardware reset.
0: the bit value is 0.
1: the bit value is 1.
X: the bit value is unknow.
-: Undefined bit in the register and the value will read 0.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 19 -
Revision 0.82
7. FUCNTIONAL DESCRIPTION
7.1 Host Interface
The Host interface type may be type 1 or type 2. and the data size of the data bus may be 16-bit or 8-
bit.
Host Interface Type 1:
The Host interface type 1 is selected when XTYP2 pin is low. Figure 7-1 shows the timing of 16-bit
CPU read and write in type 1. Figure 7-2 is the timing of 16-bit CPU write high byte and write low byte.
Figure 7-3 and 7-4 show the timing of CPU 8-bit data bus read and write in type 1.
A[3:1]
D[15:0]
XRDN
XWRLN
XCSN
XWRHN
DO[15:0]
DI[15:0]
Fig. 7-1 16-bit Read and Write Access in Host I/F Typ
Fig. 7-2 High Byte and Low Byte Write Access in Host I/F Type 1.
A[3:1]
D[15:0]
XWRLN
XCSN
XWRHN
DI[7:0]
DI[15:8]
e 1.
Preliminary W86L488
Fig. 7-3 CPU 8-bit Data Bus Read Access in Host I/F Type 1.
A[3:1]
D[7:0]
XRDN
XCSN
DO[15:8]
A0(D15)
DO[7:0]
Register bit [15:8] will be read.
Register bit [7:0] will be read.
Publication Release Date: February 5, 2004
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Revision 0.82
A[3:1]
D[7:0]
XWRLN
XCSN
A0(D15)
Register bit [15:8] will be write.
Register bit [7:0] will be write.
DI[7:0]
DI[15:8]
Fig. 7-4 CPU 8-bit Data Bus Write Access in Host I/F Type 1.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 21 -
Revision 0.82
Host Interface Type 2:
The Host interface type 2 is selected when XTYP2 pin is high. The data size of the CPU data bus may
be 16-bit or 8-bit and the access cycle may be in 3-cycle or 2-cycle. Figure 7-5 shows the timing of
CPU read write in type 2 and the access cycle is 3-cycle access, figure 7-6 shows the timing of CPU
read write in type 2 and the access cycle is 2-cycle access.
Fig. 7-5 Read and Write Timing in Host I/F Type 2, 3-Cycle Access.
DI[15:0]
A[3:1]
D[15:0]
XBE[1:0]
XRWN
XCSN
XRDYN
DO[15:0]
XASN
HCKI
Read cycle
Write cycle
Fig. 7-6 Read and Write Timing in Host I/F Type 2, 2-Cycle Access.
A[3:1]
D[15:0]
XBE[1:0]
XRWN
XCSN
XRDYN
DO[15:0]
DI[15:0]
XASN
HCKI
Read cycle
Write cycle
Preliminary W86L488
Publication Release Date: February 5, 2004
- 22 -
Revision 0.82
Data Access Request:
Data access request XDRQN is used to notify the Host that the Host should write data to the transmit
data buffer or read data from the receive data buffer in data write to the card or data read from the
card. The Data access request action also effective when Host interface type 2 is selected.
During data transmit to the card, the XDRQN will active if the data write command has been transfer
to the card and the transmit data buffer have not enough data to transmit to the card. The XDRQN will
not active if the transmit data buffer have enough data to transmit to the card. The last byte of the data
should placed at bit [15:8] if the data length is odd byte and CPU data size is 16-bit.
During data receive from the card, the XDRQN will active if the data read command has been transfer
to the card and the data have been received in the receive data buffer. The XDRQN will not active if
the data read command has been executed completedly and the receive data buffer is read out. The
last byte of the data is located at bit [7:0] if the data length is odd byte and CPU data size is 16-bit.
There are two types of data access request waveform, one is single access mode and the other is
burst access mode. Single access mode is configured if DABST = low, XDRQN will inactive after each
access receive or transmit data buffer, the XDRQN will re-active after four clock later. Figure 7-7
shows the waveform of Host access receive data buffer in single access mode (DABST = low). Burst
access mode is configured if DABST = high, XDRQN will hold at active state until the data has been
transferred completedly. The Host can access receive or transmit data buffer with higher speed
continuously and regardless of the system clock. Figure 7-8 is the waveform of Host access transmit
data buffer in burst mode (DABST = high).
Fig. 7-7 Host Read Receive Data Buffer in Single Access Mode (DABST = low).
A[3:1]
D[15:0]
XRDN
XCSN
XDRQN
System
Clock
010
010
Preliminary W86L488
Fig. 7-8 Host Write Transmit Data Buffer in Burst Access Mode (DABST = high).
A[3:1]
D[15:0]
XWRHN
XWRLN
XCSN
XDRQN
System_
Clock
010
010
010
Publication Release Date: February 5, 2004
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Revision 0.82
Interrupt:
The XINTN pin is used to notify Host that something happens or error occurs. The INT bit of status
register can be read and check repeatedly if the Host cannot accept XINTN pin. XINTN will active
(low) at the falling edge of system clock if any bit in the interrupt register is high, XINTN pin will return
to high when write high to the related bit of the interrupt status register except DRQ interrupt in, the
XINTN pin will go low again at four system clock cycles later if any other interrupt event is still
pending.
Fig. 7-9 Timing of Interrupt in.
XINTN
A[3:1]
D[15:0]
XCSN
XRDN
System_
Clock
011
XWRHN
0x80XX
011
1xxxxxxxb
Preliminary W86L488
A[3:1]
D[15:0]
XCSN
XRDN
System_
Clock
011
XWRHN
0x90XX
011
1xx0xxxxb
Publication Release Date: February 5, 2004
- 24 -
Revision 0.82
Fig. 7-10 Timing of Interrupt in (XINTN pin goes to low again).
XINTN
7.2 Card Inserting and Removing
There are two method for Host to detect SD/SDIO or MMC card inserting or removing through
W86L488, the first method is detected by CD/DAT3 pin, the second method is a dedicate switch on
the SD/MMC slot can be connected to the GIO0 pin and set GIO0 to input direction. These two
methods can be performed even if the W86L488 is in power down state.
Method 1, CD/DAT3 as card detection:
The CD/DAT3 of SD bus can be used as card detection if no data transfer on the DAT3, if SIEN bit of
the control register is low and CD_IE and INT_E on the interrupt enable register are all high, card
inserting or removing will generate interrupt. Host must read the interrupt status register and re-check
the card state by read the CD bit on the extend status register. This detection method will not effective
when wide bus on the SD bus is transfer. MMC card may not support this detection method.
Method 2, GIO0, GIP6 as card detection (inserting):
Some SD/MMC slot support external switch for card existing detection, the switch will on when
SD/SDIO or MMC card is exist. GIO0 and GIP6 with a pull high resister can be used as card detection
of port A and port B. In port A the Host can disable the GOEN0 bit on the general I/O port control
register and enable the GIT_EN0 bit on the general I/O port interrupt enable register and enable
GIT_IE and INT_E bits on the interrupt enable register. SD or MMC card inserting or removing will
change the switch state then change the state of GIO0 pin and then generate interrupt to the Host.
Host may re-check the card state by read the GIN0 bit on the general I/O port data register. The card
insert status of port A and port B also can be read in the global status and control register.
Figure 7-10 shows the waveform of GIO0 and GIOx when card insert and remove if GIO0 as card
insert and GIOx as write protect input.
Preliminary W86L488
GIO0
GIOx
(no WP)
GIOx
(WP)
Inserting
Card is exist
Removing
(GIN0 read 1)
(GINx read 1)
(GINx read 0)
Publication Release Date: February 5, 2004
- 25 -
Revision 0.82
Fig. 7-10 Card Insert use GIO0 and Write Protect use GIOx.
7.3 Reset Action
Hardware Reset:
Hardware reset is performed by setting RSTN pin to low state for at least 1uS. The CPU data size will
set to 16-bit default, all the registers will set to default value. The receive and transmit data buffer will
be cleared, all the internal logic will be reset to initial state.
Software Reset:
Software reset is executed by write the RST bit of the control register to 1, all the internal logic will be
reset to initial state and receive and transmit data buffer will be cleared, but the content of registers
are not affected. In W86L488AY, the port A and port B will reset at the same time if global software
reset in the global control register is set.
Data Buffer Reset:
Data buffer reset is used to reset the receive data buffer and transmit data buffer simutaneously, the
serial interface command will affected if the data receive or transmit command is progressing. Internal
logic state and the content of registers are not affected.
7.4 Clock Source
The clock source of W86L488 is the waveform of XTO pin, if crystal is connected, the frequency may
be from 3.58MHz to 25MHz, if the clock source is from external clock, XTI may be used as clock input
and the maximum frequency is 25MHz. In W86L488AY, the clock driver will disabled when port A and
port B are power down or global power down in the global control register is set.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 26 -
Revision 0.82
8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings*
PARAMETER SYMBOL
RATING
UNITS
1 Supply Voltage with respect to V
VSS
V
VDD
-0.3 to 6
V
2 Current at any pin other than supplies
0 to 10
mA
3 Storage Temperature
Tst
-65 to 150
C
* Exceeding these values may cause permanent damage.
8.2 Recommended Operating Conditions
CHARACTERISTICS SYMBOL
RATING
UNIT
1 Host I/F Operation Voltage (referenced to V
SS
pin).
V
VDDH
2.5 to 3.6
V
2 Operation Voltage (referenced to V
SS
pin).
V
VDD3
3.0 to 3.6
V
3 Operation Voltage (referenced to V
SS
pin) (Note)
V
VDD3
2.7to
3.0 V
4 Clock Frequency at XTI pin
fXTL 25 MHz
5 Operation Temperature
Top
0 to 70
C
Note: Clock frequency not guaranteed up to 25 MHz.
8.3 Power Supply Characteristics
(Measurement VDD3+ VDDH at VDD3 = VDDH)
PARAMETER CONDITION
SYM. MIN TYP
MAX UNITS TEST
1 Standby Supply Current
Power Supply
IQ 2 20 A Test 1
2 Operating Supply Current (Single port)
(V
VDD
= 3.3V) IVDD
14 22 mA
Test
2
3 Operating Supply Current (Dual port)
IVDD
24 36 mA
Test
2
4 Operating Supply Current (Single port)
(V
VDD
= 3.3V) IVDD
13 mA
Test
3
5 Operating Supply Current (Dual port)
IVDD
23 mA
Test
3
: Typical figure are at V
DIVDD
= 3.3V and temperature = 25
C and are for design aid only, not
guaranteed and not subject to production testing.
Test 1: All input pins are V
VDD
or V
VSS
, configured as power down mode, output without
loading and no clock input on the XTI and HCKI pins.
Test 2: 25 MHz external clock input on the XTI pin, output without loading.
Test 3: 25 MHz crystal connected at XTI and XTO pins, output without loading.
Preliminary W86L488
Publication Release Date: February 5, 2004
- 27 -
Revision 0.82
8.4 Digital Characteristics
PARAMETER CONDITION
SYMBOL
MIN.
TYP
MAX. UNITS NOTES
1 Output High Voltage
2mA load
V
OH
0.9 V
DD
1
2 Output Low Voltage
2mA sink
V
OL
0.1
V
DD
1
3
Output High Voltage at SD4
output
3mA load
V
OH
0.9
V
DD
4
Output Low Voltage at SD4
output
3mA sink
V
OL
0.1
V
DD
5 High Level Input Voltage
V
IH
0.7 V
DD
6 Low Level Input Voltage
V
IL
0.3
V
DD
7
Input
Current
Iin 1
A
8 Input
Capacitance
Cin
10
pF
: Typical figure are at V
DVDD
= 3.3V and temperature = 25
C and are for design aid only, not
guaranteed and not subject to production testing.
Notes:
1: All output pins except SD4 output.
8.5 Timing Characteristics
PARAMETER SYMBOL
MIN.
TYP.
MAX.
UNITS
NOTES
Clock (figure 8-1)
1 XTI
fXTI
1
-
20
MHz
1
2 XTI high pulse width
tXTI
wh
10 - - nS 1
3 XTI low pulse width
tXTI
wl
10 - - nS 1
4 XTI rise time
tXTI
r
- - 5 nS 1
5 XTI fall time
tXTI
f
- - 5 nS 1
6 XTO delay time
tXTO
d
- - 5 nS 2
7 XTI crystal driver
fXTI
3.58
-
25
MHz
3
8 HCLK
frequency
fHCLK
1
-
40
MHz
9 HCLK high pulse width
tHCLK
wh
10 -
-
nS
10 HCLK low pulse width
tHCLK
wl
10 -
-
nS
11 HCLK rise time
tHCLK
I
- - 5 nS
12 HCLK fall time
tHCLK
f
- - 5 nS
Preliminary W86L488
Publication Release Date: February 5, 2004
- 28 -
Revision 0.82
8.5. Timing Characteristics, continued
PARAMETER SYMBOL
MIN.
TYP.
MAX.
UNITS
NOTES
Reset
1 RSTN
tRST
4
-
- cycle
Host Interface at Type 1 (figure 8-2, 8-3)
1 Access
time
t
acc
70 - - nS 4
2
Address setup time
tA
su
10 - - nS
3
Address hold time
tA
h
5 - - nS
4
D[15:0] output delay time
tD
od
- - 30 nS 5,6
5
D[15:0] output hold time
tD
oh
10 - - nS 5,7
6
D[15:0] input setup time
tD
su
10 - - nS 8
7
D[15:0] input hold time
tD
h
5 - - nS 9
8
DMA request delay time
tDRQ
d
- - 20 nS 2
9
DMA request hold time
tDRQ
h
5 - 20 nS 2
Host Interface at Type 2 (figure 8-5)
1
Input signals setup time
tIF2
su
10 - - nS 10
2
Input signals hold time
tIF2
h
5 - - nS 10
3
Address setup time
tA2
su
10 - - nS
4
Address hold time
tA2
h
5 - - nS
5
XRDYN delay time
tRDY
d
- - 20 nS 2
6
XRDYN hold time
tRDY
h
5 - - nS 2
7
D[15:0] output delay time
tD
od
- - 30 nS 5
8
D[15:0] output hold time
tD
oh
10 - - nS 5
9
D[15:0] input setup time
tD
su
10 - - nS
10 D[15:0] input hold time
tD
h
5 - - nS
Interrupt (figure 8-4)
1
Interrupt delay time
tINT
d
- - 20 nS
2
Interrupt hold time
TINT
h
5 - 20 nS
Preliminary W86L488
Publication Release Date: February 5, 2004
- 29 -
Revision 0.82
8.5. Timing Characteristics, continued
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Serial Interface Signals (figure 8-6, 8-7, 8-8, 8-9)
1 SD3 output delay
tSD3
d
5 - 15 nS 2
2 SD3 input setup time
tSD3D
su
10 -
-
nS
3 SD3 input hold time
tSD3
h
5 - - nS
4 SD1, SD2, SD5, SD6 output delay time
tSDn
d
*
- - 30 nS 2
5 SD1, SD2, SD5, SD6 input setup time
tSDn
su
10 - - nS
6 SD1, SD2, SD5, SD6 input hold time
tSDn
h
5 - - nS
Note 1: External clock input.
Note 2: 20 pF output loading.
Note 3: Crystal driver.
Note 4: Minimum active pulse width of (XCSN and XRDN) or (XCSN and XWRHN and XWRLN).
Note 5: 40 pF output loading.
Note 6: From the last active signal of XCSN or XRDN.
Note 7: From the first in-active signal of XCSN or XRDN.
Note 8: To the first in-active signal of XCSN, XWRHN or XWRLN, XWRHN or XWRLN related to the
D[15:8] or D[7:0].
Note 9: From the first in-active signal of XCSN, XWRHN or XWRLN, XWRHN or XWRLN related to
the D[15:8] or D[7:0].
Note 10: XCSN, XASN, XRWN and XBE[1:0] signals.
Fig. 8-1 Timing Characteristic of XTI, XTO and HCKI.
HCKI
XTI
XTO
tXTO
d
tXTI
wh
tXTI
wl
tXTI
f
tXTI
r
tHCKI
wh
wl
tHCKI
tHCKI
f
tHCKI
r
Preliminary W86L488
Fig. 8-2 Host Access Timing Characteristic in Host I/F Type 1.
XWRLN
A[3:1]
D[15:0]
XRDN
XCSN
XWRHN
DO[15:0]
DI[15:0]
tD
od
tD
oh
tA
su
tA
h
t
acc
Publication Release Date: February 5, 2004
- 30 -
Revision 0.82
tD
su
tD
h
t
acc
Fig. 8-3 Data Access Request Timing Characteristic.
XTO
XDRQN
Data_Acc
(Note 1)
tDRQ
d
tDRQ
h
Note 1: May be XRDN or XWRHN or XWRLN signals when DABST = low.
Preliminary W86L488
XTO
XINTN
XRDN
tINT
d
Publication Release Date: February 5, 2004
- 31 -
Revision 0.82
Fig. 8-4 Interrupt Timing Characteristic.
HCKI
XCSN,XASN,
XRWN,XBE[1:0]
XRDYN
A[3:1]
tIF2
su
tIF2
h
tRDY
d
DI
DO
tA2
su
tA2
h
tRDY
h
tD
su
tD
h
tD
od
tD
oh
tINT
h
Fig. 8-5 Host Interface Type 2 Timing Characte
Fig. 8-6 Serial Interface CMD Timing Characteristic (SD Mode).
CLK
CMD
(output)
CMD
(input)
tCMD
d
tCMD
d
tCMD
d
tCMD
su
tCMD
h
ristic.
Preliminary W86L488
CLK
DAT[3:0]
(output)
tDAT
h
tDAT
d
DAT[3:0]
(input)
tDAT
d
tDAT
su
Publication Release Date: February 5, 2004
- 32 -
Revision 0.82
Fig. 8-7 Serial Interface DAT[3:0] Timing Characteristic (S
CLK
CMD
(output)
CMD
(input)
tCMD
d
tCMD
d
tCMD
d
tCMD
su
tCMD
h
tCMD
su
tCMD
h
D Mode).
Fig. 8-8 Serial Interface CMD Timing Characteristic (MM
Fig. 8-9 Serial Interface DAT[3:0] Timing Characteristic (MMC Mode).
CLK
DAT[3:0]
(output)
tDAT
h
tDAT
d
DAT[3:0]
(input)
tDAT
d
tDAT
su
C Mode).
Preliminary W86L488
Publication Release Date: February 5, 2004
- 33 -
Revision 0.82
9. HOW TO READ THE TOP MARKING
The top marking of W86L488Y
W86L488Y
312AA01CSA
S
MART@
IO
1st line: Winbond logo and SMART@IO Mark
2nd line: Part number of W86L488Y
3rd line: Tracking code
220 A A 01A SA
312: packages made in '03, week 12
A: assembly house ID; A means ASE, O means OSE, G means GR
A: IC revision; A means version A, B means version B
01C: for internal use
SA: for internal use
Preliminary W86L488
Publication Release Date: February 5, 2004
- 34 -
Revision 0.82
10. PACKAGE DIMENSIONS
10.1 W86L488Y Package Dimensions
48- QFN 7x7 MM^2, Thickness: 1.0MM
b
4X
Controlling Dimension :Millimeters
*D2,*E2 :By die size difference
Preliminary W86L488
Publication Release Date: February 5, 2004
- 35 -
Revision 0.82
10.2 W86L488AY Package Dimensions
64- QFN 9x9 MM^2, Thickness: 1.0MM
4X0
Preliminary W86L488
Publication Release Date: February 5, 2004
- 36 -
Revision 0.82
11. REFERENCE SCHEMATIC
11.1 W86L488Y Reference Schematic
R65
0
U2
W86L488D/48P_LQFP
19
20
21
17
43
31
18
6
10
9
8
7
3
5
4
2
1
48
47
46
45
44
41
40
38
37
36
22
15
16
26
25
24
27
12
13
14
28
39
11
35
32
34
33
29
30
VDD
CLK
DAT0
CMD
VDD
VSS
VSS
D0
D1
D2
D3
D6
D4
D5
D7
D8
D9
D10
D11
D12
D13
D14
D15/A0
A1
A2
A3
DAT1
DAT2
CD/DAT3
GIO1
GIO2
GIO0
RSTN
XTI
XTO
HCKI
XTYP2
XINTN
XCSN
XRDN/XRDWRN
XWRLN/XBELN
XWRHN/XBEHN
XDRQN/XRDY
XDAKN/XAS
C10
0.1u
VCC3
C11
0.1u
VCC3
D
D0
WP
D8
RSTN
D13
GIO1
HCKI
D1
D15
DAT2
D4
A3
GIO2
D6
CMD
D
XINTN
D
D3
NOE
INS
DAT1
CLK
NCS5
A2
XTI
NWE
D2
D7
D14
D10
DAT3
GIO3
D9
D12
D5
D
XDAKN
D11
XTO
DAT0
A1
XDRQN
R62
open
R63
0
42
VSS
VSS
GIO4
GIO3
23
Preliminary W86L488
R21
open
VCC3
R18
47K
1 2 3 4
5
6
7
8
R17
47K
1 2 3 4
5
6
7
8
R27
22
1
2
3
4
5
6
7
8
Publication Release Date: February 5, 2004
- 37 -
Revision 0.82
D
D
DAT3
DAT2
CMD
WP
DAT1
CLK
DAT0
D
D
INS
XDAKN
HCKI
GIO3
GIO1
GIO2
XTI
XTO
D
D
R15
47K
C7
0.1u
CON1
SD/MMC Card Scoket
1
2
3
7
8
9
4
5
6
10
11
12
CD/DAT3
CMD
VSS
DAT0
DAT1
DAT2
VDD
CLK
VSS
INS
WP
CASE
C8
10u
R28
22
1
2
3
4
5
6
7
8
C13
30p
Q1
20MHz
C14
30p
R55
0
VCC3
R1
47K
R2
47K
R4
47K
R3
47K
R5
47K
Preliminary W86L488
C4
22u
C2
C1
C4
C6
C8
C10
C12
C14
C16
C18
C20
C22
C24
C26
C28
C3
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
J1
C27
AMP 536280-6
2
4
C2
6
8
10
C4
12
14
16
18
20
22
24
C6
26
28
30
C8
32
34
36
38
40
42
44
C10
46
48
50
C12
52
54
56
58
60
62
64
C14
66
68
70
C16
72
74
76
78
80
82
84
C18
86
88
90
C20
94
96
98
100
102
104
C22
106
108
110
C24
112
114
116
118
120
122
124
C26
126
128
92
C6
0.1u
VCC3
C5
1u
Publication Release Date: February 5, 2004
- 38 -
Revision 0.82
XINTN
D
A5
D
A1
D0
PXA255_XINT
D14
D5
A4
NOE
D
A3
D13
D
NWE
D9
D6
D4
D10
D15
NCS5
D7
D11
D8
D
D3
D1
A0
RSTN
A2
D12
D2
1
130
C28
3
C1
5
7
9
C3
11
13
15
17
19
21
23
C5
25
27
29
C7
31
33
35
37
39
41
43
C9
45
47
49
C11
51
53
55
57
59
61
63
C13
65
67
69
C15
71
73
75
77
79
81
83
C17
85
87
89
C19
91
93
95
97
99
101
103
C21
105
107
109
C23
111
113
115
117
119
121
123
C25
125
127
129
C27
131
132
134
136
138
140
133
135
137
139
VCC3
Preliminary W86L488
W86L488D/64P_LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
D8
D7
D6
D5
D4
BGIO10
BGIO11
VSS
D3
D2
D1
D0
XINTN
RSTN
NC
XTI
XTO BD
AT2
BD
AT3/BC
S
B
C
MD/B
CDI
AD
AT2
AD
AT3/AC
S
A
C
MD/A
CDI
VSS V
DD3
AC
LK
AD
AT0/AC
D
O
AD
AT1/AIR
Q
BC
LK
BD
AT0/BC
D
O
BD
AT1/BIR
Q
AGIO4
AGIO3
AGIO2
AGIO1
AGIO0/CI_A
BGIO6/CI_B
HCKI
XDRQN/XRDYN
XDAKN/XASN
VSS
XRDN/XRWN
XWRHN/XBE0
XWRLN/XBE1
XCSN
AGIO5
A4
A3
A2
A1
BGIO7
XTYP2
BGIO8
D
15/A0
D1
4
VSS
TEST
V
DDH
BGIO9
D1
3
D1
2
D1
1
D1
0
D9
C3
0.1u
R14
0
R13
open
VCC3
VCC3
VCC3
Publication Release Date: February 5, 2004
- 39 -
Revision 0.82
11.2 W86L488AY Reference Schematic
GIO9
GIO2
A4
D
ADAT2
D2
D6
ADAT1
BDAT2
GIO3
ADAT0
D
GIO8
BCLK
D9
D1
D8
GIO7
AINS
D14
ACMD
XTO
NOE
D
XDAKN
BCMD
BWP
GIO11
D10
D
NWE
BDAT0
XTI
ADAT3
D12
A1
D
NCS5
D5
A3
GIO1
D4
RSTN
XDRQN
NWEH
D7
D15
D
AWP
D13
D
HCKI
D3
BDAT1
ACLK
D0
XINTN
BDAT3
GIO5
D11
BINS
A2
R24
0
C9
0.1u
Preliminary W86L488
R9
47K
R10
47K
JP1
1
Publication Release Date: February 5, 2004
- 40 -
Revision 0.82
HEADER 2
R6
47K
R7
47K
R8
47K
R3
47K
GIO11
GIO7
GIO2
GIO9
GIO5
GIO8
GIO3
HCKI
XDAKN
GIO1
RSTN
D
AWP
D
ACMD
ADAT3
AINS
ACLK
D
D
ADAT0
D
ADAT2
ADAT1
D
XTI
D
XTO
BCMD
BWP
BCLK
BDAT3
D
D
BINS
BDAT0
BDAT2
BDAT1
D
D
VCC3
2
R57
47k
SW1
1
2
VCC3
C15
1u
D1
1N4148
R4
47K
R1
47K
R2
47K
R5
47K
3
4
5
R47
47K
1 2 3 4
5
6
7
8
R45
47K
VCC3
R46
47K
1 2 3 4
5
6
7
8
R48
open
R49
22
1
2
3
4
5
6
7
8
CON1
SD/MMC Card Scoket_A
1
2
3
7
8
9
4
5
6
10
11
12
CD/DAT3
CMD
VSS
DAT0
DAT1
DAT2
VDD
CLK
VSS
INS
WP
CASE
R15
47K
VCC3
C8
10u
R28
22
1
2
6
7
8
R18
47K
1 2 3 4
5
6
7
8
R21
open
C7
0.1u
R17
47K
1 2 3 4
5
6
7
8
R27
22
1
2
3
4
5
6
7
8
C14
30p
Q1
20MHz
C13
30p
CON2
SD/MMC Card Scoket_B
1
2
3
7
8
9
4
5
6
10
11
12
CD/DAT3
CMD
VSS
DAT0
DAT1
DAT2
VDD
CLK
VSS
INS
WP
CASE
C11
10u
R54
22
1
2
3
4
5
6
7
8
C10
0.1u
Preliminary W86L488
C2
C1
C4
C6
C8
C10
C12
C14
C16
C18
C20
C22
C24
C26
C28
C3
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
J1
C27
AMP 536280-6
2
1
4
C2
6
8
10
C4
12
14
16
18
20
22
24
C6
26
28
30
C8
32
34
36
38
40
42
44
C10
46
48
50
C12
52
54
56
58
60
62
64
C14
66
68
70
C16
72
74
76
78
80
82
84
C18
86
88
90
C20
94
96
98
100
102
104
C22
106
108
110
C24
112
114
116
118
120
122
124
C26
126
128
92
VCC3
C4
22u
C5
1u
C6
0.1u
Publication Release Date: February 5, 2004
- 41 -
Revision 0.82
VCC3
D
XINTN
NCS5
D
D10
D12
D
D1
D8
D2
A5
D
D3
A4
D4
A1
A2
D
D7
D15
A0
A3
D5
D0
D14
D11
NOE
PXA255_XINT
D9
RSTN
D13
NWE
D6
130
C28
3
C1
5
7
9
C3
11
13
15
17
19
21
23
C5
25
27
29
C7
31
33
35
37
39
41
43
C9
45
47
49
C11
51
53
55
57
59
61
63
C13
65
67
69
C15
71
73
75
77
79
81
83
C17
85
87
89
C19
91
93
95
97
99
101
103
C21
105
107
109
C23
111
113
115
117
119
121
123
C25
125
127
129
C27
131
132
134
136
138
140
133
135
137
139
Preliminary W86L488
Publication Release Date: February 5, 2004
- 42 -
Revision 0.82
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
TEL: 81-45-4781881
Neihu District, Taipei, 114,
Taiwan, R.O.C.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
9F, No.480, Rueiguang Rd.,
Please note that all data and specifications are subject to change without notice. All the trademarks of products and
companies mentioned in this data sheet belong to their respective owners.
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