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Электронный компонент: W9816G6BB-7

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W9816G6BB
512K
2 BANKS 16 BITS SDRAM
Publication Release Date: January 2, 2003
- 1 -
Revision A1
Table of Contens-
1. GENERAL DESCRIPTION.................................................................................................................. 3
2. FEATURES ......................................................................................................................................... 3
3. PART NUMBER INFORMATION........................................................................................................ 3
4. BALL CONFIGURATION .................................................................................................................... 4
5. BALL DESCRIPTION .......................................................................................................................... 5
6. BLOCK DIAGRAM .............................................................................................................................. 6
7. FUNCTIONAL DESCRIPTION............................................................................................................ 7
Power Up and Initialization................................................................................................................ 7
Programming Mode Register ............................................................................................................ 7
Bank Activate Command................................................................................................................... 7
Read and Write Access Modes......................................................................................................... 7
Burst Read Command....................................................................................................................... 8
Burst Write Command....................................................................................................................... 8
Read Interrupted by a Read.............................................................................................................. 8
Read Interrupted by a Write .............................................................................................................. 8
Write Interrupted by a Write .............................................................................................................. 8
Write Interrupted by a Read .............................................................................................................. 8
Burst Stop Command........................................................................................................................ 8
Addressing Sequence of Sequential Mode....................................................................................... 9
Addressing Sequence of Interleave Mode ........................................................................................ 9
Auto Precharge Command.............................................................................................................. 10
Precharge Command ...................................................................................................................... 10
Self Refresh Command................................................................................................................... 10
Power Down Mode.......................................................................................................................... 10
No Operation Command ................................................................................................................. 11
Deselect Command......................................................................................................................... 11
Clock Suspend Mode ...................................................................................................................... 11
Table of Operating Modes............................................................................................................... 12
8. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 13
9. RECOMMENDED DC OPERATING CONDITIONS ......................................................................... 13
10. CAPACITANCE............................................................................................................................... 13
W9816G6BB
- 2 -
11. DC CHARACTERISTICS ................................................................................................................ 14
12. AC CHARACTERISTICS ................................................................................................................ 15
13. TIMING WAVEFORMS ................................................................................................................... 17
Command Input Timing................................................................................................................... 17
Read Timing .................................................................................................................................... 18
Control Timing of Input/Output Data ............................................................................................... 19
Mode Reqister Set Cycle ................................................................................................................ 20
Interleaved Bank Read.................................................................................................................... 21
Interleaved Bank Read.................................................................................................................... 22
Interleaved Bank Read.................................................................................................................... 23
Interleaved Bank Read.................................................................................................................... 24
Interleaved Bank Write.................................................................................................................... 25
Interleaved Bank Write.................................................................................................................... 26
Page Mode Read ............................................................................................................................ 27
Page Mode Read/Write................................................................................................................... 28
Auto Precharge Read...................................................................................................................... 29
Auto Precharge Write...................................................................................................................... 30
Auto Refresh Cycle ......................................................................................................................... 31
Self Refresh Cycle........................................................................................................................... 32
Bust Read and Single Write ............................................................................................................ 33
Power Down Mode.......................................................................................................................... 34
Auto Precharge Timing ................................................................................................................... 35
Auto Precharge Timing ................................................................................................................... 36
Timing Chart of Write-to-Read Cycle .............................................................................................. 37
Timing Chart of Burst Stop Cycle.................................................................................................... 37
Timing Chart of Burst Stop Cycle (Prechare Command)................................................................ 38
CKE/DQM Input Timing................................................................................................................... 39
CKE/DQM Input Timing................................................................................................................... 40
Self Refresh/ Power Down Mode Exit Timing ................................................................................. 41
14. PACKAGE DIMENSIONS ............................................................................................................... 42
BGA 60 Balls Pitch = 0.65 mm........................................................................................................ 42
W9816G6BB
Publication Release Date: January 2, 2003
- 3 -
Revision A1
1. GENERAL DESCRIPTION
W9816G6BB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words x 2 banks x 16 bits. Using pipelined architecture and 0.175
m process technology,
W9816G6BB delivers a data bandwidth of up to 286M bytes per second (-7).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9816G6BB is ideal for main memory in
high performance applications.
2. FEATURES
2.7V
- 3.6V power supply
Up to 200 MHz clock frequency
524,288 words x 2 banks x 16 bits organization
Self Refresh Current: standard and low power
CAS latency: 2 and 3
Burst length: 1, 2, 4, 8, and full page
Burst read, single write mode
Byte data controlled by UDQM and LDQM
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Package: BGA 60 balls pitch = 0.65 mm using
PB free materials

3. PART NUMBER INFORMATION
PART NUMBER
SPEED (CL = 3)
SELF REFRESH CURRENT(MAX.)
W9816G6BB-7
143 MHz
1 mA
W9816G6BB
- 4 -
4. BALL CONFIGURATION
Bottom View
7 6
2 1
C
B
A
P
N
G
D
E
M
H
L
F
K
R
J
Vss
Vss
DQ14
DQ13
DQ12
DQ10
DQ8
NC
NC
NC
CKE
BA
A8
A6
DQ9
DQ15
A4
VssQ
VDDQ
DQ11
VssQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
VDDQ
VDD
VDD
DQ1
DQ2
DQ3
DQ5
DQ7
NC
WE#
CAS#
CS#
NC
A10
A1
DQ6
DQ0
A3
VDDQ
VssQ
DQ4
VDDQ
NC
NC
LDQM
RAS#
NC
NC
A0
A2
VssQ
Top View
7
6
2
1
C
B
A
P
N
G
D
E
M
H
L
F
K
R
J
Vss
Vss
DQ14
DQ13
DQ12
DQ10
DQ8
NC
NC
NC
CKE
BA
A8
A6
DQ9
DQ15
A4
VssQ
VDDQ
DQ11
VssQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
VDDQ
VDD
VDD
DQ1
DQ2
DQ3
DQ5
DQ7
NC
WE#
CAS#
CS#
NC
A10
A1
DQ6
DQ0
A3
VDDQ
VssQ
DQ4
VDDQ
NC
NC
LDQM
RAS#
NC
NC
A0
A2
VssQ
W9816G6BB
Publication Release Date: January 2, 2003
- 5 -
Revision A1
5. BALL DESCRIPTION
BALL-LOCATION
BALL
NAME
FUNCTION DESCRIPTION
N6, P7, P6, R6,
R2, P2, P1, N2,
N1, M2, N7
A0
- A10
Address
Multiplexed pins for row and column address.
Row address: A0
- A10. Column address: A0 - A7.
M1 BA
Bank
Address
Select bank to activate during row address latch
time, or bank to read/write during column address
latch time.
A6, B7, C7, D7, D6,
E7, F7, G7, G1, F1,
E1, D2, D1, C1, B1,
A2,
DQ0
-
DQ15
Data Input/
Output
Multiplexed pins for data input and output.
L7
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
K6
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of
the clock,
RAS
,
CAS
and
WE
define the
operation to be executed.
K7
CAS
Column
Address
Strobe
Referred to
RAS
J7
WE
Write Enable Referred to
RAS
J2/J6
UDQM/
LDQM
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
K2 CLK
Clock
Inputs
System clock used to sample inputs on the rising
edge of clock.
L1 CKE
Clock
Enable
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
A7, R7
V
DD
Power
(+3.3V)
Power for input buffers and logic circuit inside
DRAM.
A1, R1
V
SS
Ground
Ground for input buffers and logic circuit inside
DRAM.
B6, C2, E6, F2
V
DDQ
Power
(+3.3V) for
I/O buffer
Separated power from V
DD
, used for output buffers
to improve noise immunity.
B2, C6, E2, F6
V
SSQ
Ground for
I/O buffer
Separated ground from V
SS
, used for output buffers
to improve noise immunity.
G2, G6, H1, H2, H6,
H7, J1, K1, L2, L6,
M6, M7
NC
No
Connection
No connection
W9816G6BB
- 6 -
6. BLOCK DIAGRAM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
R
O
W
D
E
C
O
D
E
R
DQ0
DQ15
LDQM
UDQM
DQ
BUFFER
CS
RAS
CAS
WE
DATA CONTROL
CIRCUIT
Note: The cell array configuration is 2048 * 256 * 16
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
A0
A9
BA
R
O
W
D
E
C
O
D
E
R
W9816G6BB
Publication Release Date: January 2, 2003
- 7 -
Revision A1
7. FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs during power up, all V
DD
and V
DDQ
pins must be ramp up simultaneously to the
specified voltage when the input signals are held in the "NOP" state. The power up voltage must not
exceed V
DD
+0.3V on any of the input pins or V
DD
supplies. After power up, an initial pause of 200
S
is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles
(CBR) are also required before or after programming the Mode Register to ensure proper subsequent
operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of
RAS
,
CAS
,
CS
and
WE
at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to t
RSC
has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to
RAS
activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
RCD
). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t
RC
).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank-to-Bank delay time (t
RRD
). The maximum time that each bank can be held active is
specified as t
RAS
(max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS
high and
CAS
low at the clock rising edge after minimum of t
RCD
delay.
WE
pin voltage level
defines whether the access cycle is a read operation (
WE
high), or a write operation (
WE
low). The
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.
W9816G6BB
- 8 -
Burst Read Command
The Burst Read command is initiated by applying logic low level to
CS
and
CAS
while holding
RAS
and
WE
high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
Burst Write Command
The Burst Write command is initiated by applying logic low level to
CS
,
CAS
and
WE
while
holding
RAS
high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having
RAS
and
CAS
high with
CS
and
WE
low at the rising edge of
W9816G6BB
Publication Release Date: January 2, 2003
- 9 -
Revision A1
the clock. The data DQs go to a high impedance state after a delay, which is equal to the
CAS
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
Data
Access Address
Burst Length
Data 0
n
BL = 2 (disturb address is A0)
Data 1
n + 1
No address carry from A0 to A1
Data 2
n + 2
BL = 4 (disturb addresses are A0 and A1)
Data 3
n + 3
No address carry from A1 to A2
Data 4
n + 4
Data 5
n + 5
BL = 8 (disturb addresses are A0, A1 and A2)
Data 6
n + 6
No address carry from A2 to A3
Data 7
n + 7
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
Data
Access Address
Bust Length
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1
A0
Data 2
A8 A7 A6 A5 A4 A3 A2
A1
A0
BL = 4
Data 3
A8 A7 A6 A5 A4 A3 A2
A1
A0
Data 4
A8 A7 A6 A5 A4 A3
A2
A1 A0
BL = 8
Data 5
A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 6
A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 7
A8 A7 A6 A5 A4 A3
A2
A1
A0
W9816G6BB
- 10 -
Auto Precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by
CAS
latency.
A Read or Write Command with auto precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (t
RP
) has been satisfied. Issue of Auto-Precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto Precharge function is initiated. The SDRAM automatically enters the precharge operation
one clock delay from the last burst write cycle. This delay is referred to as Write t
WR
. The bank
undergoing auto precharge can not be reactivated until t
WR
and t
RP
are satisfied. This is referred to as
t
DAL
, Data-in to Active delay (t
DAL
= t
WR
+ t
RP
). When using the Auto Precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy t
RAS
(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when
CS
,
RAS
and
WE
are low and
CAS
is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. The address bits, A10, and BA, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(t
RP
).
Self Refresh Command
The Self Refresh Command is defined by having
CS
,
RAS
,
CAS
and CKE held low with
WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued
after t
RC
from the end of Self Refresh command.
If, during normal operation, Auto Refresh cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 Auto Refresh cycles should be completed just prior to entering and just
after exiting the Self-Refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations;
therefore the device can not remain in Power Down mode longer than the Refresh period (t
REF
) of the
device.
W9816G6BB
Publication Release Date: January 2, 2003
- 11 -
Revision A1
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on t
CK
. The input buffers need to be
enabled with CKE held high for a period equal to t
CKS
(min) + t
CK
(min).
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when
CS
is low with
RAS
,
CAS
, and
WE
held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when
CS
is brought high, the
RAS
,
CAS
, and
WE
signals become don't
cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one-clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
W9816G6BB
- 12 -
Table of Operating Modes
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (NOTE 1, 2)
COMMAND
DEVICE
STATE
CKEN-1 CKEN DQM
BA A10 A9-0
CS
RAS CAS
WE
Bank Active
Idle H X
X
V
V
V
L
L
H
H
Bank Precharge
Any H X
X
V
L
X
L
L
H
L
Precharge All
Any H X
X
X
H
X
L
L
H
L
Write
Active (3)
H
X
X
V
L
V
L
H
L
L
Write with Auto
Precharge
Active (3)
H
X
X
V
H
V
L
H
L
L
Read
Active (3)
H
X
X
V
L
V
L
H
L
H
Read with Auto
Precharge
Active (3)
H
X
X
V
H
V
L
H
L
H
Mode Register Set
Idle H X
X
V
V
V
L
L
L
L
No-Operation
Any H X
X
X
X
X
L
H
H
H
Burst Stop
Active (4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any H X
X
X
X
X
H
X
X
X
Auto Refresh
Idle H H
X
X
X
X
L
L
L
H
Self Refresh Entry
Idle H L
X
X
X
X
L
L
L
H
Self Refresh Exit
Idle
(S.R)
L
L
H
H
X
X
X
X
X
X
X
X
H
L
X
H
X
H
X
X
Clock Suspend Mode
Entry
Active H L X
X
X
X
X
X
X
X
Power Down Mode
Entry
Idle
Active (5)
H
H
L
L
X
X
X
X
X
X
X
X
H
L
X
H
X
H
X
X
Clock Suspend Mode
Exit
Active L H
X
X
X
X
X
X
X
X
Power Down Mode Exit
Any
(Power
down)
L
L
H
H
X
X
X
X
X
X
X
X
H
L
X
H
X
H
X
X
Data Write/Output
Enable
Active H X L
X
X
X
X
X
X
X
Data Write/Output
Disable
Active H X H
X
X
X
X
X
X
X
Notes:
(1) V = Valid, X = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input level when commands are provided.
(3) These are state of bank designated by BA signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
W9816G6BB
Publication Release Date: January 2, 2003
- 13 -
Revision A1
8. ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL
RATING
UNIT
NOTES
Input, Output Voltage
V
IN
, V
OUT
-0.3
- 4.6
V 1
Power Supply Voltage
V
DD
, V
DDQ
-0.3
- 4.6
V 1
Operating Temperature
T
OPR
0
- 70
C 1
Storage Temperature
T
STG
-55
- 150
C 1
Soldering Temperature (10s)
T
SOLDER
260 C 1
Power Dissipation
P
D
1
W
1
Short Circuit Output Current
I
OUT
50
mA
1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
9. RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to 70C)
PARAMETER SYM.
MIN.
TYP.
MAX.
UNIT
NOTES
Power Supply Voltage
V
DD
2.7 3.3 3.6 V 2
Power Supply Voltage (for I/O Buffer)
V
DDQ
2.7 3.3 3.6
V
2
Input High Voltage
V
IH
2.0 -
V
DD
+0.3
V
2
Input Low Voltage
V
IL
-0.3 - 0.8 V 2
Note
:
V
IH
(max.) = V
DD
/V
DDQ
+1.2V for pulse width < 5 nS
V
IL
(min.) = V
SS
/V
SSQ
-1.2V for pulse width < 5 nS
10. CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
C, f = 1MHz)
PARAMETER SYM.
MIN.
MAX.
UNIT
Input Capacitance (A0 to A10, BA,
CS
,
RAS
,
CAS
,
WE
, UDQM, LDQM, CKE)
C
I
- 4
pf
Input Capacitance (CLK)
-
4
pf
Input/Output Capacitance (DQ0 to DQ15)
C
IO
- 6.5
pf
Note: These parameters are periodically sampled and not 100% tested
W9816G6BB
- 14 -
11. DC CHARACTERISTICS
(V
DD
= 2.7
- 3.6V, T
A
= 0
- 70C)
PARAMETER SYMBOL
-7
MAX.
UNIT NOTES
Operating Current
t
CK
= min., t
RC
= min.
Active precharge command cycling
without burst operation
1 bank operation
I
CC1
50 3
CKE = V
IH
I
CC2
25 3
Standby Current
t
CK
= min., CS
= V
IH
V
IH
/L = V
IH
(min.) /V
IL
(max.)
Bank: inactive state
CKE = V
IL
(Power down mode)
I
CC2P
1 3
CKE = V
IH
I
CC2S
8
Standby Current
CLK = V
IL
, CS
= V
IH
V
IH
/L = V
IH
(min.) /V
IL
(max.)
Bank: inactive state
CKE = V
IL
(Power down mode)
I
CC2PS
1 mA
CKE = V
IH
I
CC3
35
No Operating Current
t
CK
= min., CS
= V
IH
(min.)
Bank: active state (2 banks)
CKE = V
IL
(Power Down mode)
I
CC3P
3
Burst Operating Current (t
CK
= min.)
Read/ Write command cycling
I
CC4
100 3,
4
Auto Refresh Current (t
CK
= min.)
Auto refresh command cycling
I
CC5
50 3
Standard
I
CC6
1.5
Self Refresh Current
(CKE = 0.2V)
Self refresh mode
Low Power
I
CC6L
200
A
PARAMETER SYMBOL
MIN.
MAX.
UNIT
NOTES
Input Leakage Current
(0V
V
IN
V
DD
, all other pins not under test = 0V)
I
I(L)
-5 5
A
Output Leakage Current
(Output disable , 0V
V
OUT
V
DDQ
)
I
O(L)
-5 5
A
LVTTL OutputT
H
Level Voltage
(I
OUT
= -2 mA)
V
OH
2.4 - V
LVTTL Output
L
Level Voltage
(I
OUT
= 2 mA)
V
OL
- 0.4 V
W9816G6BB
Publication Release Date: January 2, 2003
- 15 -
Revision A1
12. AC CHARACTERISTICS
(V
DD
= 3.3V
0.3V, V
SS
= 0V, T
A
= 0 to 70
C, Notes: 5, 6, 7, 8)
-7
PARAMETER SYM.
MIN. MAX.
UNIT
Ref/Active to Ref/Active Command Period
t
RC
65
nS
Active to Precharge Command Period
t
RAS
45 100000
Active to Read/Write Command Delay Time
t
RCD
20
Read/Write(a) to Read/Write(b)Command Period
t
CCD
1
Cycle
Precharge to Active(b) Command Period
t
RP
20
nS
Active(a) to Active(b) Command Period
t
RPD
14
CL* = 2
10
Write Recovery Time
CL* = 3
t
WR
7
CL* = 2
10
1000
CLK Cycle Time
CL* = 3
t
CK
7 1000
CLK High Level Width
t
CH
2
CLK Low Level Width
t
CL
2
CL* = 2
5.5
Access Time from CLK
CL* = 3
t
AC
5
Output Data Hold Time
t
OH
2.5
Output Data High Impedance Time
t
HZ
2.5 7
Output Data Low Impedance Time
t
LZ
0
Power Down Mode Entry Time
t
SB
0 7
Transition Time of CLK (Rise and Fall)
t
T
0.5 10
Data-in-Set-up Time
t
DS
1.5
Data-in Hold Time
t
DH
1
Address Set-up Time
t
AS
1.5
Address Hold Time
t
AH
1
CKE Set-up Time
t
CKS
1.5
CKE Hold Time
t
CKH
1
Command Set-up Time
t
CMS
1.5
Command Hold Time
t
CMH
1
Refresh Time
t
REF
64
mS
Mode Register Set Cycle Time
t
RSC
14
nS
(L):For low power
W9816G6BB
- 16 -
Notes:
1.
Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
2.
All voltages are referenced to V
SS.
3.
These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values
of tCK and tRC.
4.
These parameters depend on the output loading conditions. Specified values are obtained with output open.
5.
Power up sequence is further described in the "Functional Description" section.
6.
AC test conditions.
PARAMETER CONDITIONS
Output Reference Level
1.4V/1.4V
Output Load
See diagram below
Input Signal Levels
2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal
2 nS
Input Reference Level
1.4V
50 ohms
1.4 V
Z = 50 ohms
output
AC TEST LOAD
30pF
7.
Transition times are measured between V
IH
and V
IL
.
8.
tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
W9816G6BB
Publication Release Date: January 2, 2003
- 17 -
Revision A1
13. TIMING WAVEFORMS
Command Input Timing
t
CK
CLK
A0-A10
BA
V
IH
V
IL
t
CMH
t
CMS
t
CH
t
CL
t
T
t
T
t
CKS
t
CKH
t
CKH
t
CKS
t
CKS
t
CKH
CS
RAS
CAS
WE
CKE
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
W9816G6BB
- 18 -
Timing Waveforms, continued
Read Timing
Read CAS Latency
t
AC
t
LZ
t
AC
t
OH
t
HZ
t
OH
Burst Length
Read Command
CLK
CS
RAS
CAS
WE
A0-A10
BA
DQ
Valid
Data-Out
Valid
Data-Out
W9816G6BB
Publication Release Date: January 2, 2003
- 19 -
Revision A1
Timing Waveforms, continued
Control Timing of Input/Output Data
t
CMH
t
CMS
t
CMH
t
CMS
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
CKH
t
CKS
t
CKH
t
CKS
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
DS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
CMH
t
CMS
t
CMH
t
CMS
t
OH
t
AC
t
OH
t
AC
t
OH
t
HZ
OPEN
t
LZ
t
AC
t
OH
t
AC
t
CKH
t
CKS
t
CKH
t
CKS
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
CLK
DQM
DQ0 -15
(Word Mask)
(Clock Mask)
CLK
CKE
DQ0 -15
CLK
Input Data
Output Data
(Output Enable)
(Clock Mask)
DQM
DQ0 -15
CKE
CLK
DQ0 -15
W9816G6BB
- 20 -
Timing Waveforms, continued
Mode Reqister Set Cycle
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8
Reserved
A0
A7
A0
A9
A0
Write Mode
A10
BA
"0"
"0"
A3
Addressing Mode
A0
0
Sequential
A0
1
Interleave
A9
Single Write Mode
0
Burst read and Burst write
1
Burst read and single write
A2 A1 A0
A0
0 0 0
A0
0 0 1
A0
0 1 0
A0
0 1 1
A0
1 0 0
A0
1 0 1
A0
1 1 0
A0
1 1 1
Burst Length
A0
Sequential
A0
Interleave
1
1
2
2
4
4
A0
8
8
Reserved
Reserved
A0
Full Page
CAS Latency
Reserved
A0
Reserved
2
3
Reserved
A0
A6 A5 A4
A0
0 0 0
0 1 0
0 1 1
1 0 0
0 0 1
t
RSC
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
CLK
CS
RAS
CAS
WE
A0-A10
BA
Register
set data
next
command
A0
Reserved
"0"
"0"
W9816G6BB
Publication Release Date: January 2, 2003
- 21 -
Revision A1
Timing Waveforms, continued
Interleaved Bank Read
(Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
t
RC
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RP
t
RAS
t
RAS
t
RCD
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active
Read
Active
Read
Active
Active
Active
Read
Read
Precharge
Precharge
Precharge
RAa
RBb
RAc
RBd
RAe
RAa
CAw
RBb
CBx
RAc
CAy
RBd
CBz
RAe
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
cy0
cy1
cy2
cy3
Bank #0
Bank #1
W9816G6BB
- 22 -
Timing Waveforms, continued
Interleaved Bank Read
(Burst Length = 4, CAS Latency = 3, Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active
Read
Active
Read
Active
Active
Active
Read
Read
t
RC
RAa
RAc
RBd
RAe
DQ
aw0
aw1 aw2
aw3
bx0
bx1
bx2
bx3
cy0
cy1
cy2
cy3
dz0
* AP is the internal precharge start timing
Bank #0
Bank #1
AP*
AP*
AP*
RAa
CAw RBb
CBx
RAc
CAy
RBd
RAe
CBz
RBb
W9816G6BB
Publication Release Date: January 2, 2003
- 23 -
Revision A1
Timing Waveforms, continued
Interleaved Bank Read
(Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAc
RAc
CAz
ax0
ax1
ax2
ax3
ax4
ax5
ax6
by0
by1
by4
by5
by6
by7
CZ0
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Active
Read
Precharge
Active
Read
Precharge
Active
t
AC
t
AC
Read
Precharge
t
AC
Bank #0
Bank #1
W9816G6BB
- 24 -
Timing Waveforms, continued
Interleaved Bank Read
(Burst Length = 8, CAS Latency = 3, Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
ax0
ax1
ax2
ax3
ax4
ax5
ax6
ax7
by0
by1
by4
by5
by6
CZ0
RAa
RAa
CAx
RBb
RBb
CBy
(CLK = 100 MHz)
RAc
RAc
CAz
* AP is the internal precharge start timing
Active
Read
Active
Active
Read
t
CAC
t
CAC
t
CAC
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
Bank #0
Bank #1
Read
AP*
AP*
W9816G6BB
Publication Release Date: January 2, 2003
- 25 -
Revision A1
Timing Waveforms, continued
Interleaved Bank Write
(Burst Length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAc
RAc
CAz
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
(CLK = 100 MHz)
Write
Precharge
Active
Active
Write
Precharge
Active
Write
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Bank #0
Bank #1
t
RAS
W9816G6BB
- 26 -
Timing Waveforms, continued
Interleaved Bank Write
(Burst Length = 8, Auto Precharge)
Bank #0
Bank #1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RC
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa
CAx
RBb
RBb
CBy
RAb
RAb
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
CAz
(CLK = 100 MHz)
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
Active
Write
Write
Active
AP*
Active
Write
AP*
BA
W9816G6BB
Publication Release Date: January 2, 2003
- 27 -
Revision A1
Timing Waveforms, continued
Page Mode Read
(Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
CCD
t
CCD
t
CCD
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RRD
RAa
RAa
CAI
RBb
RBb
CBx
CAy
CAm
CBz
a0
a1
a2
a3
bx0
bx1
Ay0
Ay1
Ay2
am0
am1
am2
bz0
bz1
bz2
bz3
(CLK = 100 MHz)
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Active
Read
Active
Read
Read
Read
Read
Precharge
t
AC
t
AC
t
AC
t
AC
t
AC
Bank #0
Bank #1
AP*
W9816G6BB
- 28 -
Timing Waveforms, continued
Page Mode Read/Write
(Burst Length = 8, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
t
RAS
t
RP
t
RCD
t
WR
RAa
RAa
CAx
CAy
ax0
ax1
ax2
ax3
ax4
ax5
ay1
ay0
ay2
ay4
ay3
Q Q
Q
Q
Q
Q
D
D
D
D
D
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Active
Read
Write
Precharge
t
AC
Bank #0
Bank #1
W9816G6BB
Publication Release Date: January 2, 2003
- 29 -
Revision A1
Timing Waveforms, continued
Auto Precharge Read
(Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
AC
t
AC
Active
Read
AP*
Active
Read
AP*
RAa
RAb
RAa
CAw
RAb
CAx
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
* AP is the internal precharge start timing
Bank #0
Bank #1
W9816G6BB
- 30 -
Timing Waveforms, continued
Auto Precharge Write
(Burst Length = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CS
BS0
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
RAa
t
RCD
t
RCD
RAb
RAc
RAa
CAw
RAb
CAx
RAc
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
Active
Active
Write
AP*
Active
Write
AP*
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
RAS
CAS
W9816G6BB
Publication Release Date: January 2, 2003
- 31 -
Revision A1
Timing Waveforms, continued
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
t
RC
t
RP
t
RC
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
W9816G6BB
- 32 -
Timing Waveforms, continued
Self Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
t
CKS
t
SB
t
CKS
t
CKS
All Banks
Precharge
Self Refresh
Entry
Arbitrary Cycle
t
RP
Self Refresh Cycle
t
RC
No Operation Cycle
W9816G6BB
Publication Release Date: January 2, 2003
- 33 -
Revision A1
Timing Waveforms, continued
Bust Read and Single Write
(Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BA
A10
A0-A9
DQM
CKE
DQ
(CLK = 100 MHz)
t
RCD
RBa
RBa
CBv
CBw
CBx CBy
CBz
av0
av1
av2
av3
aw0
ax0
ay0
az0
az1
az2
az3
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
t
AC
t
AC
Read
Read
Single Write
Active
Bank #0
Bank #1
W9816G6BB
- 34 -
Timing Waveforms, continued
Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
(CLK = 100 MHz)
RAa
CAa
RAa
CAx
RAa
RAa
ax0
ax1
ax2
ax3
t
SB
t
CKS
t
CKS
t
CKS
t
SB
t
CKS
Active Standby
Power Down mode
Precharge Standby
Power Down mode
Active
NOP
Precharge
NOPActive
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CS
Read
RAS
CAS
W9816G6BB
Publication Release Date: January 2, 2003
- 35 -
Revision A1
Timing Waveforms, continued
Auto Precharge Timing
(Read Cycle)
Read
AP
0
11
10
9
8
7
6
5
4
3
2
1
Q0
Q0
Read
AP
Act
Q1
Read
AP
Act
Q1
Q2
AP
Act
Read
Act
Q0
Q3
(1) CAS Latency=2
Read
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
RAS
(min).
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note:
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
t
RP
Q0
Read
AP
Act
Q0
Read
AP
Act
Q1
Q0
Read
AP
Act
Q1
Q2
Q3
Read
AP
Act
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
(2) CAS Latency=3
t
RP
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W9816G6BB
- 36 -
Timing Waveforms, continued
Auto Precharge Timing
(Write Cycle)
0
11
10
9
8
7
6
5
4
3
2
1
Act
AP
AP
AP
Write
Act
AP
D0
D0
D0
AP
Act
D1
AP
Act
D1
D2
D3
AP
Act
Write
Write
Write
D0
D0
D1
D2
D3
D4
D5
D6
D7
AP
Act
D1
D0
Act
D1
D2
D3
Act
D0
D1
D2
D3
D4
D5
D6
D7
Write
Write
Write
Write
D0
(1) CAS Latency = 2
(2) CAS Latency = 3
Write
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS
(min) .
represents the Write with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note:
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
t
RP
t
WR
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W9816G6BB
Publication Release Date: January 2, 2003
- 37 -
Revision A1
Timing Waveforms, continued
Timing Chart of Write-to-Read Cycle
In the case of Burst Length = 4
0
11
10
9
8
7
6
5
4
3
2
1
Q0
Read
Q1
Q2
Q3
Read
Write
Write
D0
D1
DQ
DQ
( a ) Command
( b ) Command
DQM
DQM
(2) CAS Latency = 3
Q0
Q1
Q2
Q3
D0
Read
Write
Read
Write
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
(1) CAS Latency = 2
D0
D0
D1
Timing Chart of Burst Stop Cycle
(Burst Stop Command)
Read
BST
0
11
10
9
8
7
6
5
4
3
2
1
DQ
DQ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Read
BST
( a ) CAS latency =2
Command
( b ) CAS latency = 3
Command
(3) Read cycle
Q4
Q4
DQ
D0
D1
D2
D3
Write
BST
Command
(2) Write cycle
D4
Note:
represents the Burst stop command
BST
W9816G6BB
- 38 -
Timing Waveforms, continued
Timing Chart of Burst Stop Cycle (Prechare Command)
(In the case of Burst Length = 8)
Note: represents the Precharge command
PRCG
Read
PRCG
0
11
10
9
8
7
6
5
4
3
2
1
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Read
PRCG
Q4
Q4
( a ) CAS latency = 2
( b ) CAS latency = 3
DQ
DQ
(1) Read cycle
(2) Write cycle
Commad
Commad
Write
PRCG
D0
D1
D2
D3
D0
D1
D2
D3
Write
PRCG
D4
D4
( b ) CAS latency = 3
DQ
( a ) CAS latency = 2
DQM
DQM
DQ
t
WR
t
WR
Commad
Commad
W9816G6BB
Publication Release Date: January 2, 2003
- 39 -
Revision A1
Timing Waveforms, continued
CKE/DQM Input Timing
(Write Cycle)
7
6
5
4
3
2
1
CKE MASK
( 1 )
D1
D6
D5
D3
D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5
4
3
2
1
( 2 )
D1
D6
D5
D3
D2
7
6
5
4
3
2
1
( 3 )
D1
D6
D5
D4
D3
D2
CLK cycle No.
External
CKE
DQM
DQ
DQM MASK
DQM MASK
CKE MASK
CKE MASK
Internal
CLK
CLK cycle No.
External
Internal
CKE
DQM
DQ
CLK
CLK
W9816G6BB
- 40 -
Timing Waveforms, continued
CKE/DQM Input Timing
(Read Cycle)
7
6
5
4
3
2
1
( 1 )
Q1
Q6
Q4
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open
Open
7
6
5
4
3
2
1
Q1
Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open
( 2 )
7
6
5
4
3
2
1
Q1
Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Q5
Q4
( 3 )
Q4
CLK
CLK
CLK
W9816G6BB
Publication Release Date: January 2, 2003
- 41 -
Revision A1
Timing Waveforms, continued
Self Refresh/ Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time ( Power down mode exit time ) is specified by t
CKS
(min) + t
CK
(min)
Command
NOP
CLK
CKE
Command
A ) t
CK
< t
CKS
(min)+t
CK
(min)
Input Buffer Enable
Command
CLK
CKE
Command
B) t
CK
>= t
CKS
(min) + t
CK
(min)
Input Buffer Enable
Note )
Command
NOP
All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
Represents the No-Operation command
Represents one command
t
CK
t
CK
t
CKS
(min)+t
CK
(min)
t
CKS
(min)+t
CK
(min)
W9816G6BB
- 42 -
14. PACKAGE DIMENSIONS
BGA 60 Balls Pitch = 0.65 mm
W9816G6BB
Publication Release Date: January 2, 2003
- 43 -
Revision A1























Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.