Features

· Pin Compatible with NMOS 8255A

· 24 Programmable I/O Pins

· Fully TTL Compatible

· High Speed, No "Wait State" Operation with 5MHz

· Direct Bit Set/Reset Capability

· Enhanced Control Word Read Capability

· L7 Process

· 2.5mA Drive Capability on All I/O Ports

· Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10

Description

the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the

make it compatible with the 80C86, and

other microprocessors.

Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.

PA3

PA2

PA1

PA0

GND

PC7

PC6

PC5

PC4

PC0

PC1

PC2

PC3

PB0

PB1

PB2

PA4

PA5

PA6

PA7

RESET

PB7

PB6

PB5

PB4

PB3

5
6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Wing Shing Computer Components Co., (H.K.)Ltd.

Tel:(852)2341 9276 Fax:(852)2797 8153

Homepage:

http://www.wingshing.com

E-mail: wsccltd@hkstar.com

RESET

GND

GND

A1
A0

PC7

PC6
PC5
PC4
PC0
PC1

PC3

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

RESET
D0
D1
D2
D3

D4
D5
D6
D7
V

PC2

44 43 42 41 40

39
38
37
36
35
34
33
32
31
30
29

7
8
9
10
11
12
13
14
15
16
17

CMOS Programmable peripheral
Interface

80C86

DIP-40

Pinouts

SPEED

QFP-44

44 QFP

44 PLCC

0 C to 70 C

PLCC-44

WS82C55A-5P

WS82C55A-5Q

WS82C55A-5C

WS82C55A-5P

WS82C55A-5Q

WS82C55A-5C

0 C to 70 C

PKG.

TEMPERATURE

RANGE

SPEED

8MHz

5MHz

PART NUMBERS

40DIP

Ordering Information

and 8MHz 80C88

The WS82C55A is a high performance CMOS version of

WS82C55A

WS82C55A

WS82C55AP

WS82C55AC

WS82C55AQ

WS82C55AP

WS82C55AQ

WS82C55AC

Functional Diagram

Pin Description

SYMBOL

PIN

NUMBER

TYPE

DESCRIPTION

: The +5V power supply pin. A 0.1

F capacitor between pins 26 and 7 is

recommended for decoupling.

GND

GROUND

D0-D7

27-34

I/O

DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.

RESET

RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the "Bus Hold" circuitry turned on.

CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.

READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.

WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.

A0-A1

8, 9

ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.

PA0-PA7

1-4, 37-40

I/O

PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.

PB0-PB7

18-25

I/O

PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.

PC0-PC7

10-17

I/O

PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.

GROUP A

PORT A

(8)

GROUP A

PORT C

UPPER

(4)

GROUP B

PORT C

LOWER

(4)

GROUP B

PORT B

(8)

GROUP B

CONTROL

GROUP A

CONTROL

DATA BUS

BUFFER

READ

WRITE

CONTROL

LOGIC

RESET

D7-D0

POWER

SUPPLIES

+5V

GND

BI-DIRECTIONAL

DATA BUS

I/O

PA7-PA0

I/O

PC7-PC4

I/O

PC3-PC0

I/O

PB7-PB0

8-BIT

INTERNAL

DATA BUS

( For DIP-40)

WS82C55A

Functional Description

Data Bus Buffer

This three-state bi-directional 8-bit buffer is used to interface

to the system data bus. Data is transmitted or

received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa-
tion are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.

(CS) Chip Select. A "low" on this input pin enables the
communcation between the

(RD) Read. A "low" on this input pin enables
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to "read from" the

(WR) Write. A "low" on this input pin enables the CPU to
write data or control words into the

(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).

(RESET) Reset. A "high" on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. "Bus hold" devices internal to the 82C55A will hold
the I/O port inputs to a logic "1" state with a maximum hold
current of 400

Group A and Group B Controls

The functional configuration of each port is programmed by
the systems software. In essence, the CPU "outputs" a con-

. The control word contains

information such as "mode", "bit set", "bit reset", etc., that ini-
tializes the functional configuration of the

Each of the Control blocks (Group A and Group B) accepts
"commands" from the Read/Write Control logic, receives
"control words" from the internal data bus and issues the
proper commands to its associated ports.

Control Group A - Port A and Port C upper (C7 - C4)

Control Group B - Port B and Port C lower (C3 - C0)

The control word register can be both written and read as
shown in the "Basic Operation" table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
"1", as this implies control word mode information.

82C55A BASIC OPERATION

INPUT OPERATION

(READ)

Port A

Data Bus

Port B

Data Bus

Port C

Data Bus

Control Word

Data Bus

OUTPUT OPERATION

(WRITE)

Data Bus

Port A

Data Bus

Port B

Data Bus

Port C

Data Bus

Control

DISABLE FUNCTION

Data Bus

Three-State

Data Bus

Three-State

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,

READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS

GROUP A

PORT A

(8)

GROUP A

PORT C

UPPER

(4)

GROUP B

PORT C

LOWER

(4)

GROUP B

PORT B

(8)

GROUP B

CONTROL

GROUP A

CONTROL

DATA

READ

WRITE

CONTROL

LOGIC

A1
A0

RESET

D7-D0

POWER

SUPPLIES

+5V
GND

BI-DIRECTIONAL

DATA BUS

I/O

PA7-

I/O

PC7-

I/O

PC3-

I/O

PB7-

BUFFER

BUS

PB0

PC0

PC4

PA0

8-BIT

INTERNAL

DATA BUS

and the CPU

82C55A to send

WS82C55A

WS82C55A

trol word to the WS82C55A

WS82C55A

Ports A, B, and C

contains three 8-bit ports (A, B, and C). All can

be configured to a wide variety of functional characteristics
by the system software but each has its own special features
or "personality" to further enhance the power and flexibility of
the

Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both "pull-up" and "pull-down" bus-hold devices
are present on Port A. See Figure 2A.

Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.

Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
two 4-bit ports under the mode control. Each 4-bit port con-
tains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.

Operational Description

Mode Selection

There are three basic modes of operation than can be
selected by the system software:

Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus

When the reset input goes "high", all ports will be set to the
input mode with all 24 port lines held at a logic "one" level by
internal bus hold devices. After the reset is removed, the

can remain in the input mode with no additional ini-

tialization required. This eliminates the need to pullup or pull-
down resistors in all-CMOS designs. The control word

register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when the control word is written.

FIGURE 2A. PORT A BUS-HOLD CONFIGURATION

FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION

FIGURE 2. BUS-HOLD CONFIGURATION

MASTER

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL

DATA OUT

(LATCHED)

EXTERNAL
PORT A PIN

OUTPUT MODE

INPUT MODE

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL

DATA OUT

(LATCHED)

EXTERNAL
PORT B, C

OUTPUT MODE

PIN

FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE

DATA BUS

I/O

PB7-PB0

I/O

PC3-PC0

I/O

PC7-PC4

I/O

PA7-PA0

CONTROL BUS

ADDRESS BUS

RD, WR

82C55A

D7-D0

A0-A1

MODE 0

I/O

PB7-PB0

CONTROL

I/O

PA7-PA0

MODE 1

OR I/O

CONTROL

OR I/O

I/O

PB7-PB0

BI-

PA7-PA0

MODE 2

CONTROL

DIRECTIONAL

FIGURE 4. MODE DEFINITION FORMAT

D7 D6 D5

D4 D3 D2 D1 D0

PORT C (LOWER)
1 = INPUT
0 = OUTPUT

PORT B
1 = INPUT
0 = OUTPUT

MODE SELECTION
0 = MODE 0
1 = MODE 1

GROUP B

PORT C (UPPER)
1 = INPUT
0 = OUTPUT

PORT A
1 = INPUT
0 = OUTPUT

MODE SELECTION
00 = MODE 0
01 = MODE 1

GROUP A

1X = MODE 2

MODE SET FLAG
1 = ACTIVE

CONTROL WORD

WS82C55A

The WS82C55A

WS82C55A

The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be "tailored" to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display compu-
tational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.

The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal defi-
nition vs. PC layout and complete functional flexibility to sup-
port almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.

Single Bit Set/Reset Feature (Figure 5)

Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.

When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.

Interrupt Control Functions

is programmed to operate in mode 1 or

mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using the
bit set/reset function of port C.

This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.

INTE Flip-Flop Definition

(BIT-SET)-INTE is SET - Interrupt Enable

(BIT-RESET)-INTE is Reset - Interrupt Disable

NOTE:

All Mask flip-flops are automatically reset during mode se-

lection and device Reset.

Operating Modes

Mode 0 (Basic Input/Output). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply writ-
ten to or read from a specific port.

Mode 0 Basic Functional Definitions:

· Two 8-bit ports and two 4-bit ports

· Any Port can be input or output

· Outputs are latched

· Input are not latched

· 16 different Input/Output configurations possible

FIGURE 5. BIT SET/RESET FORMAT

D7 D6 D5

D4 D3 D2 D1 D0

BIT SET/RESET
1 = SET
0 = RESET

BIT SELECT

BIT SET/RESET FLAG

CONTROL WORD

DON'T

CARE

0 = ACTIVE

1 2 3 4 5 6 7

0 1 0 1 0 1 0 1

0 0 1 1 0 0 1 1

0 0 0 0 1 1 1 1

MODE 0 PORT DEFINITION

GROUP A

GROUP B

PORT A

PORTC

(Upper)

PORT B

PORTC

(Lower)

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

WS82C55A

When WS82C55A

Mode 0 (Basic Input)

Mode 0 (Basic Output)

Mode 0 Configurations

CONTROL WORD #0

CONTROL WORD #2

CONTROL WORD #1

CONTROL WORD #3

tRA

tHR

tRR

tIR

tAR

tRD

tDF

INPUT

CS, A1, A0

D7-D0

tAW

tWA

tWB

tWW

tWD

tDW

D7-D0

CS, A1, A0

OUTPUT

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

WS82C55A

CONTROL WORD #4

CONTROL WORD #8

CONTROL WORD #5

CONTROL WORD #9

CONTROL WORD #6

CONTROL WORD #10

CONTROL WORD #7

CONTROL WORD #11

Mode 0 Configurations

(Continued)

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

WS82C55A

Operating Modes

Mode 1 - (Strobed Input/Output). This functional configura-
tion provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or "hand shaking"
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these "hand shaking" signals.

Mode 1 Basic Function Definitions:

· Two Groups (Group A and Group B)

· Each group contains one 8-bit port and one 4-bit

control/data port

· The 8-bit data port can be either input or output. Both

inputs and outputs are latched.

· The 4-bit port is used for control and status of the 8-bit

port.

Input Control Signal Definition

(Figures 6 and 7)

STB (Strobe Input)

A "low" on this input loads data into the input latch.

IBF (Input Buffer Full F/F)

A "high" on this output indicates that the data has been
loaded into the input latch: in essence, and acknowledg-
ment. IBF is set by STB input being low and is reset by the
rising edge of the RD input.

CONTROL WORD #12

CONTROL WORD #14

CONTROL WORD #13

CONTROL WORD #15

Mode 0 Configurations

(Continued)

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

PA7 - PA0

PC7 - PC4

PC3 - PC0

PB7 - PB0

D7 - D0

82C55A

FIGURE 6. MODE 1 INPUT

1/0

D3 D2 D1 D0

CONTROL WORD

MODE 1 (PORT A)

PC4

IBFA

PC5

INTE

PA7-PA0

STBA

INTRA

PC3

PC6, PC7

I/O

PC6, PC7
1 = INPUT
0 = OUTPUT

D7 D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

MODE 1 (PORT B)

PC2

IBFB

PC1

INTE

PB7-PB0

STBB

INTRB

PC0

WS82C55A

INTR (Interrupt Request)

A "high" on this output can be used to interrupt the CPU
when and input device is requesting service. INTR is set by
the condition: STB is a "one", IBF is a "one" and INTE is a
"one". It is reset by the falling edge of RD. This procedure
allows an input device to request service from the CPU by
simply strobing its data into the port.

INTE A

Controlled by bit set/reset of PC4.

INTE B

Controlled by bit set/reset of PC2.

Output Control Signal Definition

(Figure 8 and 9)

OBF - Output Buffer Full F/F). The OBF output will go "low"
to indicate that the CPU has written data out to be specified
port. This does not mean valid data is sent out of the part at
this time since OBF can go true before data is available.
Data is guaranteed valid at the rising edge of OBF, (See
Note 1). The OBF F/F will be set by the rising edge of the
WR input and reset by ACK input being low.

ACK - Acknowledge Input). A "low" on this input informs the
82C55A that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).

INTR - (Interrupt Request). A "high" on this output can be
used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when
ACK is a "one", OBF is a "one" and INTE is a "one". It is
reset by the falling edge of WR.

INTE A

Controlled by Bit Set/Reset of PC6.

INTE B

Controlled by Bit Set/Reset of PC2.

NOTE:

1. To strobe data into the peripheral device, the user must operate

the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generates an ACK from the pe-
ripheral device and then latch data into the peripheral device on
the rising edge of OBF.

FIGURE 7. MODE 1 (STROBED INPUT)

tST

STB

INTR

INPUT FROM

IBF

PERIPHERAL

tSIB

tSIT

tPH

tPS

tRIT

tRIB

FIGURE 8. MODE 1 OUTPUT

1/0

D3 D2 D1 D0

CONTROL WORD

MODE 1 (PORT A)

PC7

ACKA

PC6

PA7-PA0

OBFA

INTRA

PC3

PC4, PC5

PC4, PC5
1 = INPUT
0 = OUTPUT

D7 D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

MODE 1 (PORT B)

PC1

ACKB

PC2

INTE

PB7-PB0

OBFB

INTRB

PC0

INTE

WS82C55A

Operating Modes

Mode 2 (Strobed Bi-Directional Bus I/O)

The functional configuration provides a means for communi-
cating with a peripheral device or structure on a single 8-bit
bus for both transmitting and receiving data (bi-directional
bus I/O). "Hand shaking" signals are provided to maintain
proper bus flow discipline similar to Mode 1. Interrupt gener-
ation and enable/disable functions are also available.

Mode 2 Basic Functional Definitions:

· Used in Group A only

· One 8-bit, bi-directional bus Port (Port A) and a 5-bit

control Port (Port C)

· Both inputs and outputs are latched

· The 5-bit control port (Port C) is used for control and

status for the 8-bit, bi-directional bus port (Port A)

Bi-Directional Bus I/O Control Signal Definition

(Figures 11, 12, 13, 14)

INTR - (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.

Output Operations

OBF - (Output Buffer Full). The OBF output will go "low" to
indicate that the CPU has written data out to port A.

ACK - (Acknowledge). A "low" on this input enables the
three-state output buffer of port A to send out the data. Oth-
erwise, the output buffer will be in the high impedance state.

INTE 1 - (The INTE flip-flop associated with OBF). Con-
trolled by bit set/reset of PC4.

Input Operations

STB - (Strobe Input). A "low" on this input loads data into the
input latch.

IBF - (Input Buffer Full F/F). A "high" on this output indicates
that data has been loaded into the input latch.

INTE 2 - (The INTE flip-flop associated with IBF). Controlled
by bit set/reset of PC4.

FIGURE 9. MODE 1 (STROBED OUTPUT)

tWOB

tWB

tAK

tAIT

tAOB

tWIT

OBF

INTR

ACK

OUTPUT

Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O
applications.

FIGURE 10. COMBINATIONS OF MODE 1

1/0

D3 D2 D1 D0

CONTROL WORD

PORT A - (STROBED INPUT)

PC4

OBFB

PA7-PA0

STBA

INTRB

PC0

PC6, PC7

PC6, PC7
1 = INPUT
0 = OUTPUT

PORT B - (STROBED OUTPUT)

IIBFA

PC5

INTRA

PC3

ACKB

PC2

I/O

PC1

PB7, PB0

1/0

D3 D2 D1 D0

CONTROL WORD

PORT A - (STROBED OUTPUT)

PC7

STBB

PA7-PA0

OBFA

INTRB

PC0

PC4, PC5

PC4, PC5
1 = INPUT
0 = OUTPUT

PORT B - (STROBED INPUT)

ACKA

PC6

INTRA

PC3

IBFB

PC1

I/O

PC2

PB7, PB0

WS82C55A

FIGURE 11. MODE CONTROL WORD

FIGURE 12. MODE 2

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF

MASK

STB

OBF

MASK

ACK

WR)

FIGURE 13. MODE 2 (BI-DIRECTIONAL)

D7 D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

1/0 1/0

1/0

PC2-PC0
1 = INPUT
0 = OUTPUT

PORT B
1 = INPUT
0 = OUTPUT

GROUP B MODE
0 = MODE 0
1 = MODE 1

PC7

OBFA

PC6

INTE

PA7-PA0

ACKA

IBFA

PC4

INTE

PC3

PC5

PC2-PC0

STBA

I/O

INTRA

tWOB

tAOB

tAK

tAD

tKD

tPH

tPS

tSIB

tST

OBF

INTR

ACK

IBF

STB

PERIPHERAL

BUS

tRIB

DATA FROM

PERIPHERAL TO

DATA FROM

TO PERIPHERAL

DATA FROM

TO CPU

DATA FROM

CPU TO 82C55A

WS82C55A

MODE 2 AND MODE 0 (INPUT)

MODE 2 AND MODE 0 (OUTPUT)

MODE 2 AND MODE 1 (OUTPUT)

MODE 2 AND MODE 1 (INPUT)

FIGURE 14. MODE 2 COMBINATIONS

D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

PC7

STBA

PA7-PA0

OBFA

IBFA

PC5

PC2-PC0

PC2-PC0
1 = INPUT
0 = OUTPUT

ACKA

PC6

INTRA

PC3

I/O

PC4

PB7-PB0

1/0

D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

PC7

STBA

PA7-PA0

OBFA

IBFA

PC5

PC2-PC0

PC2-PC0
1 = INPUT
0 = OUTPUT

ACKA

PC6

INTRA

PC3

I/O

PC4

PB7, PB0

1/0

D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

PC7

STBA

PA7-PA0

OBFA

IBFA

PC5

ACKA

PC6

INTRA

PC3

PC4

PB7-PB0

PC1

OBFB

ACKB

PC2

PC0

INTRB

D6 D5 D4 D3 D2 D1 D0

CONTROL WORD

PC7

STBA

PA7-PA0

OBFA

IBFA

PC5

ACKA

PC6

INTRA

PC3

PC4

PB7-PB0

PC2

STBB

PC1

PC0

INTRB

IBFB

WS82C55A

Special Mode Combination Considerations

There are several combinations of modes possible. For any
combination, some or all of Port C lines are used for control
or status. The remaining bits are either inputs or outputs as
defined by a "Set Mode" command.

During a read of Port C, the state of all the Port C lines,
except the ACK and STB lines, will be placed on the data
bus. In place of the ACK and STB line states, flag status will
appear on the data bus in the PC2, PC4, and PC6 bit
positions as illustrated by Figure 17.

Through a "Write Port C" command, only the Port C pins
programmed as outputs in a Mode 0 group can be written.
No other pins can be affected by a "Write Port C" command,
nor can the interrupt enable flags be accessed. To write to
any Port C output programmed as an output in Mode 1 group
or to change an interrupt enable flag, the "Set/Reset Port C
Bit" command must be used.

With a "Set/Reset Port Cea Bit" command, any Port C line
programmed as an output (including IBF and OBF) can be
written, or an interrupt enable flag can be either set or reset.
Port C lines programmed as inputs, including ACK and STB
lines, associated with Port C fare not affected by a
"Set/Reset Port C Bit" command. Writing to the correspond-
ing Port C bit positions of the ACK and STB lines with the
"Set Reset Port C Bit" command will affect the Group A and
Group B interrupt enable flags, as illustrated in Figure 17.

Current Drive Capability

Any output on Port A, B or C can sink or source 2.5mA. This
feature allows the 82C55A to directly drive Darlington type
drivers and high-voltage displays that require such sink or
source current.

MODE DEFINITION SUMMARY

MODE 0

MODE 1

MODE 2

OUT

GROUP A ONLY

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

INTRB

IBFB

STBB

INTRA

STBA

IBFA

I/O
I/O

INTRB

OBFB
ACKB

INTRA

I/O
I/O

ACKA
OBFA

I/O
I/O
I/O

INTRA

STBA

IBFA

ACKA
OBFA

Mode 0
or Mode 1
Only

INPUT CONFIGURATION

I/O

IBFA

INTEA INTRA INTEB

IBFB

INTRB

OUTPUT CONFIGURATION

OBFA INTEA

I/O

INTRA INTEB OBFB INTRB

FIGURE 15. MODE 1 STATUS WORD FORMAT

OBFA

INTE1

IBFA

INTE2 INTRA

(Defined by Mode 0 or Mode 1 Selection)

FIGURE 16. MODE 2 STATUS WORD FORMAT

GROUP A

GROUP B

GROUP A

GROUP B

GROUP A

GROUP B

WS82C55A

Reading Port C Status (Figures 15 and 16)

In Mode 0, Port C transfers data to or from the peripheral
device. When the 82C55A is programmed to function in
Modes 1 or 2, Port C generates or accepts "hand shaking"
signals with the peripheral device. Reading the contents of
Port C allows the programmer to test or verify the "status" of
each peripheral device and change the program flow
accordingly.

There is not special instruction to read the status information
from Port C. A normal read operation of Port C is executed to
perform this function.

Applications of the

is a very powerful tool for interfacing peripheral

equipment to the microcomputer system. It represents the
optimum use of available pins and flexible enough to inter-
face almost any I/O device without the need for additional
external logic.

Each peripheral device in a microcomputer system usually
has a "service routine" associated with it. The routine
manages the software interface between the device and the
CPU. The functional definition of
by the I/O service routine and becomes an extension of the
system software. By examining the I/O devices interface
characteristics for both data transfer and timing, and
matching this information to the examples and tables in the
detailed operational description, a control word can easily be
developed to initialize the
application. Figures 18 through 24 present a few examples
of typical applications of the

INTERRUPT

ENABLE FLAG

POSITION

ALTERNATE PORT C

PIN SIGNAL (MODE)

INTE B

PC2

ACKB (Output Mode 1)
or STBB (Input Mode 1)

INTE A2

PC4

STBA (Input Mode 1 or
Mode 2)

INTE A1

PC6

ACKA (Output Mode 1 or
Mode 2)

FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2

FIGURE 18. PRINTER INTERFACE

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC7
PC6
PC5
PC4

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC1
PC2

DATA READY
ACK
PAPER FEED
FORWARD/REV.

DATA READY
ACK

PAPER FEED
FORWARD/REV.
RIBBON
CARRIAGE SEN.

MODE 1

(OUTPUT)

82C55A

MODE 1

(OUTPUT)

CONTROL LOGIC

AND DRIVERS

INTERRUPT

REQUEST

PC0

INTERRUPT

REQUEST

PC3

HAMMER

RELAYS

HIGH SPEED

PRINTER

WS82C55A-5

WS82C55A

WS82C55A

WS82C55A to exactly "fit" the

the WS82C55A is programmed

FIGURE 19. KEYBOARD AND DISPLAY INTERFACE

FIGURE 20. KEYBOARD AND TERMINAL ADDRESS

INTERFACE

FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL

FIGURE 22. BASIC CRT CONTROLLER INTERFACE

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC1
PC2

STROBE
ACK

DATA READY
ACK

MODE 1

(OUTPUT)

MODE 1

(INPUT)

FULLY

DECODED

INTERRUPT

REQUEST

INTERRUPT

REQUEST

PC3

PC6
PC7

KEYBOARD

R0
R1
R2
R3
R4
R5
SHIFT
CONTROL

B0
B1
B2
B3
B4
B5
BACKSPACE
CLEAR

BURROUGHS

SELF-SCAN

DISPLAY

BLANKING
CANCEL WORD

STROBE
ACK

FULLY

DECODED

KEYBOARD

R0
R1
R2
R3
R4
R5
SHIFT
CONTROL

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5
PC6
PC7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

MODE 0

(INPUT)

MODE 1

(INPUT)

PC3

BUST LT
TEST LT

TERMINAL

ADDRESS

INTERRUPT

REQUEST

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5
PC6
PC7

PC1

PC2
PC3

PB0
PB1
PB2

PC4
PC5

LSB

STB DATA

MAB

MODE 0

(INPUT)

MODE 0

(OUTPUT)

12-BIT

A/D

CONVERTER

(DAC)

PC0

PB3

PC6

PC7

BIT

SET/RESET

SAMPLE EN
STB

LSB

8-BIT

D/A

CONVERTER

(ADC)

ANALOG
INPUT

ANALOG
OUTPUT

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC7
PC6
PC5
PC4

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC2
PC1

MODE 0

(OUTPUT)

MODE 1

(OUTPUT)

PC3

DATA READY
ACK

CRT CONTROLLER

CHARACTER GEN.

INTERRUPT

REQUEST

REFRESH BUFFER

R0
R1
R2
R3
R4
R5
SHIFT
CONTROL

ROW STB
COLUMN STB
CURSOR H/V STB

CURSOR/ROW/COLUMN

CURSOR CONTROL

PC0

ADDRESS
H&V

BLANKED

BLACK/WHITE

WS82C55A-5

WS
82C55A-5

WS82C55A-5

WS82C55A

FIGURE 23. BASIC FLOPPY DISC INTERFACE

FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5
PC7
PC6

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC1
PC0

MODE 0

(OUTPUT)

MODE 2

PC3

DATA STB
ACK (IN)

FLOPPY DISK

INTERRUPT

REQUEST

D0
D1
D2
D3
D4
D5
D6
D7

TRACK "0" SENSOR
SYNC READY
INDEX

DATA READY

ACK (OUT)

PC2

ENGAGE HEAD

FORWARD/REV.

READ ENABLE

WRITE ENABLE

DISC SELECT

ENABLE CRC

TEST

BUSY LT

CONTROLLER

AND DRIVE

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PC4
PC5
PC6

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC1
PC2

MODE 0

(OUTPUT)

MODE 1

PC3

STB
ACK

B LEVEL

INTERRUPT

REQUEST

R0
R1
R2
R3
R4
R5
R6
R7

START/STOP
LIMIT SENSOR (H/V)
OUT OF FLUID

STOP/GO

PC0

CHANGE TOOL

LEFT/RIGHT

UP/DOWN

HOR. STEP STROBE

VERT. STEP STROBE

SLEW/STEP

FLUID ENABLE

EMERGENCY STOP

PAPER

TAPE

READER

(INPUT)

MACHINE TOOL

MODE 0

(INPUT)

WS82C55A-5

WS82C55A

Absolute Maximum Ratings

= 25

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V

+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V
Operating Temperature Range

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0

C to 70

Thermal Resistance (Typical, Note 1)

PDIP Package . . . . . . . . . . . . . . . . . . .

C/W

N/A

Maximum Storage Temperature Range . . . . . . . . . .-65

C to 150

Maximum Junction Temperature

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

= 5.0V

10%; T

= 0

C to +70

C (

SYMBOL

PARAMETER

LIMITS

UNITS

TEST CONDITIONS

MIN

MAX

Logical One Input Voltage

2.0
2.2

Logical Zero Input Voltage

0.8

Logical One Output Voltage

3.0

-0.4

= -2.5mA,

= -100

Logical Zero Output Voltage

0.4

+2.5mA

Input Leakage Current

-1.0

+1.0

= V

or GND,

DIP Pins: 5, 6, 8, 9, 35, 36

I/O Pin Leakage Current

-10

+10

VO = V

or GND DIP Pins: 27 - 34

IBHH

Bus Hold High Current

-50

-400

VO = 3.0V. Ports A, B, C

IBHL

Bus Hold Low Current

400

VO = 1.0V. Port A ONLY

IDAR

Darlington Drive Current

-2.5

Note 2, 4

Ports A, B, C. Test Condition 3

ICCSB

Standby Power Supply Current

= 5.5V, V

= V

or GND. Output Open

ICCOP

Operating Power Supply Current

mA/MHz

= +25

C, V

= 5.0V, Typical (See Note 3)

NOTES:

2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current.

3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0

s I/O Read/Write cycle time = 1mA).

4. Tested as V

at -2.5mA.

Capacitance

= 25

SYMBOL

PARAMETER

TYPICAL

UNITS

TEST CONDITIONS

CIN

Input Capacitance

FREQ = 1MHz, All Measurements are
referenced to device GND

CI/O

I/O Capacitance

WS82C55A-5);

WS82C55A

WS82C55A

AC Electrical Specifications

= +5V

10%, GND = 0V; T

SYMBOL

PARAMETER

UNITS

TEST

CONDITIONS

MIN

MAX

READ TIMING

(1) tAR

Address Stable Before RD

(2) tRA

Address Stable After RD

(3) tRR

RD Pulse Width

250

(4) tRD

Data Valid From RD

200

(5) tDF

Data Float After RD

(6) tRV

Time Between RDs and/or WRs

300

WRITE TIMING

(7) tAW

Address Stable Before WR

(8) tWA

Address Stable After WR

(9) tWW

WR Pulse Width

100

(10) tDW

Data Valid to WR High

100

(11) tWD

Data Valid After WR High

OTHER TIMING

(12) tWB

WR = 1 to Output

350

(13) tIR

Peripheral Data Before RD

(14) tHR

Peripheral Data After RD

(15) tAK

ACK Pulse Width

200

(16) tST

STB Pulse Width

100

(17) tPS

Peripheral Data Before STB High

(18) tPH

Peripheral Data After STB High

(19) tAD

ACK = 0 to Output

175

(20) tKD

ACK = 1 to Output Float

250

(21) tWOB

WR = 1 to OBF = 0

150

(22) tAOB

ACK = 0 to OBF = 1

150

(23) tSIB

STB = 0 to IBF = 1

150

(24) tRIB

RD = 1 to IBF = 0

150

(25) tRIT

RD = 0 to INTR = 0

200

(26) tSIT

STB = 1 to INTR = 1

150

(27) tAIT

ACK = 1 to INTR = 1

150

(28) tWIT

WR = 0 to INTR = 0

200

(29) tRES

Reset Pulse Width

500

NOTE: Period of initial Reset pulse after power-on must be at least 50

sec. Subsequent Reset pulses may be 500ns minimum.

0 C

to 70 C

1,(Note)

WS82C55A

WS82C55A*5

WS-XX82C55A

MIN

MAX

150

120

300

100

350

200

100

175

250

150

200

150

200

500

FIGURE 28. MODE 1 (STROBED OUTPUT)

FIGURE 29. MODE 2 (BI-DIRECTIONAL)

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF

MASK

STB

OBF

MASK

ACK

WR)

Timing Waveforms

(Continued)

tWOB (21)

tWB (12)

tAK (15)

tAIT (27)

tAOB (22)

tWIT

OBF

INTR

ACK

OUTPUT

(28)

tWOB

tAOB

tAK

tAD (19)

tKD

tPH (18)

tPS (17)

tSIB

tST

OBF

INTR

ACK

IBF

STB

PERIPHERAL

BUS

tRIB (24)

DATA FROM

PERIPHERAL TO 82C55A

DATA FROM

82C55A TO PERIPHERAL

DATA FROM

82C55A TO CPU

DATA FROM

CPU TO 82C55A

(21)

(22)

(15)

(16)

(20)

(23)

(NOTE)

WS82C55A

AC Test Circuit

AC Testing Input, Output Waveforms

Burn-In Circuits

FIGURE 30. WRITE TIMING

FIGURE 31. READ TIMING

Timing Waveforms

(Continued)

DATA

A0-A1,

BUS

tWW (9)

tDW (10)

tWD (11)

tWA (8)

tAW (7)

DATA

A0-A1,

BUS

tRR (3)

tRA (2)

tAR (1)

VALID

(4) tRD

tDF (5)

HIGH IMPEDANCE

OUTPUT FROM

DEVICE UNDER

TEST

NOTE: Includes STRAY and JIG Capacitance

TEST
POINT

(SEE NOTE)

TEST CONDITION DEFINITION TABLE

TEST CONDITION

1.7V

523

Open

150pF

1.7k

50pF

1.5V

750

Open

50pF

INPUT

VIH + 0.4V

VIL - 0.4V

1.5V

VOH

VOL

OUTPUT

AC Testing: All AC Parameters tested as per test circuits. Input RISE and

FALL times are driven at 1ns/V.

DIP

NOTES:

1. V

= 5.5V

0.5V

2. VIH = 4.5V

10%

3. VIL = -0.2V to 0.4V
4. GND = 0V

GND

F10

F12

F13

F14

F15

F11

F12

F13

F14

F15

F11

F12

F13

F14

F15

F11

F12

F11

F10

WS82C55A-5

40L

WS82C55A

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the "MO Series Symbol List" in Section 2.2

of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and

are measured with the leads constrained to be per-

pendicular to datum

7. e

and e

are measured at the lead tips with the leads uncon-

strained. e

must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.

Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

-C-

-B-

INDEX

1 2 3

N/2

AREA

SEATING

BASE

PLANE

-C-

-A-

0.010 (0.25)

B S

E40.6

(JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.250

6.35

0.015

0.39

0.125

0.195

3.18

4.95

0.014

0.022

0.356

0.558

0.030

0.070

0.77

1.77

0.008

0.015

0.204

0.381

1.980

2.095

50.3

53.2

0.005

0.13

0.600

0.625

15.24

15.87

0.485

0.580

12.32

14.73

0.100 BSC

2.54 BSC

0.600 BSC

15.24 BSC

0.700

17.78

0.115

0.200

2.93

5.08

Rev. 0 12/93

WS82C55A

Plastic Leaded Chip Carrier Packages (PLCC)

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions

are not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allow-

able mold protrusion is 0.010 inch (0.25mm) per side. Dimen-
sions D1 and E1 include mold mismatch and are measured at
the extreme material condition at the body parting line.

4. To be measured at seating plane

contact point.

5. Centerline to be determined where center leads exit plastic body.

6. "N" is the number of terminal positions.

-C-

SEATING
PLANE

0.020 (0.51)

MIN

VIEW "A"

D2/E2

0.025 (0.64)
0.045 (1.14)

0.042 (1.07)
0.056 (1.42)

0.050 (1.27) TP

0.042 (1.07)
0.048 (1.22)

PIN (1) IDENTIFIER

0.020 (0.51) MAX

3 PLCS

0.026 (0.66)
0.032 (0.81)

0.045 (1.14)

MIN

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)

MIN

VIEW "A" TYP.

0.004 (0.10)

-C-

D2/E2

N44.65

(JEDEC MS-018AC ISSUE A)

44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

SYM-

BOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.165

0.180

4.20

4.57

0.090

0.120

2.29

3.04

0.685

0.695

17.40

17.65

0.650

0.656

16.51

16.66

0.291

0.319

7.40

8.10

4, 5

0.685

0.695

17.40

17.65

0.650

0.656

16.51

16.66

0.291

0.319

7.40

8.10

4, 5

Rev. 2 11/97

WS82C55A

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 82C55

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 82C55