WM2616
12-bit Serial Input Voltage Output DAC
Production Data June 1999, Rev1.0
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and conditions.
2616 master.doc June 17, 1999 14:13
1999 Wolfson Microelectronics Ltd
.
FEATURES
12-bit voltage output DAC
Single supply from 2.7V to 5.5V
DNL
0.5 LSB, INL
1.9 LSB
Very low power consumption (3V supply):
-
900
W, slow mode
-
2.1mW, fast mode
TMS320, (Q)SPI
TM
TM
, and Microwire
TM
TM
compatible serial
interface
Programmable settling time of 4
s or 12
s typical
High impedance reference input buffer
APPLICATIONS
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2616CD
0 to 70C
8-pin SOIC
WM2616ID
-40 to 85C
8-pin SOIC
DESCRIPTION
The WM2616 is a 12-bit voltage output, resistor string digital-to-
analogue converter that can be powered down under software
control. Power down reduces current consumption to 10nA.
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2616 is programmed with a 16-bit serial word
comprising 4 control bits and 12 data bits.
Excellent performance is delivered with a typical DNL of 0.5LSBs.
The settling time of the DAC is programmable to allow the designer
to optimize speed versus power dissipation. The output stage is
buffered by a x2 gain rail-to-rail amplifier, which features a Class
AB output stage.
The device is available in an 8-pin SOIC package. Commercial
temperature (0
to 70
C) and Industrial temperature (-40
to 85
C)
variants are supported.
BLOCK DIAGRAM
TYPICAL PERFORMANCE
(7) OUT
12-BIT
DAC
LATCH
REFIN(6)
POWER-ON
RESET
DIN (1)
SCLK (2)
FS (4)
(5)
AGND
VDD
(8)
POWERDOWN/
SPEED
CONTROL
2-BIT
CONTROL
LATCH
REFERENCE
INPUT BUFFER
WM2616
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
data
X1
X2
DAC
OUTPUT
BUFFER
NCS (3)
AVDD = DVDD = 5V, V
REF
= 2.048V, Speed = Fast mode, Load = 10k/100pF
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
DNL - LSB
WM2616
Production Data Rev 1.0
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
2
PIN CONFIGURATION
1
2
3
4
NCS
DIN
SCLK
AGND
REFIN
FS
VDD
OUT
5
6
7
8
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
DIN
Digital input
Serial data input.
2
SCLK
Digital input
Serial clock input.
3
NCS
Digital input
Chip select. This pin is active low.
4
FS
Digital input
Frame synchronisation for serial input data.
5
AGND
Supply
Analogue ground.
6
REFIN
Analogue input
Voltage reference input.
7
OUT
Analogue output
DAC analogue output
8
VDD
Supply
Positive power supply.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
CONDITION
MIN
MAX
Supply voltage, VDD to AGND
7V
Digital input voltage
-0.3V
VDD + 0.3V
Reference input voltage
-0.3V
VDD + 0.3V
Operating temperature range, T
A
WM2616CD
WM2616ID
0
C
-40
C
70
C
85
C
Storage temperature
-65
C
150
C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
260
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
VDD
2.7
5.5
V
High-level digital input voltage
V
IH
VDD = 2.7V to 5.5V
2
V
Low-level digital input voltage
V
IL
VDD = 2.7V to 5.5V
0.8
V
Reference voltage to REFIN
V
REF
See Note
VDD - 1.5
V
Load resistance
R
L
2
10
k
Load capacitance
C
L
100
pF
Serial clock rate
f
SCLK
20
MHz
WM2616CD
0
70
C
Operating free-air temperature
T
A
WM2616ID
-40
85
C
Note: Reference input voltages greater then VDD/2 will cause saturation for large DAC codes.
Production Data Rev 1.0
WM2616
WOLFSON MICROELECTRONICS LTD
Production Data
Rev 1.0 June 1999
3
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
12
bits
Integral non-linearity
INL
See Note 1
1.9
4
LSB
Differential non-linearity
DNL
See Note 2
0.5
1
LSB
Zero code error
ZCE
See Note 3
2
10
mV
Gain error
GE
See Note 4
0.1
0.6
% FSR
D.c. power supply rejection ratio
d.c. PSRR
See Note 5
0.5
mV/V
Zero code error temperature coefficient
See Note 6
10
ppm/
C
Gain error temperature coefficient
See Note 6
10
ppm/
C
DAC Output Specifications
Output voltage range
0
VDD - 0.1
V
Output load regulation
2k
to 10k
load
See Note 7
0.1
0.25
%
Power Supplies
No load, V
IH
= VDD, V
IL
= 0V
VDD = 5V,
V
REF
= 2.048V Slow
0.4
0.6
mA
VDD = 5V,
V
REF
= 2.048V Fast
0.9
1.35
mA
VDD = 3V,
V
REF
= 1.024V Slow
0.3
0.45
mA
Active supply current
I
DD
VDD = 3V,
V
REF
= 1.024V Fast
See Note 8
0.7
1.1
mA
Power down supply current
No load,
all digital inputs 0V or VDD
See Note 9
0.01
10
A
Dynamic DAC Specifications
Slew rate
DAC code 128 to 4095,
10%-90%
Slow
Fast
See Note 10
0.5
2.5
0.9
3.6
V/
s
V/
s
Settling time
DAC code 128 to 4095
Slow
Fast
See Note 11
12.0
4.0
s
s
Glitch energy
Code 2047 to 2048
10
nV-s
Signal to noise ratio
SNR
fs = 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
66
74
dB
Signal to noise and distortion ratio
SNRD
fs = 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
54
66
dB
Total harmonic distortion
THD
fs
= 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
-68
-56
dB
Spurious free dynamic range
SPFDR
fs
= 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
56
70
dB
WM2616
Production Data Rev 1.0
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
4
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference
Reference input resistance
R
REFIN
10
M
Reference input capacitance
C
REFIN
5
pF
Reference feedthrough
V
REF
= 1V
PP
at 1kHz
+ 1.024V dc, DAC code 0
-75
dB
Reference input bandwidth
V
REF
= 0.2V
PP
+ 1.024V dc
DAC code 2048
Slow
Fast
0.5
1.3
MHz
MHz
Digital Inputs
High level input current
I
IH
Input voltage = VDD
1
A
Low level input current
I
IL
Input voltage = 0V
-1
A
Input capacitance
C
I
3
pF
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero
code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A
guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code.
3.
Zero code error is the voltage output when the DAC input code is zero.
4.
Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5.
Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the
zero code error and the gain error.
6.
Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
7.
Output load regulation is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is expressed as a
percentage of the full scale output voltage with a 10k
load.
8.
I
DD
is measured while continuously writing code 2048 to the DAC. For V
IH
< VDD - 0.7V and V
IL
> 0.7V supply current will increase.
9.
Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits
are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f
OUT
generated with a sampling frequency fs
.
Production Data Rev 1.0
WM2616
WOLFSON MICROELECTRONICS LTD
Production Data
Rev 1.0 June 1999
5
SERIAL INTERFACE
t
SUC16FS
t
SUFS
SCLK
DIN
NCS
FS
1
2
3
4
5
15
16
D0
D1
D12
D13
D14
D15
t
WL
t
WH
t
SUD
t
HD
t
SUCSFS
t
WHFS
t
SUC16CS
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise).
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
SUCSFS
Setup time NCS low before negative FS edge.
10
ns
t
SUFS
Setup time FS low before first negative SCLK edge.
8
ns
t
SUC16FS
Setup time, sixteenth negative SCLK edge after FS low
on which D0 is sampled before rising edge of FS.
10
ns
t
SUC16CS
Setup time, sixteenth positive SCLK edge (first positive
after D0 sampled) before NCS rising edge. If FS is used
instead of the sixteenth positive edge to update the DAC,
then the setup time is between the FS rising edge and
the NCS rising edge.
10
ns
t
WH
Pulse duration, SCLK high.
25
ns
t
WL
Pulse duration, SCLK low.
25
ns
t
SUD
Setup time, data ready before SCLK falling edge.
8
ns
t
HD
Hold time, data held valid after SCLK falling edge.
5
ns
t
WHFS
Pulse duration, FS high.
20
ns
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