WM2619
12-bit Parallel Input Voltage Output DAC
Production Data, June 1999, Rev 1.0
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and conditions.
Masterrev1.0a.doc June 17, 1999 10:52
1999 Wolfson Microelectronics Ltd
.
FEATURES
12-bit voltage output DAC
Single supply 2.7V to 5.5V operation
DNL 0.4 LSB, INL 1.5 LSB
Settling time 1s typical
Low power consumption
-
8mW typical in slow mode - 5V supply
-
4.3mW typical in fast mode - 3V supply
Power down mode
APPLICATIONS
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2619CDT
0 to 70C
20-pin TSSOP
WM2619IDT
-40 to 85C
20-pin TSSOP
DESCRIPTION
The WM2619 is a 12-bit voltage output, resistor string, digital-to-
analogue converter. A hardware controlled power down mode is
provided that reduces power consumption to 50nW. In normal
operation the device dissipates 8mW at 5V or 4.3mW at 3V.
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs.
Excellent performance is delivered with a typical DNL of 0.4 LSBs
and a settling time of 1
s. The output stage is buffered by a x2
gain near rail-to-rail amplifier, which features a Class A output
stage. The 12 data bits are double-buffered enabling the output to
be asynchronously updated under hardware control.
The device is available in a 20-pin TSSOP package. Commercial
temperature (0 to 70C) and Industrial temperature (-40 to 85C)
variants are supported.
BLOCK DIAGRAM
TYPICAL PERFORMANCE
data
(13) OUT
REFIN(12)
POWER-ON
RESET
D[0-11]
(19,20, 1-10)
NWE (17)
(14)
GND
VDD
(11)
POWERDOWN
CONTROL
REFERENCE
INPUT BUFFER
WM2619
X1
X2
DAC
OUTPUT
BUFFER
NCS (18)
12-BIT
DAC
LATCH
12-BIT
INPUT
REGISTER
(15)
NPD
(16)
NLDAC
VDD = 5V, V
REF
= 2.048V, Load = 10k/100pF
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
DNL - LSB
WM2619
Production Data
WOLFSON MICROELECTRONICS LTD
Production Data
Rev 1.0 June 1999
2
PIN CONFIGURATION
9
10
D10
D11
12
11
REFIN
VDD
20
13
14
15
16
17
18
19
D1
GND
NPD
NLDAC
NWE
NCS
D0
OUT
8
1
2
3
4
5
6
7
D9
D3
D4
D5
D6
D7
D8
D2
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
D2
Digital input
Digital data input.
2
D3
Digital input
Digital data input.
3
D4
Digital input
Digital data input.
4
D5
Digital input
Digital data input.
5
D6
Digital input
Digital data input.
6
D7
Digital input
Digital data input.
7
D8
Digital input
Digital data input.
8
D9
Digital input
Digital data input
9
D10
Digital input
Digital data input.
10
D11
Digital input
Digital data input (MSB).
11
VDD
Supply
Positive power supply.
12
REFIN
Analogue input
Voltage reference input.
13
OUT
Analogue output
Analogue output.
14
GND
Ground
Ground.
15
NPD
Digital input
Power down. Powers down all DACs overriding their individual
power down settings and all output stages. This pin is active low.
16
NLDAC
Digital input
Load DAC. Digital input active low. NLDAC must be taken low to
update the DAC latch from the holding latches.
17
NWE
Digital input
Write enable (active low).
18
NCS
Digital input
Chip select (active low).
19
D0
Digital input
Parallel data input (LSB).
20
D1
Digital input
Parallel data input.
Production Data
WM2619
WOLFSON MICROELECTRONICS LTD
Production Data
Rev1.0 June 1999
3
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during
handling and storage of this device
CONDITION
MIN
MAX
Digital Supply voltage, VDD to GND
7V
Reference input voltage
-0.3V
VDD + 0.3V
Digital input voltages
-0.3V
VDD + 0.3V
Operating temperature range, T
A
WM2619C
WM2619I
0
C
-40
C
70
C
85
C
Storage temperature
-65
C
150
C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
260
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
VDD
2.7
5.5
V
High-level digital input voltage
V
IH
VDD = 2.7V to 5.5V
2
V
Low-level digital input voltage
V
IL
VDD = 2.7V to 5.5V
0.8
V
Reference voltage to REFIN
V
REF
See Note
VDD - 1.5
V
Load resistance
R
L
2
10
k
Load capacitance
C
L
100
pF
WM2619C
0
70
C
Operating free-air temperature
T
A
WM2619I
-40
85
C
Note: Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
WM2619
Production Data
WOLFSON MICROELECTRONICS LTD
Production Data
Rev 1.0 June 1999
4
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
12
bits
Integral non-linearity
INL
See Note 1
1.5
4
LSB
Differential non-linearity
DNL
See Note 2
0.4
1
LSB
Zero code error
ZCE
See Note 3
3
20
mV
Gain error
GE
See Note 4
0.25
0.5
% FSR
D.c. power supply rejection ratio
d.c. PSRR
See Note 5
0.5
mV/V
Zero code error temperature coefficient
See Note 6
3
ppm/
C
Gain error temperature coefficient
See Note 6
1
ppm/
C
DAC Output Specifications
Output voltage range
0
VDD - 0.4
V
Output load regulation
2k
to 10k
load
See Note 7
0.1
0.3
%
Power Supplies
Active supply current
I
DD
No load, V
IH
= VDD, V
IL
= 0V
VDD = 5V, V
REF
= 2.048V
VDD = 3V, V
REF
= 1.024V
See Note 8
1.6
1.4
3.0
2.7
mA
mA
Power down supply current
No load, all digital inputs
0V or VDD
See Note 9
0.01
10
A
Dynamic DAC Specifications
Slew rate
DAC code 128 to 4095,
10%-90%
See Note 10
8
V/
s
Settling time
DAC code 128 to 4095
See Note 11
1
s
Glitch energy
Code 2047 to 2048
5
nV-s
Signal to noise ratio
SNR
fs = 480ksps, f
OUT
= 1kHz,
BW = 20kHz, TA = 25
C
See Note 12
65
78
dB
Signal to noise and distortion ratio
SNRD
fs = 480ksps, f
OUT
= 1kHz,
BW = 20kHz, TA = 25
C
See Note 12
58
67
dB
Total harmonic distortion
THD
fs = 480ksps, f
OUT
= 1kHz,
BW = 20kHz, TA=25
C
See Note 12
-68
-60
dB
Spurious free dynamic range
SPFDR
fs = 480ksps, f
OUT
= 1kHz,
BW = 20kHz, TA = 25
C
See Note 12
60
72
dB
Reference
Reference input resistance
R
REFIN
10
M
Reference input capacitance
C
REFIN
5
pF
Reference feedthrough
V
REF
= 1V
PP
at 1kHz
+ 1.024Vdc, DAC code 0
-60
dB
Reference input bandwidth
V
REF
= 0.2V
PP
+ 1.024V d.c.
DAC code 2048
1.4
MHz
Production Data
WM2619
WOLFSON MICROELECTRONICS LTD
Production Data
Rev1.0 June 1999
5
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High level input current
I
IH
Input voltage = VDD
1
A
Low level input current
I
IL
Input voltage = 0V
-1
A
Input capacitance
C
I
8
pF
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in
digital input code.
3.
Zero code error is the voltage output when the DAC input code is zero.
4.
Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5.
Power supply rejection ratio is measured by varying V
DD
from 4.5V to 5.5V and measuring the proportion of this signal imposed on
the zero code error and the gain error.
6.
Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
7.
Output load regulation is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is expressed as
a percentage of the full scale output voltage with a 10k
load.
8.
I
DD
is measured while continuously writing code 2048 to the DAC. For V
IH
< V
DD
- 0.7V and V
IL
> 0.7V supply current will increase.
9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates.
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges.
Limits are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f
OUT
generated with a sampling frequency fs
.
WM2619
Production Data
WOLFSON MICROELECTRONICS LTD
Production Data
Rev 1.0 June 1999
6
SERIAL INTERFACE
NCS
NWE
NLDAC
D [0:11]
Data
X
X
t
SUCSWE
t
SUDWE
t
HD
t
WWE
t
WLD
t
SUWELD
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V
10%, V
REF
= 2.048V and VDD
= 3V
10%, V
REF
= 1.024V over recommended operating
free-air temperature range (unless noted otherwise)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
SUCSWE
Setup time NCS low before positive NWE edge
13
ns
t
SUDWE
Setup time data ready before positive NWE edge
9
ns
T
HD
Data hold after positive NWE edge
0
ns
t
SUWELD
Setup time NWE high before NLDAC low
0
ns
t
WWE
High pulse width of NWE
10
ns
t
WLD
Low pulse width of NLDAC
10
ns
Production Data
WM2619
WOLFSON MICROELECTRONICS LTD
Production Data
Rev1.0 June 1999
7
TYPICAL PERFORMANCE GRAPHS
VDD = 5V, V
REF
= 2.048V, Load = 10k/100pF
-3
-2
-1
0
1
2
3
0
512
1024
1536
2048
2559
3071
3583
4095
DIGITAL CODE
INL - LSB
Figure 2 Integral Non-Linearity
0
0.5
1
1.5
2
2.5
3
0
1
2
3
4
5
6
7
8
9
10
ISINK - mA
OUTPUT VOLTAGE - V
VDD = 3V, V
REF
= 1V, Input Code = 0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
6
7
8
9
10
ISINK - mA
OUTPUT VOLTAGE - V
VDD = 5V, V
REF
= 2V, Input Code = 0
Figure 3 Sink Current VDD = 3V
Figure 4 Sink Current VDD = 5V
2.025
2.03
2.035
2.04
2.045
2.05
2.055
2.06
2.065
0
1
2
3
4
5
6
7
8
9
10
ISOURCE - mA
OUTPUT VOLTAGE - V
VDD = 3V, V
REF
= 1V, Input Code = 4095
4.065
4.07
4.075
4.08
4.085
4.09
4.095
4.1
4.105
0
2
4
6
8
10
ISOURCE - mA
OUTPUT VOLTAGE - V
VDD = 5V, V
REF
= 2V, Input Code = 4095
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
WM2619
Production Data
WOLFSON MICROELECTRONICS LTD
Production Data
Rev 1.0 June 1999
8
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
Output voltage =
( )
4096
CODE
V
2
REF
INPUT
OUTPUT
1111
1111
1111
( )
4096
4095
V
2
REF
:
:
1000
0000
0001
( )
4096
2049
V
2
REF
1000
0000
0000
( )
REF
REF
V
4096
2048
V
2
=
0111
1111
1111
( )
4096
2047
V
2
REF
:
:
0000
0000
0001
( )
4096
1
V
2
REF
0000
0000
0000
0V
Table 1 Binary Code Table (0V to 2V
REFIN
Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2k
load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of
code. The REFIN pin has an input resistance of 10M
and an input capacitance of typically 5pF.
The reference voltage determines the DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
The WM2619 has two configuration options that are controlled by device pins.
DEVICE POWERDOWN
The device can be powered-down by pulling pin NPD (pin 15) high. This powers down the DAC.
This will reduce power consumption significantly. When the power down function is released the
device reverts to the DAC code set prior to power down.
DAC UPDATE
The NLDAC pin (Pin 16) can be held high to prevent serial word writes from updating the DAC
latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded
into the DAC latch.
PARALLEL INTERFACE
The device registers data on the positive edge of NWE (Pin 17). It must be enabled with NCS
(Pin 18) low.
Production Data
WM2619
WOLFSON MICROELECTRONICS LTD
Production Data
Rev1.0 June 1999
9
PACKAGE DIMENSIONS
c
L
GAUGE
PLANE
0.25
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
DM008.C
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)
Symbols
Dimensions
(mm)
MIN
NOM
MAX
A
-----
-----
1.20
A
1
0.05
-----
0.15
A
2
0.80
1.00
1.05
b
0.19
-----
0.30
c
0.09
-----
0.20
D
6.40
6.50
6.60
e
0.65 BSC
E
6.4 BSC
E
1
4.30
4.40
4.50
L
0.45
0.60
0.75
0
o
-----
8
o
REF:
JEDEC.95, MO-153
A
A2
A1
SEATING PLANE
-C-
0.05 C
11
20
E1
E
e
b
10
1
D
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