Document Outline
- WM2623
- Low Power 8-bit Serial Input DAC
- Production Data, October 2000, Rev 1.0
- FEATURES
- DESCRIPTION
- APPLICATIONS
- ORDERING INFORMATION
- BLOCK DIAGRAM
- TYPICAL PERFORMANCE
- PIN CONFIGURATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- SERIAL INTERFACE
- TYPICAL PERFORMANCE GRAPHS
- DEVICE DESCRIPTION
- GENERAL FUNCTION
- SERIAL INTERFACE
- SOFTWARE CONFIGURATION OPTIONS
- APPLICATIONS INFORMATION
- LINEARITY, OFFSET, AND GAIN ERROR
- POWER SUPPLY DECOUPLING AND GROUNDING
- PACKAGE DIMENSIONS
WM2623
Low Power 8-bit Serial Input DAC
Production Data, October 2000, Rev 1.0
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and Conditions.
2000 Wolfson Microelectronics Ltd
.
FEATURES
8-bit voltage output DAC
Single supply from 2.7V to 5.5V
Very low power consumption (3V supply):
-
900
W, slow mode
-
2.1mW, fast mode
-
3
W, standby mode
DNL
0.2 LSB, INL
0.5 LSB (max)
Monotonic over Temperature
DSP compatible serial interface
Programmable settling time of 3
s or 9
s typical
High impedance reference input buffer
APPLICATIONS
Digital Servo Control Loops
Industrial Process Control
Battery powered instruments and controls
Machine and motion control devices
Digital offset and gain adjustment
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2623CD
0 to 70C
8-pin SOIC
WM2623ID
-40 to 85C
8-pin SOIC
DESCRIPTION
The WM2623 is an 8-bit voltage output, resistor string digital-to-
analogue converter. It can operate with supply voltages
between 2.7V and 5.5V and can be powered down under
software control. Power down reduces current consumption to
less than 1
A.
The device has been designed for glueless interface to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2623 is programmed with a 16-bit serial word
including 4 control bits and 8 data bits.
Excellent performance is delivered with a typical DNL of
0.2LSBs. Monotonicity is guaranteed over the operating
temperature range. The settling time of the DAC is
programmable to allow for optimisation of speed versus power
dissipation. The output stage is buffered by a rail-to-rail amplifier
with a gain of two, which features a Class AB output stage.
The reference voltage input features a high impedance buffer
which eliminates the need to keep the reference source
impedance low.
The WM2623 is available in an 8-pin SOIC package.
Commercial (0
to 70
C) and Industrial (-40
to 85
C)
temperature range variants are available.
BLOCK DIAGRAM
TYPICAL PERFORMANCE
(7) OUT
8-BIT
DAC
LATCH
REF(6)
POWER-ON
RESET
DIN (1)
SCLK (2)
FS (4)
(5)
GND
VDD
(8)
POWERDOWN/
SPEED
CONTROL
2-BIT
CONTROL
LATCH
REFERENCE
INPUT BUFFER
WM2623
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
data
X1
X2
DAC
OUTPUT
BUFFER
CSB (3)
AVDD = DVDD = 5V, V
REF
= 2.048V, Speed = Fast Mode, Load = 10kOhm/100pF
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
0
32
64
96
128
160
192
224
256
DIGITAL CODE
DNL (
L
S
B
s
)
WM2623
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 October 2000
2
PIN CONFIGURATION
1
2
3
4
NCS
DIN
SCLK
GND
REF
FS
VDD
OUT
5
6
7
8
PIN DESCRIPTION
PIN NO
NAME
TYPE
DESCRIPTION
1
DIN
Digital input
Serial data input
2
SCLK
Digital input
Serial clock input
3
NCS
Digital input
Chip select. This pin is active low.
4
FS
Digital input
Frame synchronisation for serial input data
5
GND
Supply
Ground
6
REF
Analogue input
Voltage reference input
7
OUT
Analogue output
DAC analogue output
8
VDD
Supply
Positive power supply
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
MAX
Supply voltage, VDD to GND
7V
Digital input voltage
-0.3V
VDD + 0.3V
Reference input voltage
-0.3V
VDD + 0.3V
Operating temperature range, T
A
WM2623CD
WM2623ID
0
C
-40
C
70
C
85
C
Storage temperature
-65
C
150
C
Lead temperature 1.6mm (1/16 inch) from package body for 10 seconds
260
C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
VDD
2.7
5.5
V
High-level digital input voltage
V
IH
VDD = 2.7V to 5.5V
2
V
Low-level digital input voltage
V
IL
VDD = 2.7V to 5.5V
0.8
V
Reference voltage to REF pin
V
REF
See Note
AGND
VDD - 1.5
V
Load resistance
R
L
2
10
k
Load capacitance
C
L
100
pF
Serial clock frequency
f
SCLK
20
MHz
WM2623CD
0
70
C
Operating free-air temperature
T
A
WM2623ID
-40
85
C
Note:
Reference input voltages greater than VDD/2 will cause clipping for large DAC codes.
Production Data
WM2623
WOLFSON MICROELECTRONICS LTD
PD
Rev 1.0 October 2000
3
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V 10%, V
REF
= 2.048V and VDD
= 3V 10%, V
REF
= 1.024V over recommended operating free-
air temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
8
bits
Integral non-linearity
INL
See Note 1
0.3
0.5
LSB
Differential non-linearity
DNL
See Note 2
0.07
0.2
LSB
Zero code error
ZCE
See Note 3
10
mV
Gain error
GE
See Note 4
0.6
% FSR
D.C. power supply rejection ratio
PSRR
See Note 5
%'
dB
Zero code error temperature coefficient
See Note 6
10
ppm/
C
Gain error temperature coefficient
See Note 6
10
ppm/
C
DAC Output Specifications
Output voltage range
0
VDD - 0.1
V
Output load regulation
2k
to 10k
load
See Note 7
0.1
0.25
% FS
Power Supplies
No load, DAC value = 128,
all digital inputs 0V or VDD
VDD = 5V, V
REF
= 2.048V
Slow Mode
0.4
0.6
mA
VDD = 5V, V
REF
= 2.048V
Fast Mode
0.9
1.35
mA
VDD = 3V, V
REF
= 1.024V,
Slow Mode
0.3
0.45
mA
Active supply current
VDD = 3V, V
REF
= 1.024V,
Fast Mode (See Note 8)
0.7
1.1
mA
Power down supply current
I
DD
1
A
Dynamic DAC Specifications
Slew rate
SR
DAC output 10%-90%
Slow
Fast
See Note 9
0.9
3.6
V/
s
V/
s
Settling time
t
s
DAC output 10%-90%
Slow
Fast
See Note 10
9
3
20
5.5
s
s
Glitch energy
DAC Code 127 to 128
10
nV-s
Signal to noise ratio
SNR
57
dB
Signal to noise and distortion ratio
SNRD
49
dB
Total harmonic distortion
THD
$
dB
Spurious free dynamic range
SPFDR
f
s
= 400kSPS,
f
OUT
= 1.1kHz,
BW = 20kHz
See Note 11
60
dB
Reference
Reference input resistance
R
REFIN
10
M
Reference input capacitance
C
REFIN
5
pF
Reference feedthrough
V
REF
= 1V
PP
at 1kHz
+ 1.024V dc, DAC code 0
-75
dB
Reference input bandwidth
V
REF
= 0.2V
PP
+ 1.024V dc
DAC code 128
Slow
Fast
0.525
1.3
MHz
MHz
WM2623
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 October 2000
4
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V 10%, V
REF
= 2.048V and VDD
= 3V 10%, V
REF
= 1.024V over recommended operating free-
air temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High level input current
I
IH
Input voltage = VDD
1
A
Low level input current
I
IL
Input voltage = 0V
A
Input capacitance
C
I
3
pF
Notes:
1.
Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).
2.
Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as
the digital input code.
3.
Zero code error is the voltage output when the DAC input code is zero.
4.
Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5.
Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
6.
Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
7.
Output load regulation is the difference between the output voltage at full scale with a 10k
load and 2k
load. It is
expressed as a percentage of the full scale output voltage with a 10k
load.
8.
I
DD
is measured while continuously writing code 128 to the DAC. For V
IH
< VDD - 0.7V and V
IL
> 0.7V supply current will
increase.
9.
Slew rate results are for the lower value of the rising and falling edge slew rates
10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
11. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f
OUT
generated with a sampling
frequency fs
.
Production Data
WM2623
WOLFSON MICROELECTRONICS LTD
PD
Rev 1.0 October 2000
5
SERIAL INTERFACE
NCS
FS
SCLK
DIN
1
2
3
4
5 15
16
D0
D1
D12
D13
D14
D15
t
WL
t
WH
t
SUD
t
HD
t
SUCSFS
t
SUC16CS
t
WHFS
t
SUFSCLK
t
SUC16FS
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10k
, C
L
= 100pF. VDD
= 5V 10%, V
REF
= 2.048V and VDD
= 3V 10%, V
REF
= 1.024V over recommended operating
free-air temperature range (unless noted otherwise).
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
SUCSFS
Setup time NCS low before falling FS edge.
10
ns
t
SUFS
Setup time FS low before first falling SCLK edge.
8
ns
t
SUC16FS
Setup time, 16
th
falling SCLK edge after FS low on
which data bit D0 is sampled before rising edge of FS.
10
ns
t
SUC16CS
Setup time, 16
th
rising SCLK edge (first after data bit
D0 sampled) before NCS rising edge. If FS is used
instead of the 16
th
rising edge to update the DAC, this
setup time is between the FS rising edge and the NCS
rising edge.
10
ns
t
WH
Pulse duration, SCLK high.
25
ns
t
WL
Pulse duration, SCLK low.
25
ns
t
SUD
Setup time, data ready before SCLK falling edge.
8
ns
t
HD
Hold time, data held valid after SCLK falling edge.
5
ns
t
WHFS
Pulse duration, FS high.
20
ns
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