WM2626

Low Power Dual 8-bit Serial Input DAC

with Internal Reference

Production Data, Rev. 1.0, April 2001

WOLFSON MICROELECTRONICS LTD

Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
www.wolfsonmicro.com

Production Data Datasheets contain final

specifications current on publication date.

Supply of products conforms to Wolfson

Microelectronics' Terms and conditions.

2001 Wolfson Microelectronics Ltd

FEATURES

Dual 8-bit voltage output DAC

Single supply from 2.7V to 5.5V

Low power consumption:
-

1.7mW typical (3V supply, slow mode)

3.7mW typical (3V supply, fast mode)

DNL

0.1 LSB, INL

0.4 LSB (typical)

Monotonic over temperature

Microprocessor and DSP compatible serial interface

Programmable settling time of 0.8

s or 2.8

s typical

High impedance reference input buffer

APPLICATIONS

Digital servo control loops

Industrial process control

Battery powered instruments and controls

Machine and motion control devices

Digital offset and gain adjustment

ORDERING INFORMATION

DEVICE

TEMP. RANGE

PACKAGE

WM2626CD

0° to 70°C

8-pin SOIC

WM2626ID

-40° to 85°C

8-pin SOIC

DESCRIPTION

The WM2626 is a dual 8-bit voltage output, resistor string
digital-to-analogue converter. It can operate with supply
voltages between 2.7V and 5.5V and can be powered down
under software control. Power down reduces current
consumption to 1

The device has been designed for glueless interface to industry
standard microprocessors and DSPs. It is programmed with a
16-bit serial word including 4 control bits and 8 data bits.

Excellent performance is delivered with a typical DNL of
0.2LSBs. Monotonicity is guaranteed over the operating
temperature range. The settling time of the DAC is
programmable to allow for optimisation of speed versus power
dissipation. The analogue output is buffered by a rail-to-rail
amplifier with a gain of two and a Class AB output stage.

The on-chip voltage reference is available to external circuitry
through the REF pin. It is buffered and can supply up to 1mA.
Alternatively, an external reference can be used. A high
impedance reference input buffer eliminates the need to keep
the reference source impedance low.

The WM2626 is available in an 8-pin SOIC package.
Commercial (0

to 70

C) and Industrial (-40

to 85

temperature range variants are available.

BLOCK DIAGRAM

TYPICAL PERFORMANCE

WM2626

SERIAL

INTERFACE

AND

CONTROL

LOGIC

POWER-

DOWN AND

SPEED

CONTROL

REF

DIN

SCLK

NCS

OUTA

OUTB

DAC

x1/x2

1.024V

REF

GND

VDD

VDD = 5V, Slow Mode, V

REF

= 2.048V external

-0.04

-0.03

-0.02

-0.01

0.01

0.02

0.03

0.04

128

160

192

224

256

DIGITAL CODE

f
f
e

r
e

i
a

l
Non-

near

i
t
y (

SBs)

WM2626

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

PIN CONFIGURATION

NCS

DIN

SCLK

GND

REF

OUTA

VDD

OUTB

PIN DESCRIPTION

PIN NO

NAME

TYPE

DESCRIPTION

DIN

Digital input

Serial data input

SCLK

Digital input

Serial clock input

NCS

Digital input

Chip select. This pin is active low.

OUTA

Digital input

DAC A analogue voltage output

GND

Supply

Ground

REF

Analogue in/out

Voltage reference

OUT

Analogue output

DAC B analogue voltage output

VDD

Supply

Positive power supply

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.

CONDITION

MIN

MAX

Supply voltage, VDD to GND

Digital input voltage

-0.3V

VDD + 0.3V

Reference input voltage

-0.3V

VDD + 0.3V

Operating temperature range, T

WM2626CD

WM2626ID

-40

Storage temperature

-65

150

Soldering lead temperature, 1.6mm (1/16 inch) from package body for
10 seconds

260

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply voltage

VDD

2.7

5.5

High-level digital input voltage

VDD = 2.7V to 5.5V

Low-level digital input voltage

VDD = 2.7V to 5.5V

0.8

Reference voltage to REF pin

REF

See Note

GND

VDD - 1.5

Load resistance

Load capacitance

100

Serial clock frequency

SCLK

MHz

WM2626CD

°C

Operating free-air temperature

WM2626ID

-40

°C

Note: Reference input voltages greater than VDD/2 will cause clipping for large DAC codes.

Production Data

WM2626

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

ELECTRICAL CHARACTERISTICS

Test Conditions:
R

= 10k

, C

= 100pF. VDD

= 5V ±10%, V

REF

= 2.048V and VDD

= 3V ±10%, V

REF

= 1.024V over recommended operating free-

air temperature range (unless noted otherwise).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Static DAC Specifications

Resolution

bits

Integral non-linearity

INL

End point adjusted

See Note 1

±0.4

LSB

Differential non-linearity

DNL

See Note 2

0.1

0.5

LSB

Zero code error

ZCE

See Note 3

Gain error

See Note 4

0.6

% FSR

D.C. power supply rejection ratio

D.C. PSRR

See Note 5

Zero code error temperature coefficient

See Note 6

ppm/

Gain error temperature coefficient

See Note 6

ppm/

DAC Output Specifications

Output voltage range

VDD - 0.4

Output load regulation

to 10k

load

See Note 7

0.25

% FS

Power Supplies

No load, DAC value = 128,
all digital inputs 0V or VDD

Fast

4.2

VDD=5V

Slow

3.6

Fast

3.7

6.3

Internal

Reference

VDD=3V

Slow

1.7

3.0

Fast

3.8

6.3

VDD=5V

Slow

1.7

3.0

Fast

3.4

5.7

Active supply current

External

Reference

VDD=3V

Slow

1.4

2.6

Power down supply current

Dynamic DAC Specifications

Slew rate

= 10k

, C

= 100pF

Slow

Fast

See Note 9

1.8

Settling time

= 10k

, C

= 100pF

Slow

Fast

See Note 10

2.8
0.8

5.5
2.4

Glitch energy

DIN = 0 to 1, f

CLK

= 100kHz,

NCS = VDD

nV-s

Signal to noise ratio

SNR

Signal to noise and distortion ratio

SINAD

Total harmonic distortion

THD

-50

-48

Spurious free dynamic range

SFDR

= 480kSPS,

OUT

= 1kHz,

= 10k

, C

= 100pF

See Note 11

WM2626

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

Test Conditions:
R

= 10k

, C

= 100pF. VDD

= 5V ±10%, V

REF

= 2.048V and VDD

= 3V ±10%, V

REF

= 1.024V over recommended operating free-

air temperature range (unless noted otherwise).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference Output (Internal reference)

Low reference voltage

REFL

1.003

1.024

1.045

High reference voltage

REFH

2.027

2.048

2.069

Output Current

REF

±1

Load capacitance

100

Reference Input (External reference)

Reference input resistance

REFIN

Reference input capacitance

REFIN

Reference feedthrough

REF

= 1V

at 1kHz

+ 1.024V dc, DAC code 0

-80

Reference input bandwidth

REF

= 0.2V

+ 1.024V dc

DAC code 128

Slow

Fast

0.525

1.3

MHz
MHz

Digital Inputs

High level input current

Input voltage = VDD

Low level input current

Input voltage = 0V

-1

Input capacitance

Notes:

Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).

Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as
the digital input code.

Zero code error is the voltage output when the DAC input code is zero.

Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.

Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.

Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.

Output load regulation is the difference between the output voltage at full scale with a 10k

load and 2k

load. It is

expressed as a percentage of the full scale output voltage with a 10k

load.

is measured while continuously writing code 128 to the DAC. For V

< VDD - 0.7V and V

> 0.7V supply current will

increase.

Slew rate is for an output change from 10% to 90% of full-scale output voltage, or vice versa. The results are for the lower
value of the rising and falling edge slew rates.

10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling

edges. Limits are ensured by design and characterisation, but are not production tested.

11. SNR, SNRD, THD and SPFDR are measured on a synthesised sine wave at frequency f

OUT

generated with a sampling

frequency f

Production Data

WM2626

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

SERIAL INTERFACE

NCS

SCLK

DIN

5 15

D12

D13

D14

D15

SUD

SUCSCK

SUC16CS

Figure 1 Timing Diagram

Test Conditions:
R

= 10k

, C

= 100pF. VDD

= 5V

10%, V

REF

= 2.048V and VDD

= 3V

10%, V

REF

= 1.024V over recommended operating

free-air temperature range (unless noted otherwise).

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUCSCK

Setup time, NCS low before first falling SCLK edge

SUC16CS

Setup time, 16

falling SCLK edge (when data bit D0

is sampled) before NCS rising edge.

Pulse duration, SCLK high.

Pulse duration, SCLK low.

SUD

Setup time, data ready before SCLK falling edge.

Hold time, data held valid after SCLK falling edge.

WM2626

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

TYPICAL PERFORMANCE GRAPHS

VDD = 5V, Slow Mode, V

REF

= 2.048 external

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

128

160

192

224

256

DIGITAL CODE

t
e

r
al N

-
L

i
n

ear

y (

Figure 2 Integral Non-Linearity

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

ISINK - mA

LTA

Slow

Fast

VDD = 3V, V

REF

= 1V, Input Code = 0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

ISINK - mA

LTA

Slow

Fast

VDD = 5V, V

REF

= 2V, Input Code = 0

Figure 3 Sink Current VDD = 3V

Figure 4 Sink Current VDD = 5V

2.025

2.03

2.035

2.04

2.045

2.05

2.055

2.06

ISOURCE - mA

LTA

Slow

Fast

VDD = 3V, V

REF

= 1V, Input Code = 4095

4.065

4.07

4.075

4.08

4.085

4.09

4.095

4.1

ISOURCE - mA

LTA

Slow

Fast

VDD = 5V, V

REF

= 2V, Input Code = 4095

Figure 5 Source Current VDD = 3V

Figure 6 Source Current VDD = 5V

Production Data

WM2626

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

DEVICE DESCRIPTION

GENERAL FUNCTION

The WM2626 is a dual 8-bit, voltage output DAC with an on-chip voltage reference. It uses a
resistor string network buffered with an op amp to convert 8-bit digital data to analogue voltage
levels (see Block Diagram). The output voltage is determined by the reference voltage and the
input code according to the following relationship:

( )

256

CODE

out

REFIN

INPUT

OUTPUT

1111

( )

256

255

REF

1000

0001

( )

256

129

REF

1000

0000

( )

REF

256

128

0111

1111

( )

256

127

REF

0000

0001

( )

256

REF

0000

Table 1 Binary Code Table (0V to 2V

REF

Output), Gain = 2

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2k

load with a 100pF load capacitance.

SERIAL INTERFACE

Before writing any data to the WM2626, the interface must be enabled by setting NCS to low.
Incoming data on DIN (starting with the MSB) is then shifted bit-per-bit into the internal register on
the falling edges of SCLK. From there data is loaded into the target latch after 16 bits have been
transferred, or when NCS rises. Four internal latches can be addressed: DAC A, DAC B, the buffer
latch or the control register. Their function is explained below (see `Register Addressing').

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

MHz

SCLK

min

max

Since a data word contains 16 bits, the sample rate for one channel is limited to

(

)

MHz

min

max

For full two-channel operation, where two data words need to be transmitted per sample, this figure
is halved to 625kHz. However, the DAC settling time to 8-bit accuracy limits the response time of
the analogue output for large input step transitions.

WM2626

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

SOFTWARE CONFIGURATION OPTIONS

Table 2 shows the composition of a 16-bit data word. D11-D4 contains the 8-bit data word, and
D14-D13 hold the programmable options. Bits D15 and D12 are used for addressing the different
latches. D3 to D0 are unused and should be set to ZERO.

D15

D14

D13

D12

D11

D10

SPD PWR

New DAC value (8 bits)

Table 2 Register Map

PROGRAMMABLE CONVERTER SPEED

SPD (Bit 14) allows for software control of the converter speed. A ONE selects the fast mode,
where typical settling time to within

0.5LSB of the final value is 0.8

s. a ZERO puts the device into

the slow mode, where typical settling time is 2.8

PROGRAMMABLE POWER DOWN

The power down function is controlled by PWR (Bit 13). A ZERO configures the device as active,
or fully powered up, a ONE configures the device into power down mode. When the power down
function is released the device reverts to the DAC code set prior to power down.

REGISTER ADDRESSING

Data received on the serial interface is routed according to the values of bits R1 and R0, as shown
in Table 3.

(BIT D15)

(BIT D12)

REGISTER

Write data to DAC B and buffer

Write data to buffer

Write data to DAC A and update DAC B with buffer content

Write data to control register

Table 3 Latch Addressing

To update both DACs simultaneously, the data intended for DAC B should first be stored in the
buffer. Subsequently, writing data to DAC A will automatically update the DAC B latch from the
buffer, so that the analogue output of both DACs will change at the same time.

When updating the two channels independently, all data written to the DAC B latch (R1 and R0 set
to ZERO) is also copied to the buffer. Thus the automatic update of DAC B when writing to DAC A
latch (R1=1, R0=0) does not change the DAC B data. Data should not be written only to the buffer
when operating in this mode.

The contents of the control register, shown below in Table 4, are used to program the internal
reference function.

D11

D10

REF1 REF0

Table 4 Control Register Contents

PROGRAMMABLE INTERNAL OR EXTERNAL REFERENCE

The reference can be sourced internally or externally under software control, as detailed in Table 5.
If an external reference voltage is applied to the REF pin, the device must be configured to accept
this. This will activate the reference input buffer, whose input resistance of 10M

(typical) makes

the reference input resistance independent of code.

REF1

REF0

FUNCTION

Use external reference

Use internal 1.024V reference

Use internal 2.048V reference

Use external reference

Table 5 Programmable Internal Reference

When using the on-chip reference, voltages of 1.024V or 2.048V are available. The internal
reference can source up to 1mA on the REF pin and can therefore be used as a system reference
for external components.

Production Data

WM2626

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

EXAMPLES OF OPERATION

Simultaneous operation, slow mode:

1. Write data for DAC B to buffer

D15

D14

D13

D12

D11

D10

New DAC B value

2. Write new DAC A value and update DAC B from buffer simultaneously

D15

D14

D13

D12

D11

D10

New DAC A value

Independent operation, fast mode:

Set DAC B output (fast mode):

D15

D14

D13

D12

D11

D10

New DAC B value

Set DAC A output (fast mode):

D15

D14

D13

D12

D11

D10

New DAC A value

Select internal 2.048V reference:

D15

D14

D13

D12

D11

D10

Select external reference:

D15

D14

D13

D12

D11

D10

WM2626

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

APPLICATIONS INFORMATION

LINEARITY, OFFSET, AND GAIN ERROR

Amplifiers operating from a single supply can have positive or negative voltage offsets. With a
positive offset, the output voltage changes on the first code transition. However, if the offset is
negative, the output voltage may not change with the first code, depending on the magnitude of the
offset voltage. This is because with the most negative supply rail being ground, any attempt to
drive the output amplifier below ground will clamp the output at 0 V. The output voltage then
remains at zero until the input code is sufficiently high to overcome the negative offset voltage,
resulting in the transfer function shown in Figure 7

DAC code

Negative

Offset

Output

Voltage

0 V

Figure 7 Effect of Negative Offset

This offset error, not the linearity error, produces the breakpoint. The transfer function would follow
the dotted line if the output buffer could drive below the ground rail.

DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all
inputs at 1), disregarding offset and full-scale errors. However, due to the breakpoint in the transfer
function, single supply operation does not allow for adjustment when the offset is negative. In such
cases, the linearity is therefore measured between full-scale and the lowest code that produces a
positive (non-zero) output voltage.

POWER SUPPLY DECOUPLING AND GROUNDING

Printed circuit boards with separate analogue and digital ground planes deliver the best system
performance. The two ground planes should be connected together at the low impedance power
supply source. Ground currents should be managed so as to minimise voltage drops across the
ground planes.

A 0.1

F decoupling capacitor should be connected between the positive supply and ground pins of

the DAC, with short leads as close as possible to the device. Use of ferrite beads may further
isolate the system analogue supply from the digital supply.

Production Data

WM2626

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

PACKAGE DIMENSIONS

DM009.B

D: 8 PIN SOIC 3.9mm Wide Body

Symbols

Dimensions

(mm)

Dimensions

(Inches)

MIN

MAX

MIN

MAX

1.35

1.75

0.0532

0.0688

0.10

0.25

0.0040

0.0098

0.33

0.51

0.0130

0.0200

0.19

0.25

0.0075

0.0098

4.80

5.00

0.1890

0.1968

1.27 BSC

0.050 BSC

3.80

4.00

0.1497

0.1574

0.25

0.50

0.0099

0.0196

5.80

6.20

0.2284

0.2440

0.40

1.27

0.0160

0.0500

REF:

JEDEC.95, MS-012

NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).
D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

h x 45

SEATING PLANE

-C-

0.10 (0.004)

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WM2626ID

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: WM2626ID