Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176
email: admin@wolfson.co.uk
www: http://www.wolfson.co.uk
Wolfson Microelectronics
1997 Wolfson Microelectronics
WM8144-10
Production Data
October 1997 Rev. 3.0
Integrated 10-bit Data Acquisition system for
Imaging Applications
Description
WM8144-10 integrates the analogue signal conditioning
required by CCD sensors with a 10-bit ADC and optional
pixel-by-pixel image compensation. WM8144-10 requires
minimal external circuitry and provides a cost effective
sensor-to-digital domain system solution.
Each analogue conditioning channel provides reset level
clamp, CDS, fine offset level shifting and gain
amplification. The three channels are multiplexed into the
ADC. Output from the ADC can either be direct or passed
through a digital post-processing function. The post-
processing provides compensation for variations in offset
and shading on a pixel-by-pixel basis.
The flexible output architecture allows ten-bit data to be
accessed either on a ten-bit bus or via a time-multiplexed
eight-bit bus. The WM8144-10 can be configured for pixel-
by-pixel or line-by-line multiplexing operation. Reset level
clamp and/or CDS features can be optionally bypassed.
Device configuration is either by a simple serial or eight-
bit parallel interface.
Features
Block Diagram
Reset level clamp
Correlated Double Sampling (CDS)
Fine offset level shifting
Programmable Gain Amplification
10-Bit ADC with maximum 6 MSPS
Digital post-processing for pixel-by-pixel
image compensation
Simple clocking scheme
Control by serial or parallel interface
Time-multiplexed eight-bit data output mode
48 pin TQFP package
Pin compatible with WM8144-12
Applications
Document scanners
CCD sensor interfaces
Contact image sensor (CIS) interfaces
Production Data data sheets contain fi-
nal specifications current on publication
date. Supply of products conforms to
Wolfson Microelectronics standard terms
and conditions
VSMP
MCLK
RLC
10 BIT
ADC
IMAGE
COMPENSATION
PROCESSING
EXTERNAL
DATA STORE
INTERFACE
10/8
MUX
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
V
RU
V
RT
V
RB
MUX
M
U
X
V
RL
V
MID
V
MID
OP[9:0]
ORNG
CDATA(7:0)
DV
CC[2:0]
SDI / DNA
PNS
SCK / RNW
SEN / STB
OEB
V
RLC
A
VDD
A
GND
D
VDD1
D
VDD2
D
GND
TIMING CONTROL
NRESET
S/H
RINP
CDS
CDS
CDS
S/H
S/H
GINP
S/H
S/H
BINP
S/H
WM8144-10
VS
RS
CL
8-BIT + SIGN
DAC
OFFSET
OFFSET
OFFSET
PGA
5-BIT REG
V
MID
8-BIT + SIGN
DAC
PGA
5-BIT REG
V
MID
8-BIT + SIGN
DAC
PGA
5-BIT REG
V
MID
WM8144-10
Wolfson Microelectronics
2
Ordering Information
Package Outline
Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Supply Voltage
4.75
5.25
V
Operating Temperature Range
T
A
0
70
o
C
Input Common Mode Range
V
CMR
0.5
4.5
V
NC - Make no external connection
DEVICE
TEMP RANGE
PACKAGE
WM8144-10CFT/V 0
0
C - 70
0
C
48 Pin TQFP
Absolute Maximum Ratings
Analogue Supply Voltage. . . AGND - 0.3 V, AGND +7 V
Digital Supply Voltage. . . . DGND - 0.3 V, DGND +7 V
Digital Inputs . . . . . . . . DGND - 0.3 V, DVDD + 0.3 V
Digital Outputs. . . . . . . .DGND - 0.3 V, DVDD + 0.3 V
Reference inputs . . . . . . AGND - 0.3 V, AVDD + 0.3 V
RINP, GINP, BINP . . . . . .AGND - 0.3 V, AVDD + 0.3 V
Operating temperature range, T
A
. . . . . 0oC to +70oC
Storage Temperature . . . . . . . . . . -50oC to +150oC
Lead Temperature (soldering, 10 sec) . . . . . . +260oC
Note:
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by
continuously operating at or beyond these limits. Device functional operating range limits and guaranteed
performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. The WM8144-10 is manufactured on a CMOS process. It is therefore generically sus-
ceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and
storage of this device.
As per JEDEC specifications A112-A and A113-A this product requires specific storage conditions prior to
surface mount assembly. It has been classified as having a Moisture Sensitivity level of 2 and as such will be
supplied in vacuum sealed moisture barrier bags.
24
23
16
17
18
19
20
21
22
13
14
15
37
47
46
45
44
43
42
41
40
39
38
48
1
9
8
7
6
5
4
3
2
12
11
10
25
31
30
29
28
27
26
36
35
34
33
32
PNS
AGND
GINP
VRLC
VMID
BINP
RINP
VRU
VRT
V R B
V R L
A V D D
OP2
DV
NC
NC
DVDD2
OP0
OP1
CC2
CC1
CC0
ORNG
NRESET
OP3
OP8
OP7
OP6
OP5
OP4
C D A T A 3
C D A T A 2
C D A T A 1
C D A T A 0
DGND
OP9
CDATA4
DVDD1
VSMP
MCLK
CDATA7
CDATA6
CDATA5
OEB
SEN/STB
SDI/DNA
SCK/RNW
RLC
WM8144-10
WM8144-10
Wolfson Microelectronics
3
Electrical Characteristics
V
DD
= 4.75V to 5.25V, GND = 0 V, ........T
A
= 0oC to +70oC, MLCK = 12MHz unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Supply Current - Active
110.0
150
mA
Supply Current - Standby
10.0
15
mA
Digital Inputs
High Level Input Voltage
V
IH
0.8*DVDD
V
Low Level Input Voltage
V
IL
0.2*DVDD
V
High Level Input Current
I
IH
1.0
A
Low Level Input Current
I
IL
1.0
A
Input Capacitance
10.0
pF
Digital Outputs
High Level Output Voltage
V
OH
I
OH
= 1.0mA
DVDD-0.75
V
Voltage output range V
OL
I
OL
= 1.0mA
DGND+0.75
V
High Impedance Output Current
I
OZ
1.0
A
Input Multiplexer
Channel to Channel Gain Matching
0.5
%
Input Video Set-up Time
tVSU
10
ns
Input Video Hold Time
tVH
25
ns
Reset Video Set-up Time
tRSU CDS Mode only
10
ns
Reset Video Hold Time
tRH
CDS Mode only
25
ns
Reference String
Reference Voltage - Top
V
RT
V
RU
= 5.00 V, V
RL
= 0.00V
3.465
3.5
3.535
V
Reference Voltage - Bottom
V
RB
V
RU
= 5.00 V, V
RL
= 0.00V
1.465
1.5
1.535
V
DAC Reference Voltage
V
MID
V
RU
= 5.00 V, V
RL
= 0.00V
2.475
2.5
2.525
V
R.L.C. Switch Impedence
200
Ohms
Reset Level Clamp Options
V
RLC
V
RU
= 5.00 V, V
RL
= 0.00V
1.425
1.5
1.575
V
Voltage set by user
2.375
2.5
2.625
V
configuration - Table 7
3.325
3.5
3.675
V
Impedance V
RT
to V
RB
490
700
910 Ohms
Impedance V
RU
to V
RL
1190
1700
2210 Ohms
8-bit DACs
Resolution
8
Bits
Zero Code Voltage V
DAC
-10
V
DAC
+10
mV
Full Scale Voltage Error
0
10
mV
Differential Non Linearity
DNL
0.1
1 LSB
Integral Non Linearity
INL
0.4
1 LSB
WM8144-10
Wolfson Microelectronics
4
Electrical Characteristics (Contd.)
V
DD
= 4.75V to 5.25V, GND = 0 V, ........T
A
= 0oC to +70oC, MLCK = 12MHz unless otherwise stated.
Note 1: Guaranteed monotonic up to PGA Gain code 0Fh
Note 2: Guaranteed monotonic up to PGA Gain code 1Fh
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
10-Bit ADC
Resolution
V
DD
= 5V
10
Bits
Maximum Sampling Rate
V
DD
= 5V
6
MSPS
Full Scale Transition Error Voltage at
VINP
DAC Code = 000H, V
DD
=5V,
measured relative to VRT
+/-50
+/-200
mV
Zero Scale Transition Error Voltage at
VINP
DAC Code = 000H, V
DD
=5V,
measured relative to VRB
+/-50
+/-200
mV
Differential Non Linearity
DNL
V
DD
= 5V
-1
+1.25 LSB
Number of missing codes
0 Code
PGA Gain
Red Channel Max. Gain, Note 1
Gr
12
MCLK=12MHz; VDD=5V
4
Times
Green Channel Max. Gain, Note 2
Gg
12
Mode=1
7
Times
Blue Channel Max. Gain, Note 2
Gb
12
7
Times
Red Channel Max. Gain, Note 2
Gr
8
MCLK=8MHz; VDD=5V
6
Times
Green Channel Max. Gain, Note 2
Gg
8
Mode=1
7
Times
Blue Channel Max. Gain, Note 2
Gb
8
7
Times
WM8144-10
Wolfson Microelectronics
5
Electrical Characteristics (Contd.)
V
DD
= 4.75V to 5.25V, GND = 0 V, ........T
A
= 0oC to +70oC, MLCK = 12MHz unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Switching Characteristics
MCLK Period
tPER
83.3
ns
MCLK High
tCKH
37.5
ns
MCLK Low
tCKL
37.5
ns
Data Set-up time
tDSU
10
ns
VSMP, RLC Data Hold Time
tDH
10
ns
CDATA Data Hold Time
tDH
30
ns
Output Propagation Delay
tPD
I
OH
= 1.0mA
75
ns
Output Enable TIme
tPZE
I
OL
= 1.0mA
75
ns
Output Disable Time
tPEZ
25
ns
Serial Interface
SCK Period
tSPER
83.3
ns
SCK High
tSCKH
37.5
ns
SCK Low
tSCKL
37.5
ns
SDI Set up time
tSSU
10
ns
SDI Hold Time
tSH
10
ns
Set up time - SCK to SEN
tSCE
20
ns
Set up time - SEN to SCK
tSEC
20
ns
SEN Pulse W idth
tSEW
50
ns
Parallel Interface
RNW Low to OP[9:2] Tristate
tOPZ
20
ns
Address Setup Time to STB Low
tASU
0
ns
DNA Low Setup Time to STB Low
tADLS
10
ns
Strobe Low Time
tSTB
50
ns
Address Hold Time from STB High
tAH
10
ns
DNA Low Hold Time from STB High
tADLH
10
ns
Data Set-up Time to STB Low
tDSU
0
ns
DNA High Setup Time to STB Low
tADHS
10
ns
Data Hold Time from STB High
tDH
10
ns
DNA High Hold Time from STB High
tADHH
10
ns
RNW High to OP[9:2] Output
tOPD
0
ns
PDF 
ZIP