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Электронный компонент: WM8150CDS

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WM8150
Single Channel 12-bit CIS/CCD AFE with 4-bit Wide Output
WOLFSON MICROELECTRONICS plc
w :: www.wolfsonmicro.com
Production Data, November 2002, Rev 3.0
Copyright
2002 Wolfson Microelectronics plc
DESCRIPTION
The WM8150 is a 12-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 8MSPS.
The device includes a complete analogue signal processing
channel containing Reset Level Clamping, Correlated
Double Sampling, Programmable Gain and Offset adjust
functions. Internal multiplexers allow fast switching of offset
and gain for line-by-line colour processing. The output from
this channel is time multiplexed into a high-speed 12-bit
Analogue to Digital Converter. The digital output data is
available in 4-bit wide multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 5V, a digital core
voltage of 5V, and a digital interface supply of either 5V or
3.3V, the WM8150 typically only consumes 160mW when
operating from a single 5V supply.
FEATURES
12-bit ADC
8MSPS conversion rate
Low power - 170mW typical
5V single supply or 5V/3.3V dual supply operation
Single channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
4-bit wide multiplexed data output format
Internally generated voltage references
20-pin SSOP package
Serial control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
BLOCK DIAGRAM
VRLC/VBIAS
VINP
SEN
VSMP
MCLK
SDI
SCK
TIMING CONTROL
CL
RLC
V
S
R
S
VRX
VRT
VRB
CDS
4
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
12-
BIT
ADC
AGND1
DGND
AVDD
DVDD1
OP[0]
OP[1]
OP[2]
OP[3]/SDO
AGND2
VREF/BIAS
R
G
B
M
U
X
R
G
B
PGA
I/P SIGNAL
POLARITY
ADJUST
8
8
+
+
M
U
X
DATA
I/O
PORT
DVDD2
W
WM8150
OFFSET
DAC
RLC
DAC
WM8150
Production Data
w
PD Rev 3.0 November 2002
2
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM8150CDS
0 to 70
o
C
20-pin SSOP
WM8150CDS/R
0 to 70
o
C
20-pin SSOP
(tape and reel)
WM8150
1
VINP
2
3
4
5
6
7
8
10
9
20
19
18
17
16
15
14
13
11
12
DVDD1
VSMP
MCLK
DGND
SEN
DVDD2
SDI
SCK
OP[0]
AGND2
VRLC/VBIAS
VRX
VRT
VRB
AGND1
AVDD
OP[3]/SDO
OP[1]
OP[2]
Note:
Reel quantity = 2,000
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
AGND2
Supply
Analogue ground (0V).
2
DVDD1
Supply
Digital core (logic and clock generator) supply (5V)
3
VSMP
Digital input
Video sample synchronisation pulse.
4
MCLK
Digital input
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
5
DGND
Supply
Digital ground (0V).
6
SEN
Digital input
Enables the serial interface when high.
7
DVDD2
Supply
Digital supply (5V/3.3V), all digital I/O pins.
8
SDI
Digital input
Serial data input.
9
SCK
Digital input
Serial clock.
Digital multiplexed output data bus.
ADC output data (d11:d0) is available in 4-bit multiplexed format as shown below.
A
B
C
D
10
OP[0]
Digital output
d8
d4
d0
OVRNG
11
OP[1]
Digital output
d9
d5
d1
CC0
12
OP[2]
Digital output
d10
d6
d2
CC1
13
OP[3]/SDO
Digital output
d11
d7
d3
0
Alternatively, pin OP[3]/SDO may be used to output register read-back data when
address bit 4=1 and SEN has been pulsed high. See Serial Interface description in
Device Description section for further details.
14
AVDD
Supply
Analogue supply (5V)
15
AGND1
Supply
Analogue ground (0V).
16
VRB
Analogue output
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
17
VRT
Analogue output
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
18
VRX
Analogue output
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
19
VRLC/VBIAS
Analogue I/O
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
20
VINP
Analogue input
Video input.
Production Data
WM8150
w
PD Rev 3.0 November 2002
3
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
The WM8150 has been classified as MSL1, which has an unlimited floor life at <30
o
C / 85%C Relative Humidity and therefore will
not be supplied in moisture barrier bags.
CONDITION
MIN
MAX
Analogue supply voltage: AVDD
GND - 0.3V
GND + 7V
Digital core voltage: DVDD1
GND - 0.3V
GND + 7V
Digital IO supply voltage: DVDD2
GND - 0.3V
GND + 7V
Digital ground: DGND
GND - 0.3V
GND + 0.3V
Analogue grounds: AGND1
-
2
GND - 0.3V
GND + 0.3V
Digital inputs, digital outputs and digital I/O pins
GND - 0.3V
DVDD2 + 0.3V
Analogue input (VINP)
GND - 0.3V
AVDD + 0.3V
Other pins
GND - 0.3V
AVDD + 0.3V
Operating temperature range: T
A
0
C
+70
C
Storage temperature prior to soldering
30
o
C max / 85% RH max
Storage temperature after soldering
-65
C
+150
C
Package body temperature (soldering, 10 seconds)
+260
C
Package body temperature (soldering, 2 minutes)
+183
C
Notes:
1.
GND denotes the voltage of any ground pin.
2.
AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
SYMBOLMIN
TYP
MAX
UNITS
Operating temperature range
T
A
0
70
C
Analogue supply voltage
AVDD
4.75
5.0
5.25
V
Digital core supply voltage
DVDD1
4.75
5.0
5.25
V
5V I/O
DVDD2
4.75
5.0
5.25
V
Digital I/O supply voltage
3.3V I/O
DVDD2
2.97
3.3
3.63
V
WM8150
Production Data
w
PD Rev 3.0 November 2002
4
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T
A
= 25
C, MCLK = 16MHz unless otherwise stated.
PARAMETER
SYMBOLTEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 12-bit ADC, PGA, Offset and CDS functions)
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
0.30
3.22
Vp-p
Vp-p
Input signal limits (see Note 2)
V
IN
0
VDD
V
Full-scale transition error
Gain = 0dB;
PGA[7:0] = 07(hex)
-50
10
+50
mV
Zero-scale transition error
Gain = 0dB;
PGA[7:0] = 07(hex)
-50
10
+50
mV
Differential non-linearity
DNL
0.5
1
LSB
Integral non-linearity
INL
2
5
LSB
Total output noise
Min Gain
Max Gain
0.25
0.70
LSB rms
LSB rms
References
Upper reference voltage
VRT
2.70
V
Lower reference voltage
VRB
1.45
V
Input return bias voltage
VRX
1.55
1.65
1.75
V
Diff. reference voltage (VRT-VRB)
V
RTB
1.15
1.25
1.35
V
Output resistance VRT, VRB, VRX
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
20
50
100
VRLC short-circuit current
1.86
2
4.5
mA
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
1
A
RLCDAC resolution
4
bits
RLCDAC step size, RLCDAC = 0
V
RLCSTEP
AVDD = 5.0V
0.23
0.25
0.27
V/step
RLCDAC step size, RLCDAC = 1
V
RLCSTEP
0.14
0.16
0.20
V/step
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
V
RLCBOT
AVDD = 5.0V
0.34
0.39
0.44
V
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
V
RLCBOT
0.20
0.26
0.31
V
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
V
RLCTOP
AVDD = 5.0V
4.0
4.16
4.3
V
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
V
RLCTOP
2.56
2.66
2.76
V
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
Differential non-linearity
DNL
0.1
0.5
LSB
Integral non-linearity
INL
0.25
1
LSB
Step size
2.04
mV/step
Output voltage
Code 00(hex)
Code FF(hex)
-247
+247
-260
+260
-273
+273
mV
mV
Notes:
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input
range.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
Production Data
WM8150
w
PD Rev 3.0 November 2002
5
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T
A
= 25
C, MCLK = 16MHz unless otherwise stated.
PARAMETER
SYMBOLTEST
CONDITIONS
MIN
TYP
MAX
UNIT
Programmable Gain Amplifier
Resolution
8
bits
Gain equation
255
7.57
0]
:
PGA[7
0.78
+
V/V
Max gain
G
MAX
6.8
8.35
8.7
V/V
Min gain
G
MIN
0.75
0.78
0.82
V/V
Gain error
1
2
%
Internal channel offset
V
OFF
10
mV
Analogue to Digital Converter
Resolution
12
bits
Maximum Speed
8
MSPS
Full-scale input range
(2*(VRT-VRB))
V
FS
2.5
V
DIGITALSPECIFICATIONS
Digital Inputs
Highlevel input voltage
V
IH
0.8
DVDD2
V
Low level input voltage
V
IL
0.2
DVDD2
V
Highlevel input current
I
IH
1
A
Low level input current
I
IL
1
A
Input capacitance
C
I
5
pF
Digital Outputs
Highlevel output voltage
V
OH
I
OH
= 1mA
DVDD2 - 0.5
V
Low level output voltage
V
OL
I
OL
= 1mA
0.5
V
Supply Currents



Total supply current
-
active
35
45
mA
Total analogue AVDD, supply
current
-
active
I
AVDD
30
40
mA
Total digital core, DVDD1,
supply current
-
active
I
DVDD1
1.7
2
mA
Digital I/O supply current,
DVDD2
-
active (see note 3)
I
DVDD2
4
5
mA
Supply current
-
full power down
mode
300
400
A
Notes:
3.
Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is
measured with approximately 50pF attached to the pin.