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WM8608
5 to 7.1 Channel PWM Controller
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Product Preview, March 2004, Rev 1.5
Copyright
2004 Wolfson Microelectronics plc
DESCRIPTION
The WM8608 comprises a high performance multi-channel
PWM digital power amplifier controller. Simply by adding
appropriate power output stages a multi-channel power
amplifier may be built. Six identical full audio bandwidth
channels, plus a reduced bandwidth sub channel are
provided as PWM outputs, to drive 6 speakers plus Sub.
The PCM to PWM converter supports up to 7.1 channels of
audio, in PCM input formats. These may be mixed down to
6.1 or 5.1 outputs, by mixing rear channel data into centre
rear or surround speakers if required. If 5.1 channel data is
input, the surround data may be processed internally to
create a pseudo 6.1 signal with rear channel output.
A Graphic Equaliser function is provided, plus selectable
high frequency equalisation to suit different speaker types.
Independent volume control for each channel is provided.
The WM8608 PWM controller is compatible with integrated
switching output stages available from a number of vendors
or alternatively may be used with a discrete output stage
configuration and achieve similar levels of performance.
A Dynamic Peak Compressor with programmable attack
and decay times is included, which allows headroom for
tone control, bass management and extra digital gain to be
provided, without clipping occurring.
A Synchroniser allows slaving to LRCLK, thus making the
WM8608 independent of source MCLK frequency and jitter.
The device is controlled via a 2/3 wire serial interface. The
interface provides access to all features including channel
selection, volume controls, mutes, de-emphasis and power
management facilities. The device is supplied in a 48-pin
TQFP package.
FEATURES
Multi-channel PWM audio amplifier controller
Supports Stereo, 5.1, 6.1 or 7.1 inputs
Supports 2.1, 5.1 or 6.1 outputs with optional rear centre
channel generation
PWM Audio Performance with typical output stage
-
100dB SNR (`A' weighted @ 48kHz)
-
0.01% THD @ 1Watt
-
0.1% THD @ 30Watt
Integrated Bass Management support with adjustable filter
Integrated 4-band Graphic Equaliser for 3 front channels
Adjustable output stage filter compensation for different
speakers
Volume control on each 6.1 channel +24dB to -103.5dB in
0.5dB steps, with volume ramping and auto-mute
functions
Programmable Dynamic Peak Compressor avoids clipping
even at high volume settings
Internal PLL and optional crystal oscillator, supporting
Audio and MPEG standards
2/3-Wire MPU Serial Control Interface
Master or Slave Clocking Mode
Programmable Audio Data Interface Modes
-
I
2
S, Left, Right Justified or DSP
-
16/20/24/32 bit Word Lengths
De-emphasis support for stereo
Selectable CMOS or LVDS digital outputs
APPLICATIONS
Surround Sound AV Processors and Hi-Fi systems
Automotive
Audio
DVD
receivers
WM8608
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TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................4
ORDERING INFORMATION ..................................................................................4
ABSOLUTE MAXIMUM RATINGS .........................................................................6
ELECTRICAL CHARACTERISTICS ......................................................................7
TERMINOLOGY .....................................................................................................8
POWER CONSUMPTION ......................................................................................8
SIGNAL TIMING REQUIREMENTS .......................................................................9
POWER SUPPLY.......................................................................................................... 9
MASTER CLOCK TIMING ............................................................................................. 9
AUDIO INTERFACE TIMING MASTER MODE ........................................................ 10
AUDIO INTERFACE TIMING SLAVE MODE............................................................ 11
CONTROL INTERFACE TIMING 3-WIRE MODE .................................................... 12
CONTROL INTERFACE TIMING 2-WIRE MODE .................................................... 13
PWM OUTPUT TIMING .............................................................................................. 14
DEVICE DESCRIPTION .......................................................................................15
INTRODUCTION ......................................................................................................... 15
SIGNAL PATH............................................................................................................. 15
DIGITAL AUDIO INTERFACE ..................................................................................... 16
AUDIO INTERFACE CONTROL.................................................................................. 20
MASTER CLOCK AND AUDIO SAMPLE RATES........................................................ 21
SYNCHRONISER........................................................................................................ 24
CONTROL INTERFACE OPERATION ........................................................................ 25
INPUT PROCESSOR .................................................................................................. 26
BASS MANAGEMENT................................................................................................. 29
GRAPHIC EQUALISER............................................................................................... 31
DIGITAL DEEMPHASIS .............................................................................................. 33
DIGITAL VOLUME CONTROL .................................................................................... 33
SOFT MUTE AND AUTO-MUTE ................................................................................. 36
DYNAMIC PEAK COMPRESSOR ............................................................................... 37
INTERPOLATION FILTERS ........................................................................................ 41
PCM TO PWM CONVERTER ..................................................................................... 42
STANDBY, OUTPUT DISABLE AND RESET MODES ................................................ 45
EXTERNAL POWER SUPPLY CLOCK ....................................................................... 46
REGISTER MAP...................................................................................................47
FILTER RESPONSES ................................................................................................. 48
DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 49
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APPLICATION NOTES ........................................................................................50
START-UP .................................................................................................................. 50
POWER SUPPLY CONNECTIONS............................................................................. 51
APPLICATIONS INFORMATION .........................................................................52
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 52
RECOMMENDED EXTERNAL COMPONENTS VALUES ........................................... 52
PACKAGE DIMENSIONS ....................................................................................53
IMPORTANT NOTICE ..........................................................................................54
ADDRESS: .................................................................................................................. 54
WM8608
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4
PIN CONFIGURATION
TOP
VIEW
LR
CL
K
DI
NRE
A
R
DI
NF
RO
NT
DIN
C
_
L
F
E
DI
N
S
RN
D
MC
L
K
BC
L
K
MODE
OP
D
I
S
OP
S
L
N
BG
N
D
DG
N
D
DV
DD
XO
P
XI
N
13
SCLK
14
SDIN
15
CSB
16
PWMCLKN
17
BVDD
18
OPFRN
19
OPFRP
20
BGND
21
OP
S
R
N
22
OP
S
R
P
23
BVDD
24
25
26
27
28
29
30
31
32
33
34
35
36
BVD
D
BG
N
D
BVD
D
OPRCN
C
L
KPSU
AG
N
D
OPRCP
OPSWN
OPSWP
OP
FC
N
OP
FC
P
37
38
39
40
41
42
43
44
45
46
47
1
OP
S
L
P
BGND
OPFLN
OPFLP
BVDD
EAPDB
TEST
PWMCLKP
TEST
AVDD
AGND
2
3
10
9
8
7
6
5
4
12
11
ORDERING INFORMATION
DEVICE
TEMP RANGE
PACKAGE
MOISTURE LEVEL
SENSITIVITY
PEAK SOLDERING
TEMP
WM8608EFT/V
-25 to + 85
C TQFP
48
7x7mm
MSL2
240C
WM8608EFT/RV
-25 to + 85
C TQFP
48
7x7mm
(tape and reel)
MSL2 240C
WM8608SEFT/V
-25 to + 85
C
TQFP 48 7x7mm
(lead free)
MSL2 260C
WM8608SEFT/RV
-25 to + 85
C TQFP
48
7x7mm
(lead free, tape and reel)
MSL2 260C
Note:
Reel quantity = 2,200
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5
PIN DESCRIPTION
PIN NAME
TYPE
DESCRIPTION
1 XOP
Digital
Output
Crystal oscillator output connection
2 XIN
Digital
Input
Crystal oscillator input connection (may be left unconnected in slave
mode)
3 DGND Supply
Digital negative supply
4 MCLK
Digital
Input/Output
Master clock; 256, 384, 512 fs (fs = word clock frequency) or 27MHz
5 DVDD Supply
Digital positive supply
6 DINFRONT
Digital
Input
Front channel data input
7 DINSRND
Digital
Input
Surround channel data input
8 DINC_LFE
Digital
Input
Centre and surround channel data input
9 DINREAR
Digital
Input
Rear channel data for 6.1 and 7.1 inputs
10 LRCLK
Digital
Input/Output
Left/right word clock
11 BCLK Digital
IO
Audio interface bit clock
12
OPDIS
Digital Input p.d.
Output disable
13
MODE
Digital Input p.d.
2/3 Wire control interface mode
14 SCLK Digital
Input
Serial interface clock
15 SDIN
Digital
Input/Output
Serial interface data
16 CSB Digital
Input
Serial interface load signal
17 EAPDB
Digital
Output
External output stage power down
18 BVDD Supply
PWM output buffer positive supply
19 OPSWN
Digital
Output
PWM output negative Subwoofer channel
20 OPSWP
Digital
Output
PWM output positive Subwoofer channel
21 BGND Supply
PWM output buffer ground supply
22 OPRCN
Digital
Output
PWM output negative Rear centre (left) channel
23 OPRCP
Digital
Output
PWM output positive Rear centre (left) channel
24 BVDD Supply
PWM output buffer positive supply
25 AGND Supply
Analogue negative supply
26 CLKPSU
Digital
Output
Clock for external PSU
27 BGND Supply
PWM output buffer ground supply
28 OPSRN
Digital
Output
PWM output negative Surround right channel
29 OPSRP
Digital
Output
PWM output positive Surround right channel
30 BVDD Supply
PWM output buffer positive supply
31 OPSLN
Digital
Output
PWM output negative Surround left channel
32 OPSLP
Digital
Output
PWM output positive Surround left channel
33 BGND Supply
PWM output buffer ground supply
34
OPFCN
Digital Output
PWM output negative Front centre channel
35 OPFCP
Digital
Output
PWM output positive Front centre channel
36 BVDD Supply
PWM output buffer positive supply
37 OPFRN
Digital
Output
PWM output negative Front right channel
38 OPFRP
Digital
Output
PWM output positive Front right channel
39 BGND Supply
PWM output buffer ground supply
40 OPFLN
Digital
Output
PWM output negative Front left channel
41 OPFLP
Digital
Output
PWM output positive Front left channel
42 BVDD Supply
PWM output buffer positive supply
43 PWMCLKN
Digital
Output
PWM Clock negative
44 PWMCLKP
Digital
Output
PWM Clock positive
45 NC
Not
Connected
Do Not Connect
46 NC
Not
Connected
Do Not Connect
47 AVDD
Analogue
Supply
Analogue positive supply
48 AGND
Analogue
Supply
Analogue negative supply
Notes: Digital input pins have Schmitt trigger input buffers. Pins marked `p.u.' or `p.d.' have internal pull-up or pull down.
WM8608
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30
C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN MAX
Analogue supply voltage (AVDD)
-0.3V +5V
Digital supply voltage (DVDD)
-0.3V +5V
PWM output buffer supply voltage (BVDD)
-0.3V +5V
Voltage range inputs
DGND -0.3V
DVDD +0.3V
Master Clock Frequency
10MHz 50MHz
Operating temperature range, T
A
-20
C +85
C
Storage temperature
-65
C +150
C
Notes:
1.
GND power supplies (i.e. AGND, DGND, and BGND) must always be within 0.3V of each other.
2.
VDD power supplies (i.e. AVDD, DVDD, and BVDD) must always be within 0.3V of each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Analogue supply range
AVDD
2.7
3.6
V
Digital supply range
DVDD
2.7
3.6
V
PWM output buffer supply
BVDD
2.7
3.6
V
Ground
AGND,
DGND,
BGND
0 V
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ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, BVDD, DVDD = 2.7 to 3.3V, AGND, DGND, BGND = 0V, T
A
= -20 to +85
o
C, fs = 44.1kHz/48kHz, MCLK = 256fs unless
stated.
PARAMETER SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Input capacitance
C
i
3
4
pF
Input leakage
I
leak
0.1
0.5
A
Oscillator
Input XIN LOW level
VX
IL
0
0.44
V
Input XIN HIGH level
VX
IH
0.77
AVDD
V
Input XIN capacitance
C
XI
4
5
pF
Input XIN leakage
IX
leak
0.10
0.11
0.13
mA
Output XOP LOW
VX
OL
15pF load capacitors
0.1
0.4
0.5
V
Output XOP HIGH
VX
OH
15pF load capacitors
1.2
1.3
1.4
V
Digital Logic Levels (CMOS Levels)
Input LOW level
V
IL
0.3
x
DVDD
V
Input HIGH level
V
IH
0.7 x DVDD
V
Pull-up/pull-down resistance
100
200
400
k
Output LOW
V
OL
I
OL
=+1mA
0.1
x
DVDD
V
Output HIGH
V
OH
I
OL
=-1mA
0.9 x DVDD
V
Digital Logic Levels (LVDS Levels)
Output differential voltage
V
OD
R
T
=100
200
350
500
mV
Offset voltage
V
OS
R
T
=100
0.95
1.25
1.4 V
Termination load
R
T
20pF load
100
PCM to PWM converter
Digital SNR
FL, FR, FC, SL, SR, RC
105
dB
Typical SNR with output stage
(A-weighted)
FL, FR, FC, SL, SR, RC
100
dB
Typical Dynamic Range with
output stage
FL, FR, FC, SL, SR, RC
100
dB
Digital THD+N at 0dBfs
FL, FR, FC, SL, SR, RC
0.001
%
Typical THD+N at 30Watt with
output stage
FL, FR, FC, SL, SR, RC
0.1
%
Typical THD+N at 1Watt with
typical output stage
FL, FR, FC, SL, SR, RC
0.01
%
Typical IMD (CCIF 19/20kHz)
FL, FR, FC, SL, SR, RC
-70
dBFS
Typical IMD (SMPTE
60Hz/7kHz)
FL, FR, FC, SL, SR, RC
-70
dBFS
PCM to PWM converter
Digital SNR
Subwoofer
5
105 dB
Typical SNR with output stage
(A-weighted)
Subwoofer
5
100 dB
Typical Dynamic Range with
output stage
Subwoofer
5
100 dB
Digital THD+N at 0dBfs
Subwoofer
5
0.001 %
Typical THD+N at 30Watt with
output stage
Subwoofer
5
0.1 %
Typical THD+N at 1Watt with
typical output stage
Subwoofer
5
0.01
%
Typical IMD (CCIF 19/20kHz)
Subwoofer
5
-70
dBFS
Typical IMD (SMPTE
60Hz/7kHz)
Subwoofer
5
-70
dBFS
WM8608
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Test Conditions
AVDD, BVDD, DVDD = 2.7 to 3.3V, AGND, DGND, BGND = 0V, T
A
= -20 to +85
o
C, fs = 44.1kHz/48kHz, MCLK = 256fs unless
stated.
PARAMETER SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
PWM buffer drive strength
I
source
CMOS 25
4
mA
I
sink
20pF load
25
4
mA
fs
=
44.1kHz 352.8 kHz
PWM pulse repetition rate
f
PWM
fs = 48kHz
384
kHz
Notes:
1.
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A'
weighted over a 20Hz to 20kHz bandwidth.
2.
All performance measurements done with 20kHz AES17 low pass filter, except where noted an A-weight filter is used.
Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in
the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect
dynamic specification values.
3.
Parameter guaranteed by design.
4.
Validated using the following filter
PARAMETER SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Filter
Stopband
-3dB
1.00
kHz
Note: A third order differential RC filter has been used
TERMINOLOGY
1.
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied.
2.
Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD+N (dB) - THD+N is a ratio, of the RMS values, of (Noise + Distortion)/Signal.
POWER CONSUMPTION
TYPICAL SUPPLY CURRENTS
[mA]
TOTAL CURRENT
[mA]
TOTAL POWER
[mW]
I
BVDD
MODE DESCRIPTION
I
AVDD
I
DVDD
CMOS
LVDS
CMOS LVDS CMOS
LVDS
AVDD, DVDD, BVDD = 3.3V
OFF
0 0 0 0 0 0 0 0
Standby
0.02 0.28 0
0
0.30 0.30 0.99 0.99
Mute
1.76 27.2 7.55 29.0 36.5 58.0 121 191
Stereo
1.76 27.7 7.55 29.0 37.0 58.5 122 193
5.1
1.76 28.1 7.55 29.0 37.5 58.9 124 194
6.1
1.76 29.6 7.55 29.0 38.9 60.3 128 199
7.1
1.72 29.9 7.55 29.0 39.2 60.6 129 200
Table 1 Supply Current Consumption
Notes:
1. T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 27 kHz, 24-bit data
2.
All figures are kHz 1kHz input sine wave @ 0dB.
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SIGNAL TIMING REQUIREMENTS
POWER SUPPLY
Test Conditions
AGND, DGND, BGDN = 0V, T
A
= +25
C
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
Power Supply Timing Information
AVDD: rise time 10% to 90% AVDD
t
AR
0.2 50
ms
DVDD: rise time 10% to 90% DVDD
t
DR
0.2 50
ms
BVDD: rise time 10% to 90% BVDD
t
BR
0.2 50
ms
Table 2 Power Supply Timing Requirements
MASTER CLOCK TIMING
MCLK
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGDN = 0V, T
A
= +25
C
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
t
MCLKY
20 100
ns
MCLK Duty cycle
40:60
60:40
%
MCLK Period Jitter
200
ps
MCLK Rise/Fall times 10% to 90% AVDD
3
ns
Table 3 Master Clock Timing Requirements
WM8608
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AUDIO INTERFACE TIMING MASTER MODE
BCLK
(Output)
LRCLK
(Output)
t
DL
DINFRONT
DINSRND
DINC_LFE
DINREAR
t
DHT
t
DST
Figure 2 Digital Audio Data Timing Master Mode (see Control Interface)
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGDN = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data,
unless otherwise stated.
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
t
DL
10
ns
DINFRONT, DINSRND, DINC_LFE and DINREAR setup time
to BCLK rising edge
t
DST
10
ns
DINFRONT, DINSRND, DINC_LFE and DINREAR hold time
from BCLK rising edge
t
DHT
10
ns
Table 4 Audio Interface Timing Master Mode
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AUDIO INTERFACE TIMING SLAVE MODE
BCLK
LRCLK
t
BCH
t
BCL
t
BCY
DINFRONT
DINSRND
DINC_LFE
DINREAR
t
LRSU
t
DS
t
LRH
t
DH
Figure 3 Digital Audio Data Timing Slave Mode
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data,
unless otherwise stated.
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
t
BCY
50
ns
BCLK pulse width high
t
BCH
20
ns
BCLK pulse width low
t
BCL
20
ns
BCLK rise/fall times
5
ns
LRCLK set-up time to BCLK rising edge
t
LRSU
10
ns
LRCLK hold time from BCLK rising edge
t
LRH
10
ns
LRCLK rise/fall times
5
ns
DINFRONT, DINSRND, DINC_LFE and DINREAR hold
time from BCLK rising edge
t
DH
10
ns
Table 5 Audio Interface Timing Slave Mode
Note: BCLK period should always be greater than or equal to MCLK period.
WM8608
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CONTROL INTERFACE TIMING 3-WIRE MODE
CSB
SCLK
SDIN
t
CSL
t
DHO
t
DSU
t
CSH
t
SCY
t
SCH
t
SCL
t
SCS
LSB
t
CSS
Figure 4 Control Interface Timing 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data,
unless otherwise stated.
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
t
SCS
60
ns
SCLK pulse cycle time
t
SCY
80
ns
SCLK pulse width low
t
SCL
30
ns
SCLK pulse width high
t
SCH
30
ns
SDIN to SCLK set-up time
t
DSU
20
ns
SCLK to SDIN hold time
t
DHO
20
ns
CSB pulse width low
t
CSL
20
ns
CSB pulse width high
t
CSH
20
ns
CSB rising to SCLK rising
t
CSS
20
ns
Pulse width of spikes that will be suppressed
t
ps
2
8
ns
Table 6 Control Interface Timing 3-Wire Serial Control Mode
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CONTROL INTERFACE TIMING 2-WIRE MODE
SDIN
SCLK
t
3
t
1
t
6
t
2
t
7
t
5
t
4
t
3
t
8
t
10
Figure 5 Control Interface Timing 2-Wire Serial Control Mode
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data,
unless otherwise stated.
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
400
kHz
SCLK Low Pulse-Width
t
1
600
ns
SCLK High Pulse-Width
t
2
1.3
us
Hold Time (Start Condition)
t
3
600
ns
Setup Time (Start Condition)
t
4
600
ns
Data Setup Time
t
5
100
ns
SDIN, SCLK Rise Time
t
6
300
ns
SDIN, SCLK Fall Time
t
7
300
ns
Setup Time (Stop Condition)
t
8
600
ns
Data Hold Time
t
9
900
ns
Pulse width of spikes that will be suppressed
t
ps
2
8
ns
Table 7 Control Interface Timing 2-Wire Serial Control Mode
WM8608
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PWM OUTPUT TIMING
OPXXX
t
PWMH
t
PWML
t
PWMCY
Figure 6 PWM Output Timing
Test Conditions
AVDD, DVDD, BVDD = 2.7 to 3.3V, AGND, DGND, BGND = 0V, T
A
= -20 to +85
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs,
24-bit data, unless otherwise stated.
PARAMETER SYMBOL/NOTE
MIN
TYP
MAX
UNIT
Program Register Input Information
PWM Frequency
t
PWMCY
384 kHz
PWM Low Pulse-Width
t
PWML
122
ns
PWM High Pulse-Width
t
PWMH
122
ns
LVDS Mode
PWM Rise Time
1
20pF load
1.5
1.8
2.0
ns
PWM Fall Time
1
20pF load
1.7
2.0
2.2
ns
CMOS Mode
PWM Rise Time
1
20pF load
1.5
2.3
ns
PWM Fall Time
1
20pF load
1.5
2.3
ns
Table 8 PWM Interface Timing
Note:
1.
Parameter guaranteed by design
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DEVICE DESCRIPTION
INTRODUCTION
The WM8608 is a high-performance multi-channel Pulse-Width Modulation (PWM) digital power
amplifier controller. The device accepts up to 7.1 channels of audio in PCM input format, and outputs
six PWM full-bandwidth channels, plus a PWM sub-woofer channel. The outputs are suitable for
directly driving integrated switching output stages available from a number of vendors. The device is
also compatible with discrete MOSFET output stages. In both cases, Wolfson Microelectronics offer
Reference Designs for complete PWM digital power amplifiers, providing high-performance low-cost
solutions ideal for Surround Sound AV Processors and DVD Receivers.
The WM8608 has a configurable input processor which accepts either Stereo, 5.1, 6.1 or 7.1
channels of PCM audio and outputs Stereo, 2.1, 5.1 or 6.1 outputs. This is done by mixing rear
channel data into centre rear or surround output channels, as required. If 5.1 channel data is input,
the surround data may be processed to create the rear-centre output.
The device has a Bass Management function, which has low-pass and high-pass filters for feeding
the sub channel and main output channels. It also provides selectable boost for the LFE channel.
Each channel can be configured to drive either "large" full-range speakers or "small" satellite
speakers with limited bass capability.
A Tone Control function is provided, plus selectable high frequency equalisation to compensate for
different loudspeaker characteristics. Independent volume control is provided for all channels, with
comprehensive mute features.
A Dynamic Peak Compressor with programmable attack and decay times is included, which allows
headroom for tone control, bass management and extra digital gain to be provided, without clipping
occurring.
The device is controlled via a 2/3 wire serial interface. The interface provides access to all features
including channel selection, volume controls, mute, de-emphasis and power management facilities.
SIGNAL PATH
The WM8606 receives digital input data via an 8-channel digital audio interface. The data is
processed in turn by the Input Processor, Bass Management and Equalisation, Volume Control and
Dynamic Peak Compressors, Interpolation Filters, and PCM-PWM Converters, as shown in Figure 7.
The PWM signals are output via selectable LVDS/CMOS drivers.
Figure 7 Signal Processing Block Diagram
Volume Control / Dynamic
Peak Compressors
PCM - PWM Converter
Interpolation Filters
Input Processor
Bass Management and
Equalisation
CMOS / LVDS Output
8 Channel Input
WM8608
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Parameter
Group
Delay
Unit fs=48kHz Unit
FL/FR/FC/SL/SR/RC channel
47 samples
1.0
ms
SUB channel
22 samples
0.5
ms
Table 9 Signal Path Group Delay
Key: FL = Front-Left, FR = Front-Right, FC = Front-Centre, SL = Surround-Left, SR = Surround-Right,
RL = Surround-Left, RR = Surround-Right, RC = Surround-Centre, SUB = Subwoofer
Note: The shorter delay on the SUB channel will not significantly affect audio performance. (It is
equivalent to moving the subwoofer forwards by about 15cm.)
DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting audio data into the WM8608. It uses five pins:
DINFRONT: Front L+R channel data input
DINSRND: Surround L+R channel data input
DINC_LFE: Front Centre (L) and LFE (R) channel data input
DINREAR: Rear L+R channel data input
LRCLK: Data alignment clock
BCLK: Bit clock, for synchronisation
The clock signals BCLK and LRCLK can be outputs when the WM8608 operates as a master, or
inputs when it is a slave (see Master and Salve Mode Operation, below).
MASTER AND SLAVE MODE OPERATION
The WM8608 can be configured as either a master or slave mode device. As a master device the
WM8608 generates BCLK and LRCLK and thus controls sequencing of the data transfer on the data
channels. In slave mode, the WM8608 receives data and clock signals over the digital audio
interface. The mode can be selected by writing to the MS bit (see Table 23). Master and slave modes
are illustrated below.
BCLK
LRCLK
DINFRONT
WM8608
PWM
Contoller
DSP
DECODER
DINSRND
DINREAR
DINC_LFE
BCLK
LRCLK
DINFRONT
WM8608
PWM
Contoller
DSP
DECODER
DINSRND
DINREAR
DINC_LFE
Master Mode
Slave Mode
Figure 8 Operation Mode
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK Audio
data is applied to the internal filters via the Digital Audio Interface. 5 popular interface formats are
supported:
Left Justified mode
Right Justified mode
I
2
S mode
DSP mode A
DSP mode B
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits. Except that 32
bit data is not supported in right justified mode. DINFRONT, DINSRND, DINC_LFE, DINREAR and
LRCLK are sampled on the rising, or falling edge of BCLK.
In left justified, right justified and I
2
S modes the digital audio interface receives data on the
DINFRONT, DINSRND, DINC_LFE and DINREAR inputs. Audio Data for each stereo channel is time
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multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as
a timing reference to indicate the beginning or end of the data words.
In left justified, right justified and I
2
S modes, the minimum number of BCLKs per DACLRC period is 2
times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low
for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the
above requirements are met.
In DSP mode A or B, all channels are time multiplexed onto DINFRONT. LRCLK is used as a frame
sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period
is 8 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the
rising edge is correctly positioned (see Figure 9, Figure 10 and Figure 11).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCLK following a LRCLK
transition. LRCLK is high during the left samples and low during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DINFRONT
DINSRND
DINC_LFE
DINREAR
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 9 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.
LRCLK is high during the left samples and low during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DINFRONT
DINSRND
DINC_LFE
DINREAR
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 10 Right Justified Mode Timing Diagram
WM8608
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I
2
S MODE
In I
2
S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition.
LRCLK is low during the left samples and high during the right samples.
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
DINFRONT
DINSRND
DINC_LFE
DINREAR
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCLK
1 BCLK
Figure 11 I
2
S Mode TIming Diagram
DSP MODE A AND B
In DSP mode, the Front Left (FL) channel MSB is available on either the 1
st
(mode B) or 2
nd
(mode
A) rising edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
LRCLK
BCK
DINFRONT
Input Word Length (IWL)
1/fs
DINFRONT
LEFT
n
2
1
n-1
LSB
MSB
n
2
1
n-1
DINFRONT
RIGHT
2
1
DINSRND
LEFT
n
n-1
DINREAR
RIGHT
NO VALID DATA
1 BCLK
1 BCLK
Figure 12 DSP Mode A Timing Diagram
LRCLK
BCK
DINFRONT
Input Word Length (IWL)
1/fs
DINFRONT
LEFT
n
2
1
n-1
LSB
MSB
n
2
1
n-1
DINFRONT
RIGHT
2
1
DINSRND
LEFT
n
n-1
DINREAR
RIGHT
NO VALID DATA
1
Figure 13 DSP Mode B Timing Diagram
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In both DSP modes A and B, DINFRONT left is always sent first, followed immediately by data words
for the other channels. No BCLK edges are allowed between the data words.
MODE
INPUT FORMAT (ORDER)
SUPPORTED MODES
Stereo FL,
FR
5.1
FL, FR, SL, SR, FC, LFE
6.1
FL, FR, SL, SR, FC, LFE, RC
7.1
FL, FR, SL, SR, FC, LFE, RL, RR
Restrictions apply for audio sample
rates (fs) of 176.4 and 192kHz,
e.g. fs = MCLK/192; maximal input
word length = 24 bits, or
fs = 192kHz, MCLK = 27 MHz;
maximal input word length = 16 bits
(see also Table 14).
Table 10 DSP Mode Input Format
Key: FL = Front-Left, FR = Front-Right, FC = Front-Centre, SL = Surround-Left, SR = Surround-Right,
RL = Surround-Left, RR = Surround-Right, RC = Surround-Centre, LFE = Low Frequency Effects
WM8608
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AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master/slave mode are summarised
below. MS selects audio interface operation in master or slave mode. In Master mode BCLK and
LRCLK are outputs and the frequency of LRCLK is set by the sample rate control bits SR[3:0]. In
Slave mode BCLK and LRCLK are inputs (refer to Table 12 for sample rate control in this case).
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
8
BCLKINV
0
BCLK invert bit (for master and slave
modes)
0 = BCLK not inverted
1 = BCLK inverted
7
MS
0
Master / Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
6
LRSWAP
0
Left/Right channel swap
1 = swap left and right data in audio
interface
0 = output left and right data as normal
5
SUBSWP
0
Front Centre LFE channel swap
1 = Front Centre right and LFE left
0 = Front Centre left and LFE right
Right, left and I
2
S modes LRCLK
polarity
1 = invert LRCLK polarity
0 = normal LRCLK polarity
(as show in e.g. Figure 12)
4 LRP
0
DSP Mode A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
3:2
WL[1:0]
10
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
R2 (02h)
Audio IF
Format
1:0
FORMAT[1:0]
10
Audio Data Format Select
11 = DSP Mode
10 = I
2
S Format
01 = Left justified
00 = Right justified
Table 11 Audio Data Format Control
Notes:
1.
Right Justified mode does not support 32-bit data.
2.
LRSWAP does not affect the polarity of SUBSWP, the left-right controlling of DINC_LFE is
separate from the other channels.
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MASTER CLOCK AND AUDIO SAMPLE RATES
The WM8608 supports a wide range of master clock frequencies on the MCLK pin, and can generate
many commonly used audio sample rates directly from the master clock. (See Table 14 for details.)
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0
CMAST
1
Master Clock Mode
0 = MCLK input
1 = XIN input
1 MPEG
1
MPEG
Mode
0 = see Table 14
1 = MCLK is 27MHz
2
MEDGE
0
Master Clock Active Edge
0 = positive edge
1 = negative edge
R0 (00h)
Clocking
3
CLKDIV2
0
Master Clock Divide by 2
1 = MCLK is divided by 2
0 = MCLK is not divided
Table 12 Clocking and Sample Rate Control (1)
If the WM8608 is running in MPEG mode (i.e. f
XIN
= 27MHz) the sample can be detected
automatically if the SRDET bit is set. In this case, the SR bits do not need programming.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
3:0
SR [3:0]
0000
Sample Rate Control. Refer to
Table 14.
R1 (01h)
Sample Rate
4
SRDET
1
Sample rate detect
1 = Enabled
(in MPEG mode only)
0 = Disabled
Table 13 Clocking and Sample Rate Control (2)
The clocking of the WM8608 is controlled using the CLKDIV2 and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. Each value of SR[3:0] selects one combination of
MCLK division ratios and hence one combination of sample rates (see next page). Since all sample
rates are generated by dividing MCLK, their accuracy depends on the accuracy of MCLK. If MCLK
changes the sample rates change proportionally.
WM8608
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MCLK / XIN
AUDIO SAMPLE RATE
SR [3:0]
(MPEG = 0)
CLKDIV2=0
CLKDIV2=1
[MHz] [MHz] [kHz]
32 (MCLK/384) 0001
12.288 24.576
48 (MCLK/256) 0000
96 (MCLK/256) 0011
24.576 49.152
192 (MCLK/128) 0010
11.2896 22.5792 44.1 (MCLK/256) 0100
88.2
(MCLK/256) 0111
22.5792 45.1584
176.4
(MCLK/128) 0110
32
(MCLK/512) 1001
18.432 36.864
48
(MCLK/384) 1000
96
(MCLK/384)
1011
36.864 not
supported
192
(MCLK/192)
1010
16.9344 33.8688 44.1
(MCLK/384)
1100
88.2
(MCLK/384)
1111
33.8688 not
supported
176.4
(MCLK/192)
1110
(MPEG = 1)
32
0001
44.1
0100
48
0000
88.2
0111
96
0011
176.4
0110
27.000 not
supported
192
0010
Table 14 Master Clock and Sample Rates
The following Figure 14, Figure 15, Figure 16 and Figure 17 illustrate the different Clocking and
Audio IF modes.
Figure 14 Clock and Audio IF: Clock Master / Audio IF Slave (default)
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Figure 15 Clock and Audio IF: Clock Master / Audio IF Master
Figure 16 Clock and Audio IF: Clock Slave / Audio IF Slave
Figure 17 Clock and Audio IF: Clock Slave / Audio IF Master
WM8608
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SYNCHRONISER
The WM8608 contains a synchroniser circuit to support the synchronisation of an external LRCLK to
the local LRCLK. This mode is only supported in MPEG mode.
The specification of the synchroniser circuit is:
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, T
A
= +25
o
C, f
XIN
= 27MHz, Slave Mode, fs = 48kHz, 24-bit data,
unless otherwise stated.
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
Lock time
t
lock
<1
2
s
LRCLK frequency offset
f
offLRCLK
1000
10'000
ppm
f
s
0.2
ppm/s
LRCLK drift in Lock
drift
LRCLK
6
Hz
Table 15 Synchroniser Specification
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0
SYNCEN 1
Synchroniser
Enable
0: Disable
1: Enable (in MPEG mode only)
2:1
GMIN[1:0]
10
Minimum Synchroniser Gain
00: minimum gain = 2
0
01: minimum gain = 2
1
10: minimum gain = 2
2
11: minimum gain = 2
3
4:3
GMAX[1:0] 10
Maximum
Synchroniser
Gain
00: maximum gain = 2
8
01: maximum gain = 2
10
10: maximum gain = 2
12
11: maximum gain = 2
14
R32 (20h)
Synchroniser
(1)
5
HOLD
0
Hold Synchroniser (and SR detect)
1 : Synchroniser in hold mode
Table 16 Synchroniser (1)
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R33 (21h)
Synchroniser
(2)
2:0
SYNTO[2:0]
100
Synchroniser Gain time-out
000: 0.2 ms
001: 0.5 ms
010: 1 ms
011: 2 ms
100: 5 ms (default)
101: 10 ms
110: 20 ms
111: 50 ms
Table 17 Synchroniser (2)
The next table illustrates recommendation for the Synchroniser loop gain G (see also Table 16) and
time-out time (Table 17) with respect to the LRCLK frequency and the resulting Synchroniser lock
time.
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G
F
OFFLRCLK
[ppm]
max min
GAIN TIME-OUT
[ms]
100 2
8
2
0
~1
1000 2
10
2
0
~4
10'000 2
10
2
0
~20
Table 18 Synchroniser Setup and Locking
Note: The Synchroniser requires a continuously running LRCLK. If that is not the case the HOLD
signal has to be applied to avoid the synchronizer drifting.
CONTROL INTERFACE OPERATION
SELECTION OF CONTROL MODE
The WM8608 is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each
control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The
MODE pin selects the interface format. An internal pull-down resistor configures the Control Interface
to a default 2 wire format.
MODE INTERFACE
FORMAT
Low 2
wire
(default)
High 3
wire
Table 19 Control Interface Mode Selection
The WM8606 Control Interface operates as a slave device only.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8608 is controlled using a 3-wire serial interface. SDIN is used for the program data, SCLK
is used to clock in the program data and CSB is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 13.
CSB
SCLK
SDIN
B15
B6
B7
B8
B9
B10
B11
B12
B13
B14
B1
B2
B3
B4
B5
B0
Figure 18 3-wire Serial Interface
The bits B[15:9] are Control Address Bits and the bits B[8:0] are Control Data Bits
2-WIRE SERIAL CONTROL MODE
The WM8608 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address
of each register in the WM8608).
The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK
remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus
respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit,
MSB first). If the device address received matches the address of the WM8608 and the R/W bit is `0',
indicating a write, then the WM8608 responds by pulling SDIN low on the next clock pulse (ACK). If
the address is not recognised or the R/W bit is `1', the WM8608 returns to the idle condition and wait
for a new start condition and valid address.
WM8608
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Once the WM8608 has acknowledged a correct address, the controller sends the first byte of control
data (B15 to B8, i.e. the WM8608 register address plus the first bit of register data). The WM8608
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the
WM8608 acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8608 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
SDIN
SCLK
register address and
1st register data bit
DEVICE ADDRESS
(7 BITS)
RD / WR
BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
CONTROL BYTE 1
(BITS 7 TO 0)
remaining 8 bits of
register data
STOP
START
ACK
(LOW)
ACK
(LOW)
Figure 18 2-Wire Serial Control Interface
The WM8608 has two possible device addresses, which can be selected using the CSB pin.
CSB STATE
DEVICE ADDRESS
Low
0011010
High 0011011
Table 20 2-Wire MPU Interface Address Selection
INPUT PROCESSOR
The WM8608 supports the production of 2.1, 5.1 and 6.1 outputs from stereo, 5.1, 6.1 and 7.1 inputs
according to Table 21 and Table 22.
INPUT CONFIGURATIONS
CONFIG
FL IN
FR IN
SL IN
SR IN
RL/RC
IN
RR/RC
IN
FC IN
LFE
IN
Stereo
5.1
6.1
or
7.1
Table 21 Input Configuration
The RC channel is accepted either in the RL or RR input, or alternatively in both RL and RR inputs.
Register control bit RCCFG (Table 23) determines which option is used.
OUTPUT CONFIGURATIONS
CONFIG
FL OUT
FR OUT
SL OUT
SR OUT
FC OUT
RC OUT
SUB
OUT
Stereo
2.1
5.1
6.1
Table 22 Output Configuration
By default the Subwoofer channel is directed to the SUB output, which is a lower bandwidth channel
operating at half the PWM frequency of the other channels. Optionally, the subwoofer channel can be
redirected to the RC channel at the full bandwidth.
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REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
1:0
IPCFG[1:0] 01
Input
Configuration
00 = Stereo
01 = 5.1
10 = 6.1
11 = 7.1
2
RCCFG
0
Rear-Centre Input Channel Configuration
0 = Rear-Centre input in Left channel
1 = Rear-Centre input in Right Channel
(Only applicable when operating in 6.1
input mode.)
4:3
OPCFG[1:0] 11
Output
Configuration
00 = Stereo
01 = 2.1
10 = 5.1
11 = 6.1
R3 (03h)
Input/Output
Configuration
5
SUBCFG
0
Subwoofer Channel Configuration
0 = Subwoofer Output on SUB
1 = Subwoofer Output on RC
(Only applicable when operating in 2.1 or
5.1 output mode.)
Table 23 Input and Output Configuration Register
A typical speaker configuration is illustrated in Figure 19.
FL
FC
FR
SL
SR
SUB
RC
Figure 19 Loudspeaker Configuration for 6.1 Output
The WM8608 also supports Stereo input Stereo output via the Bass Management filtering
options, as discussed in Bass Management (page 29). In this case, the output configuration is
set to 2.1.
Where there are a different number of input and output channels, the data is processed as follows.
Refer to the section on Bass Management (page 29) for details on how the sub-channel is created.
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STEREO INPUT STEREO OUTPUT
The Front-Left and Front-Right inputs are passed to the Front-Left and Front-Right Outputs. All other
channels are muted.
STEREO INPUT 2.1 OUTPUT
The Front-Left and Front-Right inputs are passed to the Front-Left and Front-Right Outputs. The low-
frequency contents of the Front inputs, may be optionally mixed and passed to the SUB output. The
Surround, Front Centre and Rear Centre channel outputs are muted.
5.1 INPUT 2.1 OUTPUT
Stereo mix-down is not supported. In this mode, the Front-Left and Front-Right inputs are passed
to the Front-Left and Front-Right Outputs. The LFE and the low-frequency contents of the Front and
Surround inputs, may be optionally mixed and passed to the SUB output. The Surround, Front Centre
and Rear Centre channel outputs are muted.
5.1 INPUT 6.1 OUTPUT
The Front and Surround channel inputs are passed to the Front and Surround channel outputs.
The LFE and the low-frequency contents of the Front and Surround inputs optionally, may be
mixed and passed to the SUB output. The RC OUT channel is obtained from the surround
channels according to the equation:
RC OUT = (SL IN + SR IN)/2
5.1 INPUT 5.1 OUTPUT
The Front and Surround channel inputs are passed to the Front and Surround channel outputs.
The LFE and the low-frequency contents of the Front and Surround inputs, may be optionally
mixed and passed to the SUB output. The Rear-Centre channel is muted.
6.1 INPUT 2.1 OUTPUT
Stereo mix-down is not supported. The Front-Left and Front-Right inputs are passed to the Front-
Left and Front-Right Outputs. The LFE and the low-frequency contents of the Front, Surround and
Rear-centre inputs are optionally mixed and passed to the SUB output. The Surround, Front Centre
and Rear Centre channel outputs are muted.
6.1 INPUT 5.1 OUTPUT
The Front channel inputs are passed to the Front channel outputs. The LFE and the low-frequency
contents of the Front, Surround and Rear-centre inputs, may be optionally mixed and passed to the
SUB output. The RC IN channel is mixed into the SL OUT and SR OUT output channels according to
the equations:
SL OUT = (SL IN + RC IN)/2, SR OUT = (SR IN + RC IN)/2
The Rear-Centre output channel is muted.
6.1 INPUT 6.1 OUTPUT
The Front and Surround channel inputs are passed to the Front and Surround channel outputs.
The LFE and the low-frequency contents of the Front, Surround and Rear-centre inputs, may
be optionally mixed and passed to the SUB output. The RC OUT channel is obtained from
either RL IN or RR IN (dependent on setting of register bit RCFG).
7.1 INPUT 2.1 OUTPUT
Stereo mix-down is not supported. The Front-Left and Front-Right inputs are passed to the Front-
Left and Front-Right outputs. The LFE and the low-frequency contents of the Front, Surround and
Rear inputs, may be optionally mixed and passed to the SUB output. The Surround, Front Centre and
Rear Centre channels are muted.
7.1 INPUT 5.1 OUTPUT
The Front channel inputs are passed to the Front channel outputs. The LFE and the low-
frequency contents of the Front, Surround and Rear inputs, may be optionally mixed and
passed to the SUB output. The RL IN and RL OUT channels are mixed into the SL OUT and
SR OUT channels according to the equations:
SL OUT = (SL IN + RL IN)/2, SR OUT = (SR IN + RR IN)/2
The Rear-Centre output channel is muted.
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7.1 INPUT 6.1 OUTPUT
The Front and Surround channel inputs are passed to the Front and Surround channel outputs.
The LFE and the low-frequency contents of the Front, Surround and Rear inputs, may be
optionally mixed and passed to the SUB output. The RC OUT channel is obtained from:
(RL IN + RR IN)/2
BASS MANAGEMENT
The Bass Management function filters and combines the input signals to produce a low-pass filtered
output for the sub-woofer channel and high-pass filtered outputs for the remaining channels. The
filters have selectable cut-off frequencies to match different types of sub-woofer and satellite
speakers. The filters are designed so that the cut-off frequencies for the high-pass and low-pass
filters remain constant irrespective of the sampling frequency used. 1
st
order filters are used for the
low-pass and high-pass filters.
LFE
FC
SUB
FR
SL
FL
SR
FC
RC
+10dB
+
lp
lp
hp
hp
lp
lp
hp
hp
lp
lp
hp
hp
FL
FR
SL
SR
RC
Figure 20 Bass Management
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The high-pass filters pairs can be bypassed to allow full-range speakers to be used on any of the 3
main output channel pairs. The low-pass outputs from the Front channels can also be disabled to
provide Stereo In Stereo Out capability when full range front speakers are used.
The Bass Management also provides a selectable LFE boost of 10dB via the LFEBOOST control bit.
This is to compensate for the standard practise of recording the LFE channel 10dB down in the mix.
Additional gain-adjust is provided after this block (refer to page 33).
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R13 (0Dh)
Bass
Management
Filter
1:0
LPHPCO[1:0]
01
Low-/High-Pass Cutoff Frequency (-3dB)
00 = 75Hz
01 = 100Hz
10 = 133Hz
11 = 178Hz
2
LFEBOOST
0
LFE Boost Enable
0 = Boost Disabled
1 = 10dB Boost Enabled
Table 24 Bass Management Filter
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R14 (0Eh)
Bass
Management
0
HPENF
1
Front High-Pass Filter
0 = High-Pass Filter bypassed
1 = High-Pass Filter enabled
Filter Bypass
1
HPENS
1
Surround High-Pass Filter
0 = High-Pass Filter bypassed
1 = High-Pass Filter enabled
2
HPENC
1
Front Centre and Rear Centre High-Pass
Filter
0 = High-Pass Filter bypassed
1 = High-Pass Filter enabled
3
LPENF
1
Front Low-Pass Filter Enable
0 = Low-Pass Filter output disabled
1 = Low-Pass Filter output enabled
4
LPENS
1
Surround Low-Pass Filter Enable
0 = Low-Pass Filter output disabled
1 = Low-Pass Filter output enabled
5
LPENC
1
Front Centre and Rear Centre Low-Pass
Filter Enable
0 = Low-Pass Filter output disabled
1 = Low-Pass Filter output enabled
Table 25 Bass Management Filter Bypass
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GRAPHIC EQUALISER
The WM8608 has a 4-band Graphic Equaliser on the front three channels. The three upper bands
are controlled via registers (see Table 26, Table 27, Table 28 and Table 29). The lowest band is
controlled via the subwoofer volume control (see VOLS in Table 32). The function has selectable cut-
off frequencies which are independent of sample rate. The boost/cut for the upper three bands is
controllable in 1.5dB steps from -6dB to +9dB via the EQB control bits.
The front-left and front-right controls are tied together, whilst the front-centre controls can be
independently adjusted.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
3:0 EQ1GF
[3:0]
1111
(Disabled)
Band 1 Front-Left/Front-Right Gain
0000 or 0001 = +9dB
0010 = +7.5dB
... (1.5dB steps)
1011 to 1110 = -6dB
1111 = Disable
R15 (0Fh)
EQ Band 1
Gain Control
7:4 EQ1GFC
[7:4]
1111
(Disabled)
Band 1 Front-Centre Gain
0000 or 0001 = +9dB
0010 = +7.5dB
... (1.5dB steps)
1011 to 1110 = -6dB
1111 = Disable
Table 26 EQ Band 1 Gain Control
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
3:0 EQ2GF
[3:0]
1111
(Disabled)
Band 2 Front-Left/Front-Right Gain
0000 or 0001 = +9dB
0010 = +7.5dB
... (1.5dB steps)
1011 to 1110 = -6dB
1111 = Disable
R16 (10h)
EQ Band 2
Gain Control
7:4 EQ2GFC
[7:4]
1111
(Disabled)
Band 2 Front-Centre Gain
0000 or 0001 = +9dB
0010 = +7.5dB
... (1.5dB steps)
1011 to 1110 = -6dB
1111 = Disable
Table 27 EQ Band 2 Gain Control
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
3:0 EQ3GF
[3:0]
1111
(Disabled)
Band 3 Front-Left/Front-Right Gain
0000 or 0001 = +9dB
0010 = +7.5dB
... (1.5dB steps)
1011 to 1110 = -6dB
1111 = Disable
R17 (11h)
EQ Band 3
Gain Control
7:4 EQ3GFC
[7:4]
1111
(Disabled)
Band 3 Front-Centre Gain
0000 or 0001 = +9dB
0010 = +7.5dB
... (1.5dB steps)
1011 to 1110 = -6dB
1111 = Disable
Table 28 EQ Band 3 Gain Control
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REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0
EQ1CF
1
Band 1 Front-Left/Front Right Centre-
Frequency
0 = High Cutoff (500Hz)
1 = Low Cutoff (250Hz)
1
EQ1CFC
1
Band 1 Front-Centre Centre-Frequency
0 = High Cutoff (500Hz)
1 = Low Cutoff (250Hz)
2
EQ2CF
1
Band 2 Front-Left/Front Right Centre-
Frequency
0 = High Cutoff (2kHz)
1 = Low Cutoff (1kHz)
3
EQ2CFC
1
Band 2 Front-Centre Centre-Frequency
0 = High Cutoff (2kHz)
1 = Low Cutoff (1kHz)
4
EQ3CF
1
Band 3 Front-Left/Front Right Cutoff
Frequency
0 = High Cutoff (8kHz)
1 = Low Cutoff (4kHz)
R18 (12h)
EQ Centre-
Frequency
Control
5
EQ3CFC
1
Band 3 Front-Centre Cutoff Frequency
0 = High Cutoff (8kHz)
1 = Low Cutoff (4kHz)
Table 29 EQ Frequency Control
Band 0 is controlled via the sub-woofer volume control register R11 as described in Table 32. The
functionality to add/subtract the boost/cut setting to the sub-woofer volume must be written into the
software controller for the chip.
The Band 0 Cutoff frequency can be changed using the corner frequency of the low-pass/high-pass
filters as described in Table 24.
DIGITAL LOUDSPEAKER EQUALISER
A loudspeaker equaliser is provided for the front three channels to compensate for high-frequency
variations that can occur when loudspeakers of different impedances are used with different output
filters in typical output stages. The equaliser has selectable cutoff frequencies which are independent
of sample rate. The gain at 20kHz is controllable in 0.5dB steps from -1.5dB to +2dB via the LSEQ
control bit. The settings are applied to all three front channels simultaneously.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0 LSCO 0
LSEQ
Filter
Characteristic
0 = High Cutoff (15kHz)
1 = Low Cutoff (10kHz)
R19 (13h)
Loudspeaker
Equaliser
3:1 LSEQ
[2:0]
100
(Disabled)
High Frequency Equalisation
000 = +2dB
001 = +1.5dB
010 = +1dB
011 = +0.5dB
100 = Disable
101 = -0.5dB
110 = -1dB
111 = -1.5dB
Table 30 Loudspeaker Equaliser
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DIGITAL DEEMPHASIS
The digital `de-emphasis' is used to equalize pre-emphasised digital CD recordings. De-emphasis
filtering is available on the Front-Left and Front-Right channels only, for sample rates of 32kHz,
44.1kHz and 48kHz. The settings are applied to the two channels simultaneously.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R20 (14h)
De-emphasis
0
DEEMP 0
De-emphasis
Control
0 = No De-emphasis
1 = De-emphasis enabled
Table 31 De-emphasis
Refer to Figure 31, Figure 32, Figure 33, Figure 34, Figure 35 and Figure 36 for details of the De-
Emphasis modes at different sample rates.
Note: Using the De-emphasis filters for other sample rates as defined above will result in a frequency
response error as shown in Figure 32, Figure 34 and Figure 36.
DIGITAL VOLUME CONTROL
The volume control allows the gain of each channel to be independently adjusted in 0.5dB steps from
-103.5dB to +24dB. When the Dynamic Peak Compressor (see below) is enabled, gains of greater
than 0dB can be applied without digital clipping occurring. The volume control has a digital zero-cross
circuit which minimises clicks during changing the volume.
An update control bit is provided which allows the volume setting on each channel to be first stored in
an intermediate latch, then afterwards applied simultaneously to all channels. If UPDATE=0, the
Volume value will be written to the pre-latch but not applied to the relevant channel. If UPDATE=1, all
pre-latched values will be applied from the next input sample. The value of UPDATE itself is not
latched.
To prevent audible clicks, the volume control includes a ramp function which automatically ramps the
volume in small steps between register updates. The ramp rate is 256dB/s 5%.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
7:0 VOLFL[7:0]
10110001
(-15dB)
Front-Left Volume in 0.5dB steps.
Refer to Table 14
R4 (04h)
Front-Left
Volume
8 UPDATE
0
Volume
Update
0 = Store FLVOL in intermediate latch
(no gain change)
1 = Store and Update all channel
gains
7:0 VOLFR
[7:0]
10110001
(-15dB)
Front-Right Volume in 0.5dB steps.
Refer to Table 14
R5 (05h)
Front-Right
Volume
8 UPDATE
0
Volume
Update
0 = Store FRVOL in intermediate latch
(no gain change)
1 = Store and Update all channel
gains
7:0 VOLSL
[7:0]
10110001
(-15dB)
Surround-Left Volume in 0.5dB steps.
Refer to Table 14
R6 (06h)
Surround-Left
Volume
8 UPDATE
0
Volume
Update
0 = Store SLVOL in intermediate latch
(no gain change)
1 = Store and Update all channel
gains
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REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
7:0 VOLSR
[7:0]
10110001
(-15dB)
Surround-Right Volume in 0.5dB
steps. Refer to Table 14
R7 (07h)
Surround-
Right Volume
8 UPDATE
0
Volume
Update
0 = Store SRVOL in intermediate latch
(no gain change)
1 = Store and Update all channel
gains
7:0 VOLFC
[7:0]
10110001
(-15dB)
Front-Centre Volume in 0.5dB steps.
Refer to Table 14
R8 (08h)
Front-Centre
Volume
8 UPDATE
0
UPDATE
0 = Store FCVOL in intermediate latch
(no gain change)
1 = Store and Update all channel
gains
7:0 VOLRC
[7:0]
10110001
(-15dB)
Rear-Centre Volume in 0.5dB steps.
Refer to Table 14
R9 (09h)
Rear-Centre
Volume
8 UPDATE
0
UPDATE
0 = Store RCVOL in intermediate latch
(no gain change)
1 = Store and Update all channel
gains
7:0 VOLS
[7:0]
10110001
(-15dB)
Sub Volume in 0.5dB steps. Refer to
Table 14
R10 (0Ah)
Subwoofer
Volume
8 UPDATE
0
UPDATE
0 = Store SVOL in intermediate latch
(no gain change)
1 = Store and Update all channel
gains
Table 32 Volume Control
VOLXX[7:0] VOLUME
LEVEL
00(hex) -dB (mute)
01(hex) -103dB
: :
: :
CF(hex) 0dB
: :
: :
FE(hex) +23.5dB
FF(hex) +24dB
Table 33 Volume Control Levels
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DUAL VOLUME CONTROL
Setting the DVC register bit causes the volume settings to be applied in pairs. For example, the
DVCF causes the Front-Left channel volume settings to be applied to both the Front-Left and Front-
Right channels from the next audio input sample. No update to the VOL registers is required for DVC
to take effect.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0
DVCF
0
Dual Volume Control Front Channels:
0 : Use VOLFR setting for Front-
Right channel
1: Apply VOLFL setting to Front-
Right channel
1
DVCS
0
Dual Volume Control Surround
Channels:
0 : Use VOLSR setting for
Surround-Right channel
1: Apply VOLSL setting to
Surround-Right channel
R11 (0Bh)
Dual Volume
Control
2
DVCC
0
Dual Volume Control Front Centre
and Rear Centre Channels:
0 : Use VOLRC setting for Rear-
Centre channel
1: Apply VOLFC setting to Rear-
Centre channel
Table 34 Dual Volume Control
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SOFT MUTE AND AUTO-MUTE
The WM8608 has a Soft Mute function set by the SMUTE control bit. Figure 21 shows the application
and release of SMUTE while a full amplitude sinusoid is being played at 48kHz sampling rate. When
SMUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC
level of the last input sample. The output will decay towards zero with a time constant of
approximately 64 input samples. When SMUTE is turned off, the output will restart almost
immediately from the current input sample, thus possibly causing a pop sound.
This function is disabled by default.
Figure 21 Application and Release of Soft Mute
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
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An auto-mute function is provided that automatically mutes the output stage when a digital silence
period is detected. Digital silence is defined as a consecutive period of 1024 zero input samples at
the output of the volume control. Auto-mute will be removed as soon as the volume control output
becomes non-zero. (Please note that on the sub channel the noise level is greatly reduced, rather
than complete digital silence.)
To achieve digital silence, you can do one of the following:
Turn on auto-mute and set the volume control to zero.
Turn on auto-mute and input zero data on the serial data input pins with the bass
management filters disabled. (Page 29)
Turn on auto-mute and soft mute.
The auto-mute operates independently across all channel pairs, and can be enabled or disabled on
individual channel pairs.
The mute features maximize the SNR of the PWM amplifier system. Soft-mute will only maximize the
SNR of channel pairs that have auto-mute enabled.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0
SMUTE
0
Digital Soft Mute
0 = disable (signal active)
1= enable
1 AMUTEF
1
Front Auto-mute
0 = disable
1 = enable
2 AMUTES
1 Surround
Auto-mute
0 = disable
1 = enable
3
AMUTEC
1
Front Centre and Rear Centre Auto-
mute
0 = disable
1 = enable
R12 (0Ch)
Mute
4 AMUTESB
1 Subwoofer
Auto-mute
0 = disable
1 = enable
Table 35 Mute
DYNAMIC PEAK COMPRESSOR
The WM8608 includes a Dynamic Peak Compressor for each channel, which prevents the
occurrence of digital clipping when gains in excess of 0dB are applied. The compressor automatically
adjusts the signal amplitude to allow headroom for the LFE boost, sub-woofer mixing, tone controls,
loudspeaker equalisation and digital volume control. The compressor has a programmable limit
threshold, programmable attack and decay time-constants, a frequency-dependent decay mode, and
built-in zero-cross detect. The compressor can be configured either to operate independently on all
channels (DUAL MONO), or on linked channel-pairs (STEREO), e.g. Table 36. The following
channels are paired together: Front-Left and Front-Right, Surround-Left and Surround-Right, Front-
Centre and Rear-Centre.
COMPRESSOR THRESHOLD
The compressor has a digital peak detector which tracks the maximum input signal level at the
output of the volume control. With reference to Figure 22, if this signal is below the threshold set by
control bit THRESH, the compressor operates transparently with no change to the signal level.
However, if peak signal rises above the threshold, the gain through the compressor is modified so
that the upper part of the curve is followed. This ensures that the output signal does not exceed 0dB.
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ATTACK AND DECAY TIMES
The attack time-constant ATK controls how fast the gain is reduced when the signal goes above the
threshold. It is defined as the time taken for the gain to reduce by 6dB. Normally a short attack time-
constant is used to prevent the signal clipping when a high-amplitude transient occurs.
The decay time-constant DCY controls how fast the gain is increased when the signal begins to fall
again. It is defined as the time taken for the gain to increase by 6dB. Normally, the decay time-
constant is much longer than the attack time-constant, to prevent the input signal from entering
repeated limiting cycles.
The frequency-dependent decay feature automatically detects the input frequency and sets the
decay time to decay slower for low frequency signals. This reduces low-frequency signal distortion by
preserving the waveform of each input cycle, whilst allowing the compressor to respond quickly to
high frequency transients. This feature is enabled via the FDEP control bit.
ZERO-CROSS
The Dynamic Peak Compressor has a zero cross detector to prevent gain changes introducing clicks
in the signal. The ZC is controlled by the same register R25 used in the volume control.
0dB
Output Level
(dB)
Peak Input Level [dB]
THRESH
[dB]
0
-6
-12
+6
+12
-18
-24
-30
-36
-12
-18
-24
-30
-36
0dB
-6dB
-12dB
+6dB
+12dB
typical
Volume Control
Setting
Figure 22 Dynamic Peak Compressor Characteristics
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0 PLENF
1
Front Channel Compressor Enable
0 = disable
1 = enable
1
PLENS
1
Surround Channel Compressor
Enable
0 = disable
1 = enable
R21 (15h)
Front,
Surround,
Front Centre
and Rear
Centre
Channel
Dynamic
Peak
Compressor
2
PLENC
1
Front Centre and Rear Centre
Channel Compressor Enable
0 = disable
1 = enable
Table 36 Front, Surround, Front Centre and Rear Centre Channel Dynamic Peak
Compressor (1)
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REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R22 (16h)
Front,
Surround,
Front Centre
and
Rear Centre
Channel
Dynamic
Peak
Compressor
2:0
ATK[2:0]
010
Front, Surround, Front Centre and
Rear Centre Channel Attack Rate
000 = 170s
001 = 330s
010 = 670s
011 = 1.33ms
100 = 2.67ms
101 = 5.33ms
110 = 10.7ms
111 = 20.1ms
5:3
DCY[2:0]
011
Front, Surround, Front Centre and
Rear Centre Channel Decay Rate
000 = 340ms
001 = 680ms
010 = 1.36s
011 = 2.73s
100 = 5,46s
101, 110, 111 = 10.9s
7:6
THRESH[1:0]
11
Front, Surround, Front Centre and
Rear Centre Channel Compressor
Thresholds
00 = -12dB
01 = -9dB
10 = -6dB
11 = -3dB
8
FDEP
0
Frequency-dependent
decay
0 = disable
1 = enable
Table 37 Front, Surround, Front Centre and Rear Centre Channel Dynamic Peak
Compressor (2)
Note: The Dynamic Peak Compressors can be enabled independently for each channel pair (e.g.
FL/FR, SL/SR). All channels use the same characteristics (e.g. Attack Rate).
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R23 (17h)
Sub Channel
Dynamic
Peak
Compressor
0 PLENSUB
1
Sub Channel Compressor Enable
0 = disable
1 = enable
Table 38 Subwoofer Channel Dynamic Peak Compressor (1)
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REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
2:0
ATK[2:0]
010
Sub Channel Attack Rate
000 = 170s
001 = 330s
010 = 670s
011 = 1.33ms
100 = 2.67ms
101 = 5.33ms
110 = 10.7ms
111 = 20.1ms
5:3
DCY[2:0]
011
Sub Channel Decay Rate
000 = 340ms
001 = 680ms
010 = 1.36s
011 = 2.73s
100 = 5,46s
101, 110, 111 = 10.9s
7:6 THRESH[1:0] 11
Sub Channel Compressor Thresholds
00 = -12dB
01 = -9dB
10 = -6dB
11 = -3dB
R24 (18h)
Sub Channel
Dynamic
Peak
Compressor
8 FDEP
0
Frequency-dependent
decay
0 = disable
1 = enable
Table 39 Subwoofer Channel Dynamic Peak Compressor (2)
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ZERO-CROSS DETECT
The Dynamic Peak Compressor has a zero-cross detect that minimises clicks during gain changes.
The zero-cross detect can be enabled/disabled in channel-pairs. The zero-cross has a timeout
feature which ensures that the volume will change even if the input has a large DC offset. Once a
new gain has been requested from the Dynamic Peak Compressor, the zero-cross detector will wait
for a zero-cross for 25 to 50
ms before applying the gain change.
Note that the zero-cross settings programmed here also apply to the Dynamic Peak Compressor.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0
ZCF
1
Zero-Cross Enable Front Channels:
0 : Disable Zero-Cross
1: Enable Zero-Cross
1
ZCS
1
Zero-Cross Enable Surround
Channels:
0 : Disable Zero-Cross
1: Enable Zero-Cross
2
ZCC
1
Zero-Cross Enable Front Centre and
Rear Centre Channels:
0 : Disable Zero-Cross
1: Enable Zero-Cross
3
ZCSUB
1
Zero-Cross Enable Sub Channel:
0 : Disable Zero-Cross
1: Enable Zero-Cross
R25 (19h)
Volume
Control Zero-
Cross
4
ZCT
1
Zero Cross Timeout Enable:
0 : Disable Zero-Cross Timeout
1: Enable Zero-Cross Timeout
Table 40 Volume Control Zero-Cross
INTERPOLATION FILTERS
The WM8608 uses two types of interpolation filters, selected according to sampling frequency, as
shown in Table 40.
SAMPLING FREQUENCY
FILTER TYPE
INTERPOLATION
Main
Channels
Main
Channels
SUB
32kHz 0
12x
6x
44.1kHz 0
8x
4x
48kHz 0
8x
4x
88.2kHz 0
4x
2x
96kHz 0
4x
2x
176.4kHz 1
2x
1x
192kHz 1
2x
1x
Table 41 Interpolation Filter Types
Note: If the Subwoofer channel is redirected into the Rear Centre (RC) channel the main channel
characteristics apply.
FILTER TYPE 0
PARAMETER SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Filter
Passband
0.05 dB
0.454
f
s
Stopband
-3dB
0.484 f
s
Passband ripple
0.05 dB
Stopband Attenuation
f
>
0.546fs
-60
dB
Group Delay
23
samples
Table 42 Digital Filter 0 Characteristics
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FILTER TYPE 1
PARAMETER SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Filter
Passband
0.242
f
s
Stopband
0.723 f
s
Passband ripple
0.05 dB
Stopband Attenuation
-60
dB
Group Delay
6
samples
Table 43 Digital Filter 1 Characteristics
The subwoofer filter characteristic is defined in Table 44
FILTER TYPE SUBWOOFER
PARAMETER SYMBOL
TEST
CONDITIONS
-0.1dB
-3dB
UNIT
Sample Rate
32k
2.0
10.7
kHz
44k1
2.7
14.5
kHz
48k
3.0
15.8
kHz
88k2
6.1
32.1
kHz
96k
6.8
34.9
kHz
176k
*
*
kHz
192k
*
*
kHz
Table 44 Subwoofer Filter Characteristic
Note: * indicates no interpolation filters
PCM TO PWM CONVERTER
The PCM to PWM converter converters the Pulse-Code Modulated (PCM) signal into a highly linear
Pulse-Width Modulated (PWM) signal. Table 45 defines the Pulse Repetition Frequency, (PRF),
output clock rate (OBCLK) and minimum pulse width for each supported sampling frequency.
t
PWMP
t
PWMP
t
PWMM
t
PWMM
t
OBCLK
Figure 23 PCM to PWM Converter
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The PRF Frequency (T
PWMP
) of the Sub-woofer channel is half of the frequency defined in Table 45
in order to reduce power dissipation in the output stage.
PRF
(1/T
PWMP
)
Main Channel
SUB
OUTPUT BITCLOCK
FREQUENCY
(1/T
OBCLK
)
MINIMUM PULSE
WIDTH (T
PWMM
)
SAMPLING
FREQUENCY
[kHz] [kHz]
[MHz]
[ns]
32kHz 384 192
98.304
122
44.1kHz 352.8 176.4
90.3168
133
48kHz 384 192
98.304
122
88.2kHz 352.8 176.4
90.3168
133
96kHz 384 192
98.304
122
176.4kHz 352.8 176.4
90.3168
133
192kHz 384 192
98.304
122
Table 45 Output Bitclock Frequency
Notes:
1. The correct Output Bitclock Frequency (T
OBCLK
) is generated by the built-in PLL of the WM8608
device. The incoming clock must meet the jitter specification defined in Table 3.
OUTPUT PHASE
The Phase control word determines whether the output of each channel is non-inverted or inverted.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
Bit Channel
Phase
0 FL
1
=
invert
1 FR
1
=
invert
2 SL
1
=
invert
3 SR
1
=
invert
4 FC
1
=
invert
5 RC
1
=
invert
R26 (1Ah)
Output Phase
6:0 PH[6:0] 0000000
6 SUB
1
=
invert
Table 46 Phase
WM8608
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PWM OUTPUT CONFIGURATION
Two different PWM output formats are supported. These are:
CMOS
or
LVDS
Tri-state outputs to support power-down.
The PWM output format can be defined with the LVDS and PWMCFG setting defined in Table 47.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0
LVDS
0
Output PAD configuration
0 = CMOS
1 = LVDS
2:1
PWMCFG
[1:0]
00
PWM Output State for LVDS=0 when
output disabled or in standby mode:
01 = all PWM Outputs high
00 = all PWM Outputs low
10, 11 = high impedance
For LVDS=1 when output disabled or in
standby mode, the output state is high
impedance.
3
PWMPH
1
PWM Output Phase
0 = PWM outputs in phase
1 = PWM outputs phase shifted to each
other
R27 (1Bh)
PWM Output
Configuration
7
PWMCLK
0
PWM Output Clock
0 = disabled
1 = enabled
Table 47 PWM Output Configuration
OUTPUT CONFIGURATION
If required the WM8608 device can be disabled in a system by setting the TRI bit as defined in Table
48. Setting the TRI bit will set all output pins of the device to high impedance.
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R28 (1Ch)
Output
Configuration
0
TRI
0
Output Pins Mode
0 = Normal
1 = High Impedance
Table 48 Output Configuration
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STANDBY, OUTPUT DISABLE AND RESET MODES
STANDBY
Setting the STDBY register bit selects a low power mode, and immediately configures the output to
produce an output defined in Table 47 (PWMCFG). All trace of the previous input samples is
removed, but all control register settings are preserved.
OUTPUT DISABLE (OPDIS) PIN AND REGISTER (OPDISR)
The OPDIS pin is provided to immediately shutdown the outputs, primarily for their protection. This is
useful for short-circuit or thermal protection. The OPDIS pin can be configured in 2 modes:
Synchronous
Latched
In synchronous mode if OPDIS is high for longer than 100ns the outputs will be disabled. They will be
enabled again at the end of a processing frame when OPDIS goes low for longer than 100ns.
In latched mode if OPDIS is high for longer than 100ns, the outputs will be disabled and will remain
off until OPDIS is reset via the control interface and the end of a processing frame is reached (Table
50).
The output disable register (OPDISR) also allows the PWM outputs to be disabled via a register
write. If OPDISR is set the PWM outputs will be disabled at the end of the next processing frame and
enabled if OPDISR is reset at the end of the next processing frame.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0 STDBY
1
Standby
select:
0 : Normal Mode
1: Standby Mode
1 OPDISR
0
Output
disable
register
0: Normal mode
1: PWM output disabled
R29 (1Dh)
Power Down
2 MENA
1
OPDIS
Mode
0 : Synchronous
1: Latched, reset via Control I/F
Table 49 Power Down
EXTERNAL APPLICATION POWER-DOWN (EAPDB) PIN
The state of the output pin EAPDB shows whether the device is disabled (i.e. OPDIS input pin active
or STDBY register set).
EAPDB STATE DESCRIPTION
1
The device is operating
correctly
External
Application
Power Down
0
(default)
The outputs are disabled or
the WM8608 device is in
Standby (default) mode
Table 50 EAPDB Pin
WM8608
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RESET
The WM8608 device can be reset writing to the Reset register as defined in Table 51.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0
RLENA
0
Writing 1 to bit 0 of the register will
reset OPDIS
R30 (1Eh)
Reset
all
RESET
0
Writing all 1's to the register will
reset the device and register
settings
Table 51 Reset
Note: RESET or RLENA will be applied at the end of the register write and released at the beginning
of the next register write. I.e. to reset the OPDIS register write 1 to bit 0 of the Reset register and
them write 0 to bit 0.
EXTERNAL POWER SUPPLY CLOCK
The WM8608 device can generate a clock signal for an external PSU (Power Supply Unit) which is
available at the CLKPSU pin.
CLKPSU
t
PCLKPSU
t
HCLKPSU
Figure 24 External Power Supply Clock
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
0
ENPSU 0
CLKPSU
enable
1: enabled
2:1
CLKPSU[1:0] 00
CLKPSU
frequency
00: CLKPSU = f
PRF
01: CLKPSU = f
PRF
/2
10: CLKPSU = f
PRF
/4
11: CLKPSU = f
PRF
/6
R31 (1Fh)
PSU
4:3
DCYPSU[1:0]
00
CLKPSU duty cycle
00: t
hclkpsu
/t
pclkpsu
= 0.5 (50%)
01: t
hclkpsu
/t
pclkpsu
= 0.125 (12.5%)
10: t
hclkpsu
/t
pclkpsu
= 0.0625 (6.25%)
11: t
hclkpsu
/t
pclkpsu
= 0.03125 (3.125%)
Table 52 PSU Clock
Note: See Table 45 for specification of f
PRF
.
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REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description.
There are 32 registers with 9 bits per register. These can be controlled using the Control Interface.
REGISTER ADDRESS
REMARKS
BIT[8] BIT[7] BIT[6] BIT[5] BIT[4] BIT[3] BIT[2] BIT[1] BIT[0] DEFAULT PAGE
REF
R0 (00h)
00_0000
Clocking 0
0 0 0 0
CLKDIV2
MEDGE
MPEG
CMAST
0_0000_0011
21
R1 (01h)
00_0001
Sample Rate
0
0 0 0
SRDET
SR
0_0001_0000
21
R2 (02h)
00_0010
Audio IF Format
BCLKINV
MS LRSWAP
SUBSWP
LRP
WL
FORMAT
0_0000_1010
20
R3 (03h)
00_0011
Input/Output Configuration
0
0 0
SUBCFG
OPCFG
RCCFG IPCFG
0_0001_1001
27
R4 (04h)
00_0100
Front-Left Volume
UPDATE
VOLFL (Front Left) Volume
0_1011_0001
33
R5 (05h)
00_0101
Front-Right Volume
UPDATE
VOLFR (Front Right) Volume
0_1011_0001
33
R6 (06h)
00_0110
Surround-Left Volume
UPDATE
VOLSL (Surround Left) Volume
0_1011_0001
33
R7 (07h)
00_0111
Surround-Right Volume UPDATE
VOLSR (Surround Right) Volume
0_1011_0001
34
R8 (08h)
00_1000
Front-Centre Volume
UPDATE
VOLFC (Front Centre) Volume
0_1011_0001
34
R9 (09h)
00_1001
Rear-Centre Volume
UPDATE
VOLRC (Rear Centre) Volume
0_1011_0001
34
R10 (0Ah)
00_1010
Subwoofer Volume
UPDATE
VOLS (Subwoofer) Volume
0_1011_0001
34
R11 (0Bh)
00_1011
Dual Volume Control
0
0 0 0 0 0
DVCC
DVCS
DVCF
0_0000_0000
35
R12 (0Ch)
00_1100
Mute 0
0 0 0
AMUTESB
AMUTEC AMUTES AMUTEF SMUTE 0_0001_1110
37
R13 (0Dh)
00_1101
Bass (1)
0
0 0 0 0 0
LFEBOOST
LPHPCO 0_0000_0001 30
R14 (0Eh)
00_1110
Bass (2)
0
0 0
LPENC
LPENS
LPENF
HPENC
HPENS
HPENF
0_0011_1111
30
R15 (0Fh)
00_1111
EQ Band 1 Gain Control
0 EQ1GFC
EQ1GF
0_1111_1111
31
R16 (10h)
01_0000
EQ Band 2 Gain Control
0 EQ2GFC
EQ2GF
0_1111_1111
31
R17 (11h)
01_0001
EQ Band 3 Gain Control
0
EQ3GFC EQ3GF
0_1111_1111
31
R18 (12h)
01_0010
EQ Frequency Control
0
0
0
EQ3CFC EQ3CF EQ2CFC EQ2CF EQ1CFC EQ1CF 0_0011_1111
32
R19(13h)
01_0011
Speaker Equaliser
0
0 0 0 0
LSEQ
LSCO
0_0000_1000
32
R20 (14h)
01_0100
Deemphasis 0
0 0 0 0 0 0 0
DEEMPH
0_0000_0000
33
R21 (15h)
01_0101
Peak Compressor F, S, C (1)
0
0 0 0 0 0
PLENC
PLENS
PLENF
0_0000_0111
38
R22 (16h)
01_0110
Peak Compressor F, S, C, (2)
FDEP
THRESH DCY
ATK
0_1101_1010
39
R23 (17h)
01_0111
Peak Compressor SUB (1)
0
0 0 0 0 0 0 0
PLENSUB
0_0000_0001 39
R24 (18h)
01_1000
Peak Compressor SUB (2)
FDEP
THRESH DCY
ATK
0_1101_1010
40
R25 (19h)
01_1001
Zero Cross
0
0 0 0
ZCT
ZCSUB
ZCC
ZCS
ZCF
0_0001_1111
41
R26 (1Ah)
01_1010
Output phase
0
0 PH
0_0000_0000
43
R27 (1Bh)
01_1011
PWM Output Config
0
PWMCLK
0
0
0 PWMPH PWMCFG LVDS
0_0000_1000 44
R28 (1Ch)
01_1100
Output Config
0
0 0 0 0 0 0
0
TRI 0_0000_0000 44
R29 (1Dh)
01_1101
Power Down
0
0 0 0 0 0
MENA
OPDISR
STDBY
0_0000_0101
45
R30 (1Eh)
01_1110
Reset 0
0 0 0 0 0 0 0
RLENA
0_0000_0000
46
R31 (1Fh)
01_1111
PSU 0
0 0 0 DCYPSU
CLKPSU
ENPSU
0_0000_0000
46
R32 (20h)
10_0000
Synchroniser (1)
0
0 0
HOLD GMAX
GMIN SYNCEN
0_0001_0101
24
R33 (21h)
10_0001
Synchroniser (2)
0
0 0 0 0 0
SYNTO
0_0000_0100
24
Table 53 Register Map Description
WM8608
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DIGITAL FILTER CHARACTERISTICS
FILTER RESPONSES
-80
-70
-60
-50
-40
-30
-20
-10
0
10
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Res
p
ons
e
(dB
)
Figure 25 Digital Filter Frequency Response 32kHz
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Res
pons
e (dB
)
Figure 26 Digital Filter Ripple 32kHz
-80
-70
-60
-50
-40
-30
-20
-10
0
10
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
R
e
s
pon
s
e
(dB
)
Figure 27 Digital Filter Frequency Response 44.1, 48
and 96kHz
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Res
p
ons
e (dB
)
Figure 28 Digital Filter Ripple 44.1, 48 and 96kHz
-80
-70
-60
-50
-40
-30
-20
-10
0
10
0
0.2
0.4
0.6
0.8
1
Frequency (Fs)
Res
p
ons
e
(dB
)
Figure 29 Digital Filter Frequency Response 176.4kHz
and 192kHz
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Res
pons
e (dB
)
Figure 30 Digital filter Ripple 176.4kHz and 192kHz
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DIGITAL DE-EMPHASIS CHARACTERISTICS
-12
-10
-8
-6
-4
-2
0
0
2000
4000
6000
8000
10000
12000
14000
16000
Frequency (Hz)
R
e
sp
o
n
se
(
d
B
)
Figure 31 De-Emphasis Frequency Response (32kHz)
-6
-5
-4
-3
-2
-1
0
1
0
2000
4000
6000
8000
10000
12000
14000
16000
Frequency (Hz)
R
e
sp
o
n
se
(
d
B)
Figure 32 De-Emphasis Error (32kHz)
-12
-10
-8
-6
-4
-2
0
0
5000
10000
15000
20000
Frequency (Hz)
Re
s
p
o
n
s
e
(
d
B
)
Figure 33 De-Emphasis Frequency Response (44.1kHz)
-6
-5
-4
-3
-2
-1
0
1
0
5000
10000
15000
20000
Frequency (Hz)
R
e
s
pons
e
(dB
)
Figure 34 De-Emphasis Error (44.1kHz)
-12
-10
-8
-6
-4
-2
0
0
5000
10000
15000
20000
Frequency (Hz)
R
e
s
pons
e
(dB
)
Figure 35 De-Emphasis Frequency Response (48kHz)
-6
-5
-4
-3
-2
-1
0
1
0
5000
10000
15000
20000
Frequency (Hz)
R
e
s
pons
e
(dB
)
Figure 36 De-Emphasis Error (48kHz)
WM8608
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APPLICATION NOTES
START-UP
The WM8608 per default is switched off and the PWM output pins are static high, to protect any
external circuit. When the device has been properly initialized and the output configuration has been
defined then the device can safely be switched on. A typical start-up sequence is show in Figure 37.
Figure 37 WM8608 Start-up
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POWER SUPPLY CONNECTIONS
The WM8608 has got 3 individual power supplies. Figure 38 shows how these power supplies are
connected and used on the chip and package.
WM8608
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Figure 38 WM8608 Power Supply Connections
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 39 WM8608 External Component Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE
SUGGESTED VALUE
DESCRIPTION
Y1
24.576 / 27.000MHz
Crystal (15pF load, 500W)
C1, C2
22pF
Capacitor NP0 0603
C3 4.7F
Capacitor Y5V 0805
C4-C10 0.1F
Capacitor X7R 0603
Table 54 External Components Description
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PACKAGE DIMENSIONS
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
DM004.C
FT: 48 PIN TQFP (7 x 7 x 1.0 mm)
Symbols
Dimensions
(mm)
MIN
NOM
MAX
A
-----
-----
1.20
A
1
0.05
-----
0.15
A
2
0.95
1.00
1.05
b
0.17
0.22
0.27
c
0.09
-----
0.20
D
9.00 BSC
D
1
7.00 BSC
E
9.00 BSC
E
1
7.00 BSC
e
0.50 BSC
L
0.45
0.60
0.75
0
o
3.5
o
7
o
Tolerances of Form and Position
ccc
0.08
REF:
JEDEC.95, MS-026
25
36
e
b
12
1
D1
D
E1
E
13
24
37
48
A
A2
A1
SEATING PLANE
ccc C
-C-
c
L
WM8608
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IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
Document Outline
- WM8608
- 5 to 7.1 Channel PWM Controller
- DESCRIPTION
- FEATURES
- APPLICATIONS
- TABLE OF CONTENTS
- PIN CONFIGURATION
- ORDERING INFORMATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TERMINOLOGY
- POWER CONSUMPTION
- SIGNAL TIMING REQUIREMENTS
- POWER SUPPLY
- MASTER CLOCK TIMING
- AUDIO INTERFACE TIMING MASTER MODE
- AUDIO INTERFACE TIMING SLAVE MODE
- CONTROL INTERFACE TIMING 3-WIRE MODE
- CONTROL INTERFACE TIMING 2-WIRE MODE
- PWM OUTPUT TIMING
- DEVICE DESCRIPTION
- INTRODUCTION
- SIGNAL PATH
- DIGITAL AUDIO INTERFACE
- AUDIO INTERFACE CONTROL
- MASTER CLOCK AND AUDIO SAMPLE RATES
- SYNCHRONISER
- CONTROL INTERFACE OPERATION
- INPUT PROCESSOR
- BASS MANAGEMENT
- GRAPHIC EQUALISER
- DIGITAL DEEMPHASIS
- DIGITAL VOLUME CONTROL
- SOFT MUTE AND AUTO-MUTE
- DYNAMIC PEAK COMPRESSOR
- INTERPOLATION FILTERS
- PCM TO PWM CONVERTER
- STANDBY, OUTPUT DISABLE AND RESET MODES
- EXTERNAL POWER SUPPLY CLOCK
- REGISTER MAP
- DIGITAL FILTER CHARACTERISTICS
- FILTER RESPONSES
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