Document Outline
- WM8728
- 24-bit,192kHz Stereo DAC with Volume Control andDSD Support
- DESCRIPTION
- FEATURES
- APPLICATIONS
- BLOCK DIAGRAM
- PIN CONFIGURATION
- ORDERING INFORMATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- DC ELECTRICAL CHARACTERISTICS
- ELECTRICAL CHARACTERISTICS
- TERMINOLOGY
- MASTER CLOCK TIMING
- DIGITAL AUDIO INTERFACE
- DSD AUDIO MONOPHASE INTERFACE
- POWER SUPPLY TIMING
- DSD AUDIO BIPHASE INTERFACE
- MPU 3-WIRE INTERFACE TIMING
- MPU 2-WIRE INTERFACE TIMING
- DEVICE DESCRIPTION
- INTRODUCTION
- CLOCKING SCHEMES
- DIGITAL AUDIO INTERFACE
- AUDIO DATA SAMPLING RATES
- HARDWARE DSD MODE
- HARDWARE CONTROL MODES
- SOFTWARE CONTROL INTERFACE
- REGISTER MAP
- ATTENUATION CONTROL
- DIGITAL FILTER CHARACTERISTICS
- DAC FILTER RESPONSES
- DIGITAL DE-EMPHASIS CHARACTERISTICS
- DSD MODE CHARACTERISTICS
- APPLICATIONS INFORMATION
- RECOMMENDED EXTERNAL COMPONENTS (PCM AUDIO)
- RECOMMENDED EXTERNAL COMPONENTS VALUES
- RECOMMENDED EXTERNAL COMPONENTS (DSD AUDIO)
- RECOMMENDED EXTERNAL COMPONENTS VALUES FOR DSD
- RECOMMENDED DSD CONNECTIONS
- RECOMMENDED ANALOGUE LOW PASS FILTER FOR PCM DATA FORMAT (OPTIONAL)
- PACKAGE DIMENSIONS
- IMPORTANT NOTICE
WM8728
24-bit, 192kHz Stereo DAC with
Volume Control andDSD Support
WOLFSON MICROELECTRONICS plc
w :: www.wolfsonmicro.com
Production Data, December 2002, Rev 3.1
Copyright
2002 Wolfson Microelectronics plc
DESCRIPTION
The WM8728 is a high performance stereo DAC designed
for audio applications such as DVD, home theatre systems,
and digital TV. The WM8728 supports PCM data input word
lengths from 16 to 32-bits and sampling rates up to 192kHz.
Alternatively the WM8728 can operate in DSD compatible
mode where a 64x bitstream is input for each channel. The
WM8728
consists
of
a
serial
interface
port,
digital
interpolation filters, multi-bit sigma delta modulators and
stereo DAC in a small 20-pin SSOP package. The WM8728
also includes a digitally controllable mute and attenuate
function for eachchannel.
The WM8728 supports a variety of connection schemes for
audio DAC control. The 2 or 3-wire MPU serial port provides
access to a wide range of features including on-chip mute,
attenuation and phase reversal. A hardware controllable
interface is also available (DSD operation is only possible in
hardware mode).
The WM8728 is an ideal device to interface to AC-3
,
DTS
, and MPEG audio decoders for surround sound
applications, or for use in DVD players supporting DVD-A.
FEATURES
Stereo DAC with24 bit PCM or single bit DSD operation
Audio Performance
-
106dB SNR (`A' weighted @ 48kHz) DAC
-
-97dB THD
DAC Sampling Frequency: 8kHz - 192kHz
2 or 3-Wire Serial Control Interface or Hardware Control
Programmable Audio Data Interface Modes
-
I
2
S, Left, Right Justified, DSP
-
16/20/24/32 bit Word Lengths
Independent Digital Volume Control on EachChannel with
127.5dB Range in 0.5dB Steps
3.0V - 5.5V Supply Operation
20-pin SSOP Package
Exceeds Dolby Class A Performance Requirements
APPLICATIONS
DVD-Audio and DVD `Universal' Players
Home theatre systems
Digital TV
Digital broadcast receivers
BLOCK DIAGRAM
SERIAL
INTERFACE
MUTE/
ATTEN
CONTROL INTERFACE
BCKIN
SIGMA
DELTA
MODULATOR
LRCIN
DIN
MUTE/
ATTEN
SIGMA
DELTA
MODULATOR
DIGITAL FILTERS
MCLK
DVDD
AVDD
MUTEB
SDIDEM
SCKDSD
LATI2S
MODE
CSBIWL
ZERO
VOUTL
VOUTR
VMID
AGND
DGND
LOW
PASS
FILTER
LOW
PASS
FILTER
RIGHT
DAC
LEFT
DAC
MUX
MUX
PCM/DSD
WM8728
VREFP VREFN
w
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PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM8728EDS
-25 to +85
o
C
20-pin SSOP
WM8728EDS/R
-25 to +85
o
C
20-pin SSOP
(tape and reel)
MUTEB
CSBIWL
VREFP
MODE
LATI2S
DGND
BCKIN
LRCIN
VOUTL
VMID
VREFN
AGND
WM8728
16
15
14
20
19
18
17
5
6
7
1
2
3
4
DVDD
ZERO
MCLK
DIN
13
12
11
8
9
10
AVDD
VOUTR
SDIDEM
SCKDSD
Note:
Reel quantity = 2,000
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
LRCIN
Digital Input
DAC Sample Rate Clock Input: PCM Input Mode
Right Channel DSD Bitstream Input: DSD Input Mode
2
DIN
Digital Input
Serial Audio Data Input: PCM Input Mode
Left Channel DSD Bitstream Input: DSD Input Mode
3
BCKIN
Digital Input
Audio Data Bit Clock Input
4
MCLK
Digital Input
Master Clock Input
5
ZERO
Digital Output (Open drain)
Infinite ZERO Detect Flag (L = IDZ detected, H = IDZ not detected).
6
DGND
Supply
Digital Ground Supply
7
DVDD
Supply
Digital Positive Supply
8
VOUTR
Analogue Output
Right Channel DAC Output
9
AGND
Supply
Analogue Ground Supply
10
AVDD
Supply
Analogue Positive Supply
11
VOUTL
Analogue Output
Left Channel DAC Output
12
VMID
Analogue Output
Mid Rail Decoupling Point
13
VREFN
Supply
DAC Negative Reference normally AGND, must not be below AGND
14
VREFP
Supply
DAC Positive Reference normally AVDD, must not be above AVDD
15
CSBIWL
Digital Input
(pull-up)
Software Mode: 3-Wire Serial Control Chip Select
Hardware Mode: Input Word Length
16
MODE
Digital Input (pull-down)
Control Mode Selection (L = Hardware, H = Software)
17
MUTEB
Digital Bi-directional
Mute Control (L = Mute on, H = Mute off, Z = Automute Enabled)
18
SDIDEM
Digital Bi-directional
Software Mode: 3 or 2-Wire Serial Control Data Input:
Hardware Mode: De-Emphasis Select
19
SCKDSD
Digital Input
(pull-down)
Software Mode: 3 or 2-Wire Serial Control Clock Input
Hardware Mode: DSD Bitstream Operation Select
20
LATI2S
Digital Input
(pull-up)
Software Mode 3-Wire Serial Control Load Input
Hardware Mode: Input Data Format Selection
Note:
Digital input pins have Schmitt trigger input buffers.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
The WM8728 has been classified as MSL1, which has an unlimited floor life at <30
o
C / 85% Relative Humidity and therefore will
not be supplied in moisture barrier bags.
CONDITION
MIN
MAX
Digital supply voltage
-0.3V
+7V
Analogue supply voltage
-0.3V
+7V
Voltage range digital inputs
DGND -0.3V
DVDD +0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
Master Clock Frequency
50MHz
Operating temperature range, T
A
-25
C
+85
C
Storage temperature prior to soldering
30
C max / 85% RH max
Storage temperature after soldering
-65
C
+150
C
Package body temperature (soldering 10 seconds)
+260
C
Package body temperature (soldering 2 minutes)
+183
C
Note:
Analogue and digital grounds must always be within 0.3V of each other.
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DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range
DVDD
3.0
5.5
V
Analogue supply range
AVDD
3.0
5.5
V
Ground
AGND, DGND
0
V
Difference DGND to AGND
-0.3
0
+0.3
V
Analogue supply current
AVDD = 5V
19
mA
Digital supply current
DVDD = 5V
8
mA
Analogue supply current
AVDD = 3.3V
18
mA
Digital supply current
DVDD = 3.3V
4
mA
Note:
DVDD supply needs to be active before AVDD supply for correct device power on reset. See Power Supply Timing section.
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (TTL Levels)
Input LOW level
V
IL
0.8
V
Input HIGH level
V
IH
2.0
V
Output LOW
V
OL
I
OL
= 1mA
DGND + 0.3V
V
Output HIGH
V
OH
I
OH
= 1mA
DVDD 0.3V
V
Analogue Reference Levels
Reference voltage
VMID
(VREFP -
VREFN)/2 -
50mV
(VREFP -
VREFN)/2
(VREFP -
VREFN)/2 +
50mV
V
Potential divider resistance
R
VMID
10k
ohms
DAC Output (Load= 10k ohms. 50pF)
0dBFs Full scale output voltage
At DAC outputs
1.1 x
AVDD/5
Vrms
SNR (Note 1,2,3)
A-weighted,
@ fs = 48kHz
100
106
dB
SNR (Note 1,2,3)
A-weighted
@ fs = 96kHz
106
dB
SNR (Note 1,2,3)
A-weighted
@ fs = 192kHz
106
dB
SNR (Note 1,2,3)
A-weighted,
@ fs = 48kHz
AVDD, DVDD = 3.3V
102
dB
SNR (Note 1,2,3)
A-weighted
@ fs = 96kHz
AVDD, DVDD = 3.3V
102
dB
SNR (Note 1,2,3)
Non `A' weigh ted @ fs
= 48kHz
103
dB
THD (Note 1,2,3)
1kHz, 0dBFs
-97
dB
THD+N (Dynamic range, Note 2)
1kHz, -60dBFs
100
106
dB
DAC channel separation
100
dB
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Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Load = 10k Ohms,
0dBFS
1.1
V
RMS
Output level
Load = 10k Ohms,
0dBFS,
(AVDD = 3.3V)
0.726
V
RMS
Gain mismatch
channel-to-channel
1
%FSR
To midrail or a.c.
coupled
1
koh ms
Minimum resistance load
To midrail or a.c.
coupled
(AVDD = 3.3V)
600
ohms
Maximum capacitance load
5V or 3.3V
100
pF
Output d.c. level
(VREFP -
VREFN)/2
V
Power On Reset (POR)
POR threshold
2.4
V
Notes:
1.
Ratio of output level with1kHz full scale input, to the output level withall ZEROS into the digital input, over a 20Hz to
20kHz bandwidth.
2.
All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification
values.
3.
VMID decoupled with10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1.
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the output with a
ZERO signal applied. (No Auto-ZERO or Automute function is employed in achieving these results).
2.
Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4.
Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5.
Channel Separation (dB) - Also known as Cross Talk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full-scale signal down one channel and measuring the other.
WM8728
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MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing Information
MCLK Master clock pulse widthhigh
t
MCLKH
13
ns
MCLK Master clock pulse widthlow
t
MCLKL
13
ns
MCLK Master clock cycle time
t
MCLKY
26
ns
MCLK Duty cycle
40:60
60:40
DIGITAL AUDIO INTERFACE
BCKIN
LRCIN
t
BCH
t
BCL
t
BCY
DIN
t
LRSU
t
DS
t
LRH
t
DH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
t
BCY
40
ns
BCKIN pulse widthhigh
t
BCH
16
ns
BCKIN pulse widthlow
t
BCL
16
ns
LRCIN set-up time to
BCKIN rising edge
t
LRSU
8
ns
LRCIN hold time from
BCKIN rising edge
t
LRH
8
ns
DIN set-up time to BCKIN
rising edge
t
DS
8
ns
DIN h old time from BCKIN
rising edge
t
DH
8
ns
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DSD AUDIO MONOPHASE INTERFACE
MCLK
t
BCH
t
BCL
t
BCY
DIN/LRCIN
t
DS
t
DH
Figure 3 Normal DSD timing requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
MCLK cycle time
t
BCY
344
ns
MCLK pulse widthhigh
t
BCH
160
ns
MCLK pulse widthlow
t
BCL
160
ns
DIN/LRCIN set-up time to
MCLK rising edge
t
DS
10
ns
DIN/LRCIN hold time from
MCLK rising edge
t
DH
10
ns
POWER SUPPLY TIMING
DVDD
AVDD
t
PSU
Figure 4 Power Supply Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
DVDD set up time to AVDD
rising edge
t
PSU
Measured from DVDD/2 to AVDD/2
10
ms
WM8728
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DSD AUDIO BIPHASE INTERFACE
MCLK
DIN/LRCIN
D0
D1
D1
D2
D2
t
BCY
t
BCH
t
BCL
t
PH
t
SU
t
HD
t
MCL
t
MCH
t
MCY
BCKIN
Figure 5 Biphase DSD Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
t
BCY
162.8
ns
BCKIN pulse widthhigh
t
BCH
80
81.4
ns
BCKIN pulse widthlow
t
BCL
80
81.4
ns
MCLK cycle time
t
MCY
325.5
ns
MCLK pulse widthhigh
t
MCH
160
162.8
ns
MCLK pulse widthlow
t
MCL
160
162.8
ns
Phase shift between BCKIN
and MCLK
t
PH
20
ns
Data setup time to BCKIN
falling edge
t
SU
10
ns
Data h old time to BCKIN
rising edge
t
HD
10
ns
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MPU 3-WIRE INTERFACE TIMING
LATI2S
SCKDSD
SDIDEM
t
CSL
t
DHO
t
DSU
t
CSH
t
SCY
t
SCH
t
SCL
t
SCS
LSB
t
CSS
CSBIWL
t
CSSH
t
CSSU
Figure 6 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCKDSD rising edge to LATI2S
rising edge
t
SCS
40
ns
SCKDSD pulse cycle time
t
SCY
80
ns
SCKDSD pulse widthlow
t
SCL
20
ns
SCKDSD pulse widthhigh
t
SCH
20
ns
SDIDEM to SCKDSD set-up
time
t
DSU
20
ns
SCKDSD to SDIDEM hold time
t
DHO
20
ns
LATI2S pulse widthlow
t
CSL
20
ns
LATI2S pulse widthhigh
t
CSH
20
ns
LATI2S rising to SCKDSD rising
t
CSS
20
ns
CSBIWL to LATI2S set-up time
t
CSSU
20
ns
LATI2S to CSBIWL hold time
t
CSSH
20
ns
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MPU 2-WIRE INTERFACE TIMING
SCKDSD
SDIDEM
t
SSU
t
SHD
t
SCY
t
SCH
t
SCL
t
DSU
t
DHD
t
SCR
t
SCF
t
DF
t
DR
t
ESU
Figure 7 Program Register Input Timing - 2-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCKDSD pulse cycle time
t
SCY
80
ns
SCKDSD pulse widthlow
t
SCL
20
ns
SCKDSD pulse widthhigh
t
SCH
20
ns
SDIDEM to SCKDSD data set-
up time for start signal
t
SSU
10
ns
SDIDEM from SCKDSD data
hold time for start signal
t
SHD
10
ns
SDIDEM to SCKDSD data set-
up time
t
DSU
20
ns
SCKDSD to SDIDEM data hold
time
t
DHD
20
ns
SCKDSD rise time
t
SCR
5
ns
SCKDSD fall time
t
SCF
5
ns
SDIDEM rise time
t
DR
5
ns
SDIDEM fall time
t
DF
5
ns
SDIDEM to SCKDSD data set-
up time for stop signal
t
ESU
10
ns
Notes:
1.
The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.
2.
In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chip address.
3.
In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interface into 3-wire
mode.
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DEVICE DESCRIPTION
INTRODUCTION
The WM8728 is a high performance DAC designed for digital consumer audio applications. Its
range of features makes it ideally suited for use in DVD players, AV receivers and other high-end
consumer audio equipment.
WM8728 is a complete 2-channel stereo audio digital-to-analogue converter, including digital
interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo DAC and
output smoothing filters. The WM8728 includes an on-chip digital volume control, configurable
digital audio interface and a 2 or 3 wire MPU control interface. It is fully compatible and an ideal
partner for a range of industry standard microprocessors, controllers and DSPs.
Control of internal functionality of the device is by either hardware control (pin programmed) or
software control (2 or 3-wire serial control interface). The MODE pin selects between hardware
and software control. The software control interface may be asynchronous to the audio data
interface. In which case control data will be re-synchronised to the audio processing internally.
Operation using a master clock of 256fs, 384fs, 512fs or 768fs is provided, selection between
clock rates being automatically controlled in hardware mode, or serial controlled when in software
mode. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate
master clock is input. Support is also provided for up to 192ks/s using a master clock of 128fs or
192fs.
The audio data interface supports right justified, left justified and I
2
S (Philips left justified, one bit
delayed) interface formats along with a highly flexible DSP serial port interface. When in hardware
mode, the three serial interface pins become control pins to allow selection of, input data format
type (I
2
S or right justified), input word length (20 or 24 bit) and de-emphasis functions.
In DSD mode, a separate bitstream data input pin is required for each of the channels, plus a 64fs
dataclock MCLK. These signals are applied via pins DIN and LRCIN and the signals routed
internally into the DAC circuits, under control of the SCKDSD mode select pin (19) See Figure 3.
Additionally a Phase Modulation scheme is supported, whereby the audio data is transmitted as a
Manchester encoded bitstream. This has the advantage of removing the significant spectral audio
energy from the datastream, minimising digital signal corruption of the analogue outputs. In order
to simplify decoding of this Phase modulated data, a 2x speed clock (BCKIN) is used to sample
the incoming data. See Figure 5.
The device is packaged in a small 20-pin SSOP.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock
to which all audio data processing is synchronised. This clock is often referred to as the audio
system's Master Clock. The external master system clock can be applied directly through the
MCLK input pin withno software configuration necessary for sample rate selection.
Note that on the WM8728, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In
a system where there are a number of possible sources for the reference clock it is recommended
that the clock source with the lowest jitter be used to optimise the performance of the DAC.
WM8728 always acts as a slave and requires clocks to be inputs.
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DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular
interface formats are supported:
Left Justified mode
Right Justified mode
I
2
S mode
DSP Early mode
DSP Late mode
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits with the
exception that 32 bit data is not supported in right justified mode. DIN and LRCIN maybe
configured to be sampled on the rising or falling edge of BCKIN.
In left justified, right justified and I
2
S modes, the digital audio interface receives data on the DIN
input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is
present. LRCIN is also used as a timing reference to indicate the beginning or end of the data
words. The minimum number of BCKINs per LRCIN period is 2 times the selected word length.
LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length
BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are
met
The WM8728 will automatically detect when data with a LRCIN period of exactly 32 BCKINs is
sent, and select 16-bit mode - overriding any previously programmed word length. Word length
will revert to a programmed value only if a LRCIN period other than 32 BCKINs is detected.
In DSP early or DSP late mode, the data is time multiplexed onto DIN. LRCIN is used as a frame
sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN
period is 2 times the selected word length. Any mark to space ratio is acceptable on LRCIN
provided the rising edge is correctly positioned. (See Figure 11 and Figure 12)
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 8 Left JustifiedMode Timing Diagram
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RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
Figure 9 Right JustifiedMode Timing Diagram
I
2
S MODE
In I
2
S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left data word and high during the right data word.
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCKIN
1 BCKIN
Figure 10 I
2
S Mode Timing Diagram
DSP EARLY MODE
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data words.
The word order is DIN left, DIN right.
LRCIN
BCKIN
DIN
Input Word Length(IWL)
1/fs
LEFT CHANNEL
n
2
1
n-1
LSB
MSB
n
2
1
n-1
RIGHT CHANNEL
NO VALID DATA
1 BCKIN
1 BCKIN
Figure 11 DSP Early Mode Timing Diagram
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DSP LATE MODE
In DSP late mode, the first bit is sampled on the BCKIN rising edge, which detects a low to high
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is
DIN left, DIN right.
LRCIN
BCKIN
DIN
Input Word Length(IWL)
1/fs
LEFT CHANNEL
n
2
1
n-1
LSB
MSB
n
2
1
n-1
RIGHT CHANNEL
NO VALID DATA
1
Figure 12 DSP Late Mode Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8728 can range from 128fs to 768fs, where fs is the audio sampling
frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used
to operate the digital filters and the noise shaping circuits.
The WM8728 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If
there is a greater than 32 clocks error, the interface shuts down the DAC and mutes the output.
The master clock should be synchronised with LRCIN, although the WM8728 is tolerant of phase
differences or jitter on this clock. See Table 1
MASTER CLOCK FREQUENCY (MHZ) (MCLK)
SAMPLING
RATE
(LRCIN)
128fs
192fs
256fs
384fs
512fs
768fs
32kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1kHz
5.6448
8.467
11.2896
16.9340
22.5792
33.8688
48kHz
6.114
9.216
12.288
18.432
24.576
36.864
96kHz
12.288
18.432
24.576
36.864
Unavailable
Unavailable
192kHz
24.576
36.864
Unavailable
Unavailable
Unavailable
Unavailable
Table 1 Typical Relationships Between Master Clock Frequency andSampling Rate
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HARDWARE DSD MODE
DSD mode is selected by taking the SCKDSD pin high whilst the MODE pin is low. In this mode
the internal digital filters are bypassed, and the already modulated bitstream data is applied
directly to the Switched Capacitor DAC filter where it is converted and lowpass filtered, see Figure
27 to Figure 30.
Two formats are supported for data transfer, MONOPHASE or BIPHASE MODULATED.
In Monophase mode, DSD data is simply clocked into the device using the rising edge of the 64fs
MCLK signal.
In Biphase mode, the data is supplied in Manchester encoded form (a bit transition occurs during
every data bit, which shapes the spectral energy minimising corruption of the analogue outputs).
A secondary clock BCKIN, at 128fs is used to simplify data recovery, the data simply being
clocked with the falling edge of BCKIN when MCLK is at logic low (0V).
See Figure 3 and Figure 5 for details of DSD interface timing.
HARDWARE CONTROL MODES
When the MODE pin is held low, the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, pin 17 (MUTEB) controls the selection of MUTE directly,
and can be used to enable and disable the automute function. Automute is enabled by leaving
MUTEB pin floating, it is disabled by applying a signal to the pin. When left floating this pin
becomes an output and indicates infinite ZERO detect (IZD), see also pin 5 (ZERO). The status
of IZD controls the selection of MUTE when automute is enabled. When IZD is detected MUTE is
enabled and when IZD is not detected MUTE is disabled.
MUTEB PIN
DESCRIPTION
0
Mute DAC channels
1
Normal Operation
Floating
MUTEB becomes an output to indicate when IZD occurs.
L=IZD detected (MUTE enabled), H=IZD not detected (MUTE disabled).
Table 2 Mute andAutomute Control
ZERO PIN
DESCRIPTION
0
Indicates Infinite Zero detected from the digital input.
1
Indicates Infinite Zero not detected from the digital input.
Table 3 Zero Pin Output
Figure 13 shows the application and release of MUTE whilst a full amplitude sinusoid is being
played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace)
begins to decay exponentially from the DC level of the last input sample. The output will decay
towards V
MID
witha time constant of approximately 64 input samples. Wh
en MUTE is de-
asserted, the output will restart almost immediately from the current input sample.
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-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
Figure 13 Application andRelease of Soft Mute
The MUTEB pin is an input to select mute or not mute. MUTEB is active low; taking the pin low
causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking
MUTEB high again allows data into the filter.
The automute function detects a series of ZERO value audio samples of 1024 samples long
being applied to bothchannels. After suchan event, a latchis set whose output (AUTOMUTED)
is wire OR'ed through a 10kohm resistor to the MUTEB pin. Thus if the MUTEB pin is not being
driven, the automute function will assert mute.
If MUTEB is tied high, AUTOMUTED is overridden and will not mute unless the IZD register bit is
set. If MUTEB is driven from a bi-directional source, then both MUTE and automute functions are
available. If MUTEB is not driven, AUTOMUTED appears as a weak output (10kOhm-source
impedance) so can be used to drive external mute circuits. AUTOMUTED will be removed as
soon as any channel receives a non-ZERO input.
A diagram showing how the various Mute modes interact is shown below Figure 14.
IZD (Register Bit)
AUTOMUTED
(Internal Signal)
10k
MUT (Register Bit)
SOFTMUTE
(Internal
Signal)
MUTEB
PIN
Figure 14 Selection Logic for MUTE Modes
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INPUT FORMAT SELECTION
In hardware mode, LATI2S (pin 20) and CSBIWL (pin 15) become input controls for selection of
input data format type and input data word length.
LATI2S
CSBIWL
INPUT DATA MODE
0
0
24-bit right justified
0
1
20-bit right justified
1
0
16-bit I
2
S
1
1
24-bit I
2
S
Table 4 Input Format Selection
Note:
In 24 bit I
2
S mode, any width of 24 bits or less is supported provided that LRCIN is high for a
minimum of 24 BCKINs and low for a minimum of 24 BCKINs. If exactly 32 BCKINs occur in one
LRCIN (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.
DE-EMPHASIS CONTROL
In hardware mode, SDIDEM (pin 18) becomes an input control for selection of de-emphasis
filtering to be applied.
SDIDEM
DE-EMPHASIS
0
Off
1
On
Table 5 De-emphasis Control
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using a 2-wire interface compatible or 3-wire (SPI-
compatible) interface.
SELECTION OF CONTROL MODE
The WM8728 may be programmed to operate in hardware or software control modes. This is
achieved by setting the state of the MODE pin.
MODE
INTERFACE FORMAT
0
Hardware Control Mode
1
Software Control Mode
Table 6 Control Interface Mode Selection
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
In this mode, SDIDEM is used for the program data, SCKDSD is used to clock in the program
data and LATI2S is used to latch in the program data. The 3-wire interface protocol is shown in
Figure 15.
LATI2S
SCKDSD
SDIDEM
B15
B6
B7
B8
B9
B10
B11
B12
B13
B14
B1
B2
B3
B4
B5
B0
Figure 15 3-Wire Serial Interface
Notes:
1.
B[15:9] are Control Address Bits
2.
B[8:0] are Control Data Bits
3.
CSBIWL needs to be low during writes see Figure 6
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2-WIRE SERIAL CONTROL MODE
In 2-wire mode, which is the default, SDIDEM is used for the program data and SCKDSD is used
to clock in the program data see Figure 16.
WM8728 has an address of 001101X (binary) which represents an audio device.
The final
address digit is dependent on pin CSBIWL, which should be tied to either DVDD or DGND. This
allows the device to have a choice of two identification header addresses used in the 2 wire
interface word. This feature allows more than one WM8728 device to be present on the interface
bus.
LATI2S should be tied to either DVDD or DGND, as it is unused. This pin if toggled from low to
high and high to low, will cause the device to enter the 3-wire interface mode and cannot be
placed back into 2-wire mode except by toggling the MODE pin, or powering off the device.
SDIDEM
SCKDSD
ACK
R ADDR
ACK
DATA B15-8
STOP
START
DATA B7-0
R/W
ACK
Figure 16 2-Wire Serial Interface
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REGISTER MAP
WM8728 uses a total of 4 program registers, which are 16-bits long. These registers are all loaded through input pin SDIDEM.
Using either 2-wire or 3-wire serial control mode as shown in Figure 15 and Figure 16.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
M0
0
0
0
0
0
0
0
UPDATEL
LAT7
LAT6
LAT5
LAT4
LAT3
LAT2
LAT1
LAT0
M1
0
0
0
0
0
0
1
UPDATER
RAT7
RAT6
RAT5
RAT4
RAT3
RAT2
RAT1
RAT0
M2
0
0
0
0
0
1
0
0
0
0
IW2
IW1
IW0
PWDN DEEMPH
MUT
M3
0
0
0
0
0
1
1
IZD
0
0
BCP
REV
0
ATC
LRP
I
2
S
ADDRESS
DATA
Table 7 Mapping of Program Registers
REGISTER
ADDRESS
(A3,A2,A1,A0)
BITS
NAME
DEFAULT
DESCRIPTION
[7:0]
LAT[7:0]
11111111 (0dB)
Attenuation data for left channel in 0.5dB steps, see Table 10
0000
DACL
Attenuation
8
UPDATEL
0
Attenuation data load control for left channel.
0: Store DACL in intermediate latch(no change to output)
1: Store DACL and update attenuation on bothchannels.
[7:0]
RAT[7:0]
11111111 (0dB)
Attenuation data for right channel in 0.5dB steps, see Table 10
0001
DACR
Attenuation
8
UPDATER
0
Attenuation data load control for right channel.
0: Store DACR in intermediate latch(no change to output)
1: Store DACR and update attenuation on bothchannels.
0
MUT
0
Left and right DACs soft mute control.
0: No mute
1: Mute
1
DEEMPH
0
De-emphasis control.
0: De-emphasis off
1: De-emphasis on
2
PWDN
0
Left and Right DACs Power-down Control
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
0010
DAC Control
[5:3]
IW[2:0]
0
Audio data format select, see Table 15
0
I
2
S
0
Audio data format select, see Table 15
1
LRP
0
Polarity select for LRCIN/DSP mode select.
0: normal LRCIN polarity/DSP late mode
1: inverted LRCIN polarity/DSP early mode
2
ATC
0
Attenuator Control.
0: All DACs use attenuation as programmed.
1: Right channel DACs use corresponding left DAC
attenuation
4
REV
0
Output phase reverse.
5
BCP
0
BCKIN Polarity
0 : normal BCKIN polarity
1: inverted BCKIN polarity
0011
Interface
Control
8
IZD
0
Infinite ZERO detection circuit control and automute control
0: Infinite ZERO detect disabled
1: Infinite ZERO detect enabled
Table 8 Register Bit Descriptions
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ATTENUATION CONTROL
Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation
is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation
control bits. All attenuation registers are double latched allowing new values to be pre-latched to
both channels before being updated synchronously. Setting the UPDATE bit on any attenuation
write will cause all pre-latched values to be immediately applied to the DAC channels.
REGISTER
ADDRESS
BITS
LABEL
DEFAULT
DESCRIPTION
[7:0]
LAT[7:0]
11111111 (0dB)
Attenuation data for Left channel DACL in 0.5dB steps.
0000
Attenuation
DACL
8
UPDATEL
0
Controls simultaneous update of all Attenuation Latches
0: Store DACL in intermediate latch(no change to output)
1: Store DACL and update attenuation on all channels.
[7:0]
RAT[7:0]
11111111 (0dB)
Attenuation data for Right channel DACR in 0.5dB steps.
0001
Attenuation
DACR
8
UPDATER
0
Controls simultaneous update of all Attenuation Latches
0: Store DACR in intermediate latch(no change to output)
1: Store DACR and update attenuation on all channels.
Table 9 Attenuation Register Map
Note:
1.
The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the
relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input
sample.
2.
Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise.
DAC OUTPUT ATTENUATION
Registers LAT and RAT control the left and right channel attenuation. Table 9 shows how the
attenuation levels are selected from the 8-bit words.
XAT[7:0]
ATTENUATION LEVEL
00(hex)
dB (mute)
01(hex)
127.5dB
:
:
:
:
:
:
FE(hex)
0.5dB
FF(hex)
0dB
Table 10 Attenuation Control Levels
MUTE MODES
Setting the MUT register bit will apply a 'soft' mute to the input of the digital filters:
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0010
DAC Control
0
MUT
0
Soft Mute select
0 : Normal Operation
1: Soft mute all channels
Table 11 Mute control
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DE-EMPHASIS MODE
Setting the DEEMPH register bit puts the digital filters into de-emphasis mode:
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0010
DAC Control
1
DEEMPH
0
De-emphasis mode select:
0 : De-emphasis Off
1: De-emphasis On
Table 12 De-emphasis Control
POWERDOWN MODE
Setting the PWDN register bit immediately connects all outputs to V
MID
and selects a low power
mode. All trace of the previous input samples is removed, and all control register settings are
cleared. When PWDN is cleared again the first 16 input samples will be ignored, as the FIR will
repeat it's power-on initialisation sequence.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0010
DAC Control
2
PWDN
0
Power Down Mode Select:
0 : Normal Mode
1: Power Down Mode
Table 13 Powerdown control
DIGITAL AUDIO INTERFACE CONTROL REGISTERS
The WM8728 has a fully featured digital audio interface that is a superset of that contained in the
WM8716. Interface format is selected via the IWL[2:0] register bits in register M2 and the I
2
S
register bit in M3.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0010
DAC Control
5:3
IWL[2:0]
000000
Interface format Select
0011
Interface Control
0
I
2
S
0
Interface format Select
Table 14 Interface Format Controls
IW2
I
2
S
IW1
IW0
AUDIO INTERFACE DESCRIPTION
(NOTE 1)
0
0
0
0
16 bit right justified mode
0
0
0
1
20 bit right justified mode
0
0
1
0
24 bit right justified mode
0
0
1
1
24 bit left justified mode
0
1
0
0
16 bit I
2
S mode
0
1
0
1
24 bit I
2
S mode
0
1
1
0
20 bit I
2
S mode
0
1
1
1
20 bit left justified mode
1
0
0
0
16 bit DSP mode
1
0
0
1
20 bit DSP mode
1
0
1
0
24 bit DSP mode
1
0
1
1
32 bit DSP mode
1
1
0
0
16 bit left justified mode
Table 15 Audio Data Input Format
Note:
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8728 pads the unused LSBs with
ZEROS. If the DAC is programmed into 32-bit mode, the 8 LSBs are treated as zero.
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SELECTION OF LRCIN POLARITY
In left justified, right justified or I
2
S modes, the LRP register bit controls the polarity of LRCIN. If
this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 8,
Figure 9 and Figure 10. Note that if this feature is used as a means of swapping the left and right
channels, a 1 sample phase difference will be introduced.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0011
Interface Control
1
LRP
0
LRCIN Polarity (normal)
0 : normal LRCIN polarity
1: inverted LRCIN polarity
Table 16 LRCIN Polarity Control
In DSP modes, the LRCIN register bit is used to select between early and late modes (see Figure
11 and Figure 12.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0011
Interface Control
1
LRP
0
DSP Format (DSP modes)
0 : Late DSP mode
1: Early DSP mode
Table 17 DSP Format Control
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the BCKIN
rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed
between the data words. The word order is DIN left, DIN right.
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left
and right channel DACs from the next audio input sample. No update to the attenuation registers
is required for ATC to take effect.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0011
Interface Control
2
ATC
0
Attenuator Control Mode:
0 : Right channels use Right
attenuation
1:
Right Channels use Left
Attenuation
Table 18 Attenuation Control Select
OUTPUT PHASE REVERSAL
The REV register bit controls the phase of the output signal. Setting the REV bit causes the
phase of the output signal to be inverted.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0011
Interface Control
4
REV
0
Analogue Output Phase
0: Normal
1: Inverted
Table 19 Output Phase Control
BCKIN POLARITY
By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change
on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN can
be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the
inverse of that shown in Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0011
Interface Control
5
BCP
0
BCKIN Polarity
0 : normal BCKIN polarity
1: inverted BCKIN polarity
Table 20 BCKIN Polarity Control
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INFINITE ZERO DETECTION
Setting the IZD register bit determines whether the device is automuted when a sequence of more
than 1024 ZEROS is detected.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0011
Interface Control
8
IZD
0
Infinite ZERO detection circuit
control and automute control
0: Infinite ZERO detect disabled
1: Infinite ZERO detect enabled
Table 21 IZD Control
DIGITAL FILTER CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Passband Edge
-3dB
0.487fs
Passband Ripple
f < 0.444fs
0.05
dB
Stopband Attenuation
f > 0.555fs
-60
dB
Table 22 Digital Filter Characteristics
DAC FILTER RESPONSES
-120
-100
-80
-60
-40
-20
0
0
0.5
1
1.5
2
2.5
3
Response (dB)
Frequency (Fs)
Figure 17 DAC Digital Filter Frequency Response
-44.1, 48 and96kHz
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Response (dB)
Frequency (Fs)
Figure 18 DAC Digital Filter Ripple
-44.1, 48 and96kHz
-80
-60
-40
-20
0
0
0.2
0.4
0.6
0.8
1
Response (dB)
Frequency (Fs)
Figure 19 DAC Digital Filter Frequency Response
-192kHz
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Response (dB)
Frequency (Fs)
Figure 20 DAC Digital Filter Ripple
-192kHz
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DIGITAL DE-EMPHASIS CHARACTERISTICS
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
12
14
16
Response (dB)
Frequency (kHz)
Figure 21 De-Emphasis Frequency Response (32kHz)
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
0
2
4
6
8
10
12
14
16
Response (dB)
Frequency (kHz)
Figure 22 De-Emphasis Error (32kHz)
-10
-8
-6
-4
-2
0
0
5
10
15
20
Response (dB)
Frequency (kHz)
Figure 23 De-Emphasis Frequency Response (44.1kHz)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0
5
10
15
20
Response (dB)
Frequency (kHz)
Figure 24 De-Emphasis Error (44.1kHz)
-10
-8
-6
-4
-2
0
0
5
10
15
20
Response (dB)
Frequency (kHz)
Figure 25 De-Emphasis Frequency Response (48kHz)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0
5
10
15
20
Response (dB)
Frequency (kHz)
Figure 26 De-Emphasis Error (48kHz)
WM8728
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DSD MODE CHARACTERISTICS
-60
-50
-40
-30
-20
-10
0
0
500
1000
1500
2000
Response (dB)
Frequency (kHz)
Figure 27 DSD Frequency Response - no post filter
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
0
50
100
150
200
250
300
350
400
Response (dB)
Frequency (kHz)
Figure 28 DSD Frequency Response - no post filter
-120
-100
-80
-60
-40
-20
0
0
50
100
150
200
250
300
350
400
Response (dB)
Frequency (kHz)
Figure 29 DSD frequency response - 4th order post filter
-8
-6
-4
-2
0
0
10
20
30
40
50
60
Response (dB)
Frequency (kHz)
Figure 30 DSD frequency response - 4th order post filter
WM8728
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS (PCM AUDIO)
20
DVDD
DGND
LATI2S
AGND
AVDD
7
6
Software I/F or
Hardware Control
WM8728
Notes:
1. AGND and DGND should be connected as close to the WM8728 as possible.
2. C
2
, C
3
, C
4
and C
8
should be positioned as close to the WM8728 as possible.
3. Capacitor types should be carefully chosen. Capacitors with very low ESR are
recommended for optimum performance.
VREFP
VREFN
C
3
C
4
C
5
C
2
DVDD
C
1
19
SCKDSD
18
SDIDEM
VOUTR
11
C
6
VOUTL
C
7
AC-Coupled
VOUTR/L
to External LPF
16
MODE
17
MUTEB
8
AVDD
4
MCLK
3
BCKIN
2
DIN
Audio Serial Data I/F
DGND
AGND
1
LRCIN
10
14
9
13
+
+
+
+
Software/hardware
control mode select
15
CSBIWL
5
ZERO
DVDD
R1
AGND
12
VMID
C
9
C
8
+
Figure 31 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C5
10
F
De-coupling for DVDD and AVDD/VREFP
C2 to C4
0.1
F
De-coupling for DVDD and AVDD/VREFP
C6 and C7
10
F
Output AC coupling caps to remove midrail DC level from outputs.
C8
0.1
F
C9
10
F
Reference de-coupling capacitors for VMID pin.
R1
10k
10k pull-up to DVDD
Table 23 External Components Description
WM8728
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RECOMMENDED EXTERNAL COMPONENTS (DSD AUDIO)
20
DVDD
DGND
LATI2S
AGND
AVDD
7
6
MUTE Control
WM8728
Notes:
1. AGND and DGND should be connected as close to the WM8728 as possible.
2. C
2
, C
3
, C
4
and C
8
should be positioned as close to the WM8728 as possible.
3. Capacitor types should be carefully chosen. Capacitors with very low ESR are
recommended for optimum performance.
4. When using monophase DSD encoding pin 3 BCKIN should be tied to
DVDD. In Biphase DSD encoding BCKIN runs at 2 cycles per bit.
VREFP
VREFN
C
3
C
4
C
5
C
2
DVDD
C
1
19
SCKDSD
18
SDIDEM
VOUTR
11
C
6
VOUTL
C
7
AC-Coupled
VOUTR/L
to External LPF
16
MODE
17
MUTEB
8
AVDD
4
MCLK
3
BCKIN
2
DIN
DSD right bitstream
DGND
AGND
1
LRCIN
10
14
9
13
+
+
+
+
15
CSBIWL
DGND
DVDD
DSD left bitstream
DSD bit clock
DSD biphase mode clock
DVDD
R1
5
ZERO
VMID
C
9
C
8
AGND
12
+
Figure 32 External Connections for DSD Applications
RECOMMENDED EXTERNAL COMPONENTS VALUES FOR DSD
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C5
10
F
De-coupling for DVDD and AVDD.
C2 to C4
0.1
F
De-coupling for DVDD and AVDD.
C6 and C7
10
F
Output AC coupling caps to remove midrail DC level from outputs.
C8
0.1
F
C9
10
F
Reference de-coupling capacitors for VMID pin.
R1
10k
10k pull-up to DVDD
Table 24 External Components for DSD
WM8728
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RECOMMENDED DSD CONNECTIONS
CXD2751Q
WM8728EDS
BCKA
DSAR
DSAL
MCLK
DIN
LRCIN
64fs
Right Channel Data
Left Channel Data
Figure 33 Monophase Mode Connection Diagram
CXD2751Q
WM8728EDS
BCKA
BCKD
DSAR
DSAL
MCLK
DIN
LRCIN
64fs
BCKIN
128fs
Right Channel Data
Left Channel Data
Figure 34 Biphase Mode Connection Diagram
DSD mode is selected with the WM8728 by pulling the SCKDSD pin high while the MODE pin is held low.
DSD mode is hardware only operation.
The CXD2751Q from Sony is a signal processor for Super Audio CD playback.
RECOMMENDED ANALOGUE LOW PASS FILTER FOR PCM DATA FORMAT
(OPTIONAL)
+
_
+
+VS
-VS
10uF
51
7.5K
680pF
1.8k
47k
4.7k
4.7k
1.0nF
Figure 35 Recommended Low Pass Filter (Optional)
WM8728
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PACKAGE DIMENSIONS
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
DM0015.B
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
Symbols
Dimensions
(mm)
MIN
NOM
MAX
A
-----
-----
2.0
A
1
0.05
-----
-----
A
2
1.65
1.75
1.85
b
0.22
0.30
0.38
c
0.09
-----
0.25
D
6.90
7.20
7.50
e
0.65 BSC
E
7.40
7.80
8.20
5.00
5.30
5.60
L
0.55
0.75
0.95
REF:
A A2
A1
SEATING PLANE
-C-
0.10 C
10
1
D
11
20
e
b
E1
E
-
JEDEC.95, MO 150
0
o
4
o
8
o
E
1
L
1
0.125 REF
c
L
GAUGE
PLANE
0.25
L
1
WM8728
Production Data
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PD Rev 3.1 December 2002
30
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service
without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time
of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard
warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty.
Specific testing of all parameters of eachdevice is not necessarily performed, except th
ose mandated by government
requirements.
In order to minimise risks associated withcustomer applications, adequate design and operating safeguards must be used by
the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any
license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of WM covering or relating to any combination, machine, or process in which such products or services might be or are
used. WM's publication of information regarding any third party's products or services does not constitute WM's approval,
license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information
withalteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business
practice, and WM is not responsible nor liable for any suchuse.
Resale of WM's products or services withstatements different from or beyond the parameters stated by WM for that product or
service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any suchuse.
ADDRESS:
Wolfson Microelectronics plc
20 Bernard Terrace
Edinburgh
EH8 9NX
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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