Document Outline
- WM8738
- DESCRIPTION
- FEATURES
- APPLICATIONS
- BLOCK DIAGRAM
- PIN CONFIGURATION
- ORDERING INFORMATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TERMINOLOGY
- DIGITAL AUDIO INTERFACE TIMING
- DEVICE DESCRIPTION
- INTRODUCTION
- ADC
- ADC DIGITAL FILTER
- AUDIO DATA SAMPLING RATES
- DIGITAL AUDIO INTERFACES
- DIGITAL FILTER CHARACTERISTICS
- ADC FILTER RESPONSES
- ADC HIGH PASS FILTER
- RECOMMENDED EXTERNAL COMPONENTS
- RECOMMENDED EXTERNAL COMPONENTS VALUES
- PACKAGE DIMENSIONS
- IMPORTANT NOTICE
WM8738
24 Bit Stereo ADC
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Product Preview, January 2003, Rev 1.8
Copyright
2003 Wolfson Microelectronics plc
DESCRIPTION
The WM8738 is a high performance stereo audio ADC
designed for consumer applications.
Stereo line-level audio inputs are provided, along with a
control input pin to allow operation of the audio interface in
either one of two industry standard modes. The device also
has a selectable digital high pass filter to remove residual
DC offsets.
Stereo 24-bit multi-bit sigma delta ADCs are provided, along
with oversampling digital interpolation filters. 24-bit digital
audio output word lengths and sampling rates from 8kHz to
96kHz are supported.
The device is available in a small 14-pin SOIC package.
FEATURES
Audio Performance
-
90 dB SNR (`A' weighted @ 48kHz) ADC
3.0 5.5V Analogue Supply Operation
3.0 3.6V Digital Supply Operation
ADC Sampling Frequency: 8kHz 96kHz
Selectable ADC High Pass Filter
Selectable Audio Data Interface Modes
-
I
2
S or Left Justified
14-pin SOIC Package
APPLICATIONS
CD and Minidisc Recorders
DVD Players
General Purpose Audio Conversion
BLOCK DIAGRAM
DIGITAL
FILTERS
FM
T
NO
HP
RIN
LIN
CAP
DV
D
D
DG
ND
AVDD
AGND
LRCLK
SDATO
VR
EF
AUDIO
INTERFACE
BCLK
MCLK
ADC
ADC
CONTROL
INTERFACE
W
WM8738
WM8738
Product Preview
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PP Rev 1.8 January 2003
2
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM8738ED
-25 to +85
o
C
14-pin SOIC
WM8738GED
-25 to +85
o
C
14-pin SOIC
(lead free)
WM8738ED/R
-25 to +85
o
C
14-pin SOIC
(tape and reel)
WM8738GED/R
-25 to +85
o
C
14-pin SOIC
(lead free, tape
and reel)
WM8738
1
2
3
4
5
6
7
MCLK
LIN
AVDD
AGND
LRCLK
NOHP
SDATO
DGND
CAP
FMT
BCLK
DVDD
8
9
10
11
14
13
12
RIN
VREF
Note:
Reel quantity = 3,000
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
DVDD
Supply
Digital positive supply
2
SDATO
Digital Output
ADC digital data output
3
BCLK
Digital Input
ADC digital output data clock (5v Tolerant)
4
FMT
Digital input (with pull down)
Audio interface format selection (5v Tolerant)
`0' = I
2
S
`1' = Left Justified
5
CAP
Analog
Reference de-coupling pin
6
VREF
Analogue output
Buffered reference decoupling pin
7
RIN
Analogue Input
Right channel ADC input
8
LIN
Analogue Input
Left channel ADC input
9
AVDD
Supply
Analogue positive supply
10
AGND
Supply
Analogue ground supply and chip substrate
11
NOHP
Digital input (with pull down)
Digital highpass filter bypass; (5v Tolerant)
`0' = Enabled
`1' = Bypassed
12
LRCLK
Digital Input
Data left/right word clock (5v Tolerant)
13
MCLK
Digital Input
Master clock input (5v Tolerant)
14
DGND
Supply
Digital supply ground
Notes
1. Digital input pins have Schmitt trigger input buffers and are 5V tolerant.
WM8738
Product Preview
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PP Rev 1.8 January 2003
3
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
The WM8738 has been classified as MSL1, which has an unlimited floor life at <30
o
C / 85% Relative Humidity and therefore will
not be supplied in moisture barrier bags.
CONDITION
MIN
MAX
Digital supply voltage
-0.3V
+3.63V
Analogue supply voltage
-0.3V
+7.0V
Voltage range digital inputs
DGND -0.3V
+7.0V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
Master Clock Frequency
37MHz
Operating temperature range, T
A
-25
C
+85
C
Storage temperature prior to soldering
30
C max / 85% RH max
Storage temperature after soldering
-65
C
+150
C
Package body temperature (soldering 10 seconds)
+240
C
Package body temperature (soldering 2 minutes)
+183
C
Notes
1.
Analogue and digital grounds must always be within 0.3V of each other.
2.
The digital supply voltage must always be less than or equal to the analogue supply voltage.
RECOMMENDED OPERATINGCONDITIONS
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range
DVDD
3.0
3.6
V
Analogue supply range
AVDD
3.0
5.5
V
Ground
DGND,AGND
0
V
Analogue supply current
AVDD = 5.0V,
(DVDD at 3.3V)
30
mA
Analogue supply current
AVDD = 3.3V,
(DVDD at 3.3V)
19
mA
Supply Current Low Power
Mode
AVDD = 5.0V
(DVDD at 3.3V)
180
A
Supply Current Low Power
Mode
AVDD = 3.3V
(DVDD at 3.3V)
110
A
Digital supply current
DVDD = 3.3V
AVDD = 5.0V or 3.3V
4
mA
WM8738
Product Preview
w
PP Rev 1.8 January 2003
4
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (TTL Levels)
Input LOWlevel
V
IL
0.8
V
Input HIGH level
V
IH
2.0
V
Output LOWV
OL
0.1 x DVDD
V
Output HIGH
V
OH
0.9 x DVDD
V
Pull down resistance (FMT,
NOHP)
R
PD
100
k
Analogue Reference Levels
Reference voltage
V
CAP
AVDD/2
50mV
AVDD/2
AVDD/2 +
50mV
V
Buffered reference voltage
V
REF
V
CAP
V
Potential divider output
impedance
R
CAP
40K
50K
60K
Ohms
Input to ADC
Input Signal Level (0dB)
V
RIN
/ V
LIN
1.0
Vrms
SNR (Note 1,2)
A-weighted, 0dB gain
@ fs = 48KHz
90
dB
SNR (Note 1,2)
A-weighted, 0dB gain
@ fs = 96KHz
90
dB
SNR (Note 1,2)
A-weighted, 0dB gain
@ fs = 48KHz, AVDD =
3.3V
90
dB
Dynamic Range (Note 2)
DNR
A-weighted, -60dB full
scale input
90
97
dB
Total Harmonic Distortion (THD)
(Note 4)
-1dB input, 0dB gain
-87
dB
ADC channel separation
1KHz input
95
dB
Input Resistance
20k
Ohms
Input Capacitance
10
pF
Notes
1.
Ratio of output level with 1kHz full scale input, to the output level with the input open circuited, measured `A' weighted
over a 20Hz to 20kHz bandwidth using an Audio analyser.
2.
All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
3.
VREF and CAP de-coupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
4.
This data is measured, using an active filter on the device inputs.
TERMINOLOGY
1.
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No `Auto-zero' or Automute function is employed in achieving these results).
2.
Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD+N (dB) - THD+N is a ratio, of the r.m.s. values, of (Noise + Distortion)/Signal.
4.
Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5.
Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6.
Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
WM8738
Product Preview
w
PP Rev 1.8 January 2003
5
DIGITAL AUDIO INTERFACE TIMING
M CLK
t
MCLKH
t
MCLKY
t
MCLKL
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
T
MCLKH
10
ns
MCLK System clock pulse width low
T
MCLKL
10
ns
MCLK System clock cycle time
T
MCLKY
27
ns
BCLK
LRCLK
t
BCH
t
BCL
t
B CY
SDATO
t
LRS U
t
LRH
t
DD
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
t
BCY
80
ns
BCLK pulse width high
t
BCH
40
ns
BCLK pulse width low
t
BCL
40
ns
LRCLK set-up time to BCLK
rising edge
t
LRSU
10
ns
LRCLK hold time from
BCLK rising edge
t
LRH
10
ns
SDATO propagation delay
from BCLK falling edge
t
DD
10
ns
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