Document Outline
- WM8781
- 24-Bit, 192kHz Stereo ADC
- DESCRIPTION
- FEATURES
- APPLICATIONS
- BLOCK DIAGRAM
- TABLE OF CONTENTS
- PIN CONFIGURATION
- ORDERING INFORMATION
- PIN DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- SIGNAL TIMING REQUIREMENTS
- DEVICE DESCRIPTION
- INTRODUCTION
- ADC
- ADC DIGITAL FILTER
- DIGITAL AUDIO INTERFACE
- POWER DOWN CONTROL
- POWER ON RESET
- DIGITAL FILTER CHARACTERISTICS
- ADC FILTER RESPONSES
- ADC HIGH PASS FILTER
- APPLICATIONS INFORMATION
- RECOMMENDED EXTERNAL COMPONENTS
- RECOMMENDED EXTERNAL COMPONENTS VALUES
- PACKAGE DIMENSIONS
- IMPORTANT NOTICE
- ADDRESS:
w
WM8781
24-Bit, 192kHz Stereo ADC
WOLFSON MICROELECTRONICS plc
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http://www.wolfsonmicro.com/enews/
Production Data, April 2006, Rev 4.1
Copyright
2006 Wolfson Microelectronics plc
DESCRIPTION
The WM8781 is a high performance, low cost stereo audio
ADC designed for recordable media applications.
The device offers stereo line level inputs along with two
control input pins (FORMAT, IWL) to allow operation of the
audio interface in three industry standard modes. An
internal op-amp is integrated on the front end of the chip to
accommodate analogue input signals greater than 1V
rms
.
The device also has a high pass filter to remove residual
DC offsets.
WM8781 offers Master or Slave mode clocking schemes.
A control input pin M/S is used to allow Slave mode
operation or Master mode operation. A stereo 24-bit multi-
bit sigma-delta ADC is used with 128x, 64x or 32x over-
sampling, according to sample rate. Digital audio output
word lengths from 16-24 bits and sampling rates from
8kHz to 192kHz are supported.
The device is a hardware controlled device and is supplied
in a 20-lead SSOP package.
FEATURES
SNR 102dB (`A' weighted @ 48kHz)
THD -90dB (at 1dB)
Sampling Frequency: 8 192kHz
Master or Slave Clocking Mode
System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs,
768fs
Audio Data Interface Modes
-
16-24 bit I
2
S, 16-24 bit Left, 16-24 bit Right Justified
Supply Voltages
-
Analogue 2.7 to 5.5V
-
Digital core: 2.7V to 3.6V
20-lead SSOP package
APPLICATIONS
Recordable DVD Players
Personal Video Recorders
STB
Studio Audio Processing Equipment
BLOCK DIAGRAM
WM8781
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TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
ABSOLUTE MAXIMUM RATINGS .........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY............................................................................................................. 7
SIGNAL TIMING REQUIREMENTS .......................................................................8
DEVICE DESCRIPTION .......................................................................................10
INTRODUCTION.......................................................................................................... 10
ADC ............................................................................................................................. 1 0
ADC DIGITAL FILTER ................................................................................................. 10
DIGITAL AUDIO INTERFACE...................................................................................... 11
POWER DOWN CONTROL......................................................................................... 14
POWER ON RESET .................................................................................................... 14
DIGITAL FILTER CHARACTERISTICS ...............................................................16
ADC FILTER RESPONSES ......................................................................................... 16
ADC HIGH PASS FILTER ............................................................................................ 17
APPLICATIONS INFORMATION .........................................................................18
RECOMMENDED EXTERNAL COMPONENTS........................................................... 18
RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 18
PACKAGE DIMENSIONS ....................................................................................19
IMPORTANT NOTICE ..........................................................................................20
ADDRESS:................................................................................................................... 20
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PIN CONFIGURATION
1
MCLK
2
3
VREFGND
4
5
VREFP
6
7
AVDD
8
AINR
9
AGND
10
AINOPR
AINOPL
COM
AINL
M/S
BCLK
FSAMPEN
IWL
LRCLK
DGND
DOUT
DVDD
VMID
FORMAT
11
12
13
14
15
16
17
20
19
18
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
WM8781GEDS
-25
C to +85C
20-lead SSOP
(Pb-free)
MSL1
260
o
C
WM8781GEDS/R
-25
C to +85C
20-lead SSOP
(Pb-free, tape and reel)
MSL1
260
o
C
Note:
Reel quantity = 2,000
WM8781
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PIN DESCRIPTION
PIN NO.
NAME
TYPE
DESCRIPTION
1
MCLK
Digital Input
Master Clock
2
DOUT
Digital Output
ADC Digital Audio Data
3
LRCLK
Digital Input / Output
Audio Interface Left / Right Clock
4
DGND
Supply
Digital Negative Supply
5
DVDD
Supply
Digital Positive Supply
6
BCLK
Digital Input / Output
Audio Interface Bit Clock
7
IWL
Digital Tristate Input
Word Length
0 = 16 bit
1 = 20 bit
Z = 24 bit
8
FSAMPEN
Digital Tristate Input
Fast Sampling Rate Enable
0 = 48kHz enable
1 = 96kHz enable
Z = 192kHz enable
9
FORMAT
Digital Tristate Input
Audio Mode Select
0 = RJ
1 = LJ
Z = I2S
10
VMID
Analogue Output
Midrail Voltage Decoupling Capacitor
11
VREFGND
Supply
Negative Supply and Substrate Connection
12
VREFP
Analogue Output
Positive Reference Voltage Decoupling Pin; 10uF external decoupling
13
AVDD
Supply
Analogue Positive Supply
14
AGND
Supply
Analogue Negative Supply and Substrate Connection
15
AINOPR
Analogue Output
Right Channel Internal Op-Amp Output
16
AINR
Analogue Input
Right Channel Input
17
COM
Analogue Input
Common mode high impedance input should be set to midrail.
18
AINOPL
Analogue Output
Left Channel Internal Op-Amp Output
19
AINL
Analogue Input
Left Channel Input
20
M/S
Digital Input
Interface Mode Select
0 = Slave mode (128fs, 192fs, 256fs, 384fs, 512fs, 768fs)
1 = Master mode (384fs, 192fs)
(fs=word clock frequency)
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30
C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30
C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
MAX
Digital supply voltage
-0.3V
+3.63V
Analogue supply voltage
-0.3V
+7V
Voltage range digital inputs
DGND -0.3V
DVDD + 0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
+Operating temperature range, T
A
-25
C
+85
C
Storage temperature after soldering
-65
C
+150
C
Notes
1.
Analogue and digital grounds must always be within 0.3V of each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range
DVDD
2.7
3.6
V
Analogue supply range
AVDD
2.7
5.5
V
Ground
DGND,AGND
0
V
Notes
1.
Digital supply DVDD must never be more than 0.3V greater than AVDD.
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ELECTRICAL CHARACTERISTICS
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Performance
Full Scale Input Signal Level
(for ADC 0dB Input)
1
.0
V
rms
Input resistance, using
recommended external resistor
network on p17.
10
k
Input capacitance
20
pF
A-weighted,
@ fs = 48kHz
93
102
dB
Unweighted,
@ fs = 48kHz
100
dB
Signal to Noise Ratio
(see Terminology note 1,2,4)
SNR
A-weighted,
@ fs = 48kHz, AVDD =
3.3V
100
dB
A-weighted,
@ fs = 96kHz
93
99
dB
Unweighted,
@ fs = 96kHz
99
dB
Signal to Noise Ratio
(see Terminology note 1,2,4)
SNR
A-weighted,
@ fs = 96kHz, AVDD =
3.3V
99
dB
1kHz, -1dB Full Scale
@ fs = 48kHz
-91
dB
1kHz, -1dB Full Scale
@ fs = 96kHz
-91
dB
Total Harmonic Distortion
THD
1kHz, -1dB Full Scale
@ fs = 192kHz
-90
dB
Dynamic Range
DNR
-60dBFS
93
102
dB
Channel Separation
(see Terminology note 4)
1kHz Input
90
dB
Channel Level Matching
1kHz signal
0.1
dB
Channel Phase Deviation
1kHz signal
0.0001
Degree
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp, applied
to AVDD, DVDD
50
dB
Digital Logic Levels (TTL Levels)
Input LOW level
V
IL
0.8
V
Input HIGH level
V
IH
2.0
V
Input leakage current digital pad
-1
0.2
+1
A
Input leakage current digital
tristate input (Note 3)
85
A
Input capacitance
5
pF
Output LOW
V
OL
I
OL
=1mA
0.1 x DVDD
V
Output HIGH
V
OH
I
OH
=
-1mA
0.9 x DVDD
V
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Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Reference Levels
Midrail Reference Voltage
VMID
AVDD to VMID and
VMID to VREFN
3%
AVDD/2
+3%
V
Potential Divider Resistance
R
VMID
50
k
Buffered Reference Voltage
VREFP
3%
AVDD/2
+3%
V
VREF source current
I
VREF
5
mA
VREF sink current
I
VREF
5
mA
Supply Current
Analogue supply current
AVDD = 5V
32
mA
Digital supply current
DVDD = 3.3V
5
mA
Power Down
0.5
mA
Notes:
1.
All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter. Failure to
use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the
Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect
dynamic specification values.
2.
VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce
performance.
3.
This high leakage current is due to the topology of the instate pads. The pad input is connected to the midpoint of an
internal resistor string to pull input to vmid if undriven.
TERMINOLOGY
1.
Signal-to-noise ratio (dB) Ratio of output level with 1kHz full scale input, to the output level with all zeros into the
digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these
results).
2.
Dynamic range (dB) DR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD+N (dB) THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4.
Channel Separation (dB) Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
T
MCLKL
1
1
ns
MCLK System clock pulse width low
T
MCLKH
1
1
ns
MCLK System clock cycle time
T
MCLKY
28
ns
MCLK duty cycle
T
MCLKDS
40:60
60:40
Table 1 Master Clock Timing Requirements
AUDIO INTERFACE TIMING MASTER MODE
Figure 2 Digital Audio Data Timing Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Master Mode, fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
t
DL
0
10
ns
DOUT propagation delay from BCLK falling edge
t
DDA
0
10
ns
Table 2 Digital Audio Data Timing - Master Mode
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AUDIO INTERFACE TIMING SLAVE MODE
Figure 3 Digital Audio Data Timing Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
t
BCY
50
ns
BCLK pulse width high
t
BCH
20
ns
BCLK pulse width low
t
BCL
20
ns
LRCLK set-up time to BCLK rising edge
t
LRSU
10
ns
LRCLK hold time from BCLK rising edge
t
LRH
10
ns
DOUT propagation delay from BCLK falling edge
t
DD
0
10
ns
Table 3 Digital Audio Data Timing - Slave Mode
Note:
LRCLK should be synchronous with MCLK, although the WM8781 interface is tolerant of phase variations or jitter on these
signals.
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DEVICE DESCRIPTION
INTRODUCTION
The WM8781 is a stereo 24-bit ADC designed for demanding recording applications such as DVD
recorders, studio mixers, PVRs, and AV amplifiers. The WM8781 consists of stereo line level inputs,
followed by a sigma-delta modulator and digital filtering.
The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow
operation of the audio interface in three industry standard modes (left justified, right justified or I
2
S) .
An internal op-amp is integrated on the front end of the chip to accommodate analogue input signals
greater than 1V
rms
. The device also has a high pass filter to remove residual DC offsets.
The WM8781 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow
Slave mode or Master mode operation. The WM8781 supports master clock rates from 128fs to
768fs and digital audio output word lengths from 16-24 bits. Sampling rates from 8kHz to 192kHz are
supported, delivering high SNR operating with 128x, 64x or 32x over-sampling, according to the
sample rate.
The line inputs are biased internally through the operational amplifier to V
MID
.
ADC
The WM8781 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is
illustrated in Figure 4 Multi-Bit Oversampling Sigma Delta ADC Schematic.
LIN/RIN
ANALOG
INTEGRATOR
MULTI
BITS
TO ADC DIGITAL FILTERS
Figure 4 Multi-Bit Oversampling Sigma Delta ADC Schematic
The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high
frequency noise.
The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any input voltage greater than full scale
will possibly overload the ADC and cause distortion. Note that the full scale input has a linear
relationship with AVDD. The internal op-amp and appropriate resistors can be used to reduce signals
greater than 1Vrms before they reach the ADC.
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface.
ADC DIGITAL FILTER
The ADC digital filters contain a digital high pass filter. The high-pass filter response detailed in
Digital Filter Characteristics. The operation of the high pass filter removes residual DC offsets that
are present on the audio signal.
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DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
DOUT: ADC data output
LRCLK: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT
and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with
left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left
or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always
an output. BCLK and LRCLK maybe an inputs or outputs depending whether the device is in Master
or Slave mode. (see Master and Slave Mode Operation, below).
Three different audio data formats are supported:
Left justified
Right justified
I
2
S
MASTER AND SLAVE MODE OPERATION
The WM8781 can be configured as either a master or slave mode device. As a master device the
WM8781 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT.
In slave mode, the WM8781 responds with data to clocks it receives over the digital audio interface.
The mode can be selected by setting the MS input pin (see Table 4 Master/Slave selection below).
Master and slave modes are illustrated below.
Figure 5 Master Mode
Figure 6 Slave Mode
PIN
DESCRIPTION
M/S
Master/Slave Selection
0 = Slave Mode
1= Master Mode
Table 4 Master/Slave selection
AUDIO INTERFACE CONTROL
The Input Word Length and Audio Format mode can be selected by using IWL and FORMAT pins.
PIN
DESCRIPTION
IWL
Word Length
0 = 16 bit
1 = 20 bit
Z = 24 bit
FORMAT
Audio Mode Select
0 = RJ
1 = LJ
Z = I2S
Table 5 Audio Data Format Control
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AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 7 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 8 Right Justified Audio Interface (assuming n-bit word length)
In I
2
S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 9 I
2
S Audio Interface (assuming n-bit word length)
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MASTER CLOCK AND AUDIO SAMPLE RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system's
Master Clock (MCLK). The external master system clock can be applied directly through the MCLK
input pin. In a system where there are a number of possible sources for the reference clock it is
recommended that the clock source with the lowest jitter be used to optimise the performance of the
ADC.
The master clock is used to operate the digital filters and the noise shaping circuits. The WM8781
supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio
sampling frequency (LRCLK). In Slave Mode, the WM8781 automatically detects the audio sample
rate. In Master Mode, LRCLK is generated for rate 384fs, unless the user changes this to 192fs
using the FSAMPEN pin = z (see Table 7 below). BCLK is also generated in Master Mode, where
BCLK=64fs.
Table 6 shows the common MCLK frequencies for different sample rates.
Master Clock Frequency (MHz)
SAMPLING RATE
(LRCLK)
128fs
192fs
256fs
384fs
512fs
768fs
8kHz
1.024
1.536
2.048
3.072
4.096
6.144
16kHz
2.048
3.072
4.096
6.144
8.192
12.288
32kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1kHz
5.6448
8.467
11.2896
16.9340 22.5792 33.8688
48kHz
6.144
9.216
12.288
18.432
24.576
36.864
96kHz
12.288
18.432
24.576
36.864
-
-
192kHz
24.576
36.864
-
-
-
-
Table 6 Master Clock Frequency Selection
In Slave mode, the WM8781 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available
(768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8781 is tolerant of
phase variations or jitter on these clocks.
The WM8781 can operate at sample rates from 8kHz to 192kHz. The WM8781 uses a sigma-delta
modulator that operates at a fixed frequency of 6.144MHz (128 x LRCLK oversampling @ 48kHz
sampling rate). For correct operation of the device and optimal performance, the user must set the
appropriate ADC modulator sampling rate enable. In both Master and Slave Modes, it is
recommended that for 96kHz the user sets FSAMPEN to 1, and for 192kHz set FSAMPEN to z. For
Master Mode 192kHz, FSAMPEN set to z is a requirement.
PIN
DESCRIPTION
M/S
Master/Slave Selection
0 = Slave Mode (128fs, 192fs,
256fs, 384fs, 512fs, 768fs)
1= Master Mode (384fs, 192fs
when FSAMPEN=z)
FSAMPEN
Fast sampling rate enable
0 = 48kHz enable (128x OSR)
1 = 96kHz enable (64x OSR)
z = 192kHz enable (32x OSR)
Table 7 Master/Slave and Sampling Rate Enable Selection
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POWER DOWN CONTROL
The WM8781 can be powered down by stopping MCLK. Power down mode using MCLK is entered
after 65536/fs clocks. On power-up, the WM8781 applies the power-on reset sequence described
below.
When MCLK is stopped DOUT is forced to zero.
POWER ON RESET
Figure 10 Power Supply Timing Requirements power-on
Figure 11 Power Supply Timing Requirements power-down
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Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = DGND = 0V, T
A
= +25C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
DVDD level to activate POR
power on
V
pora
Measured from DGND
0.7
V
AVDD level to activate POR
power on
V
pora
Measured from AGND
0.7
V
VMID level to activate POR
power on
V
pora
Measured from AGND
0.7
V
DVDD level to release POR
power on (see notes 1 and 2)
V
porr
Measured from DGND
DVDD Min
V
AVDD level to release POR
power on (see notes 1 and 2)
V
porr
Measured from AGND
AVDD Min
V
VMID level to release POR
power on (see notes 1 and 2)
V
porr
Measured from AGND
1
V
POR active period (see notes 1
and 2)
t
por
Measured from POR active to
POR release
30
(note 6)
Defined by DVDD/AVDD/
VMID Rise Time
s
DVDD level to activate POR
power off (see note 5)
V
por_off
Measured from DGND
0.8
V
AVDD level to activate POR
power off (see note 5)
V
por_off
Measured from AGND
0.8
V
VMID level to activate POR
power off (see note 5)
V
por_off
Measured from AGND
0.7
V
Power on - POR propagation
delay through device
t
pon
Measured from rising EDGE of
POR
30
s
Power down - POR propagation
delay through device
t
poff
Measured from falling EDGE of
POR
30
s
Notes:
1.
POR is activated when DVDD or AVDD or VMID reach their stated V
pora
level (Figure 10).
2.
POR is only released when DVDD and AVDD and VMID have all reached their stated V
porr
levels (Figure 10).
3.
The rate of rise of VMID depends on the rate of rise of AVDD, the internal 50k resistance and the external decoupling
capacitor. Typical tolerance of 50K resistor can be taken as +/-20%.
4.
If AVDD, DVDD or VMID suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go
below V
por_off,
), then the chip will not reset and will resume normal operation when the voltage is back to the
recommended level again.
5.
The chip will enter reset at power down when AVDD or DVDD or VMID falls below V
por_off
. This may be important if the
supply is turned on and off frequently by a power management system.
6.
The minimum t
por
period is maintained even if DVDD, AVDD and VMID have zero rise time. This specification is
guaranteed by design rather than test.
WM8781
Production Data
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PD, April 2006, Rev 4.1
16
DIGITAL FILTER CHARACTERISTICS
The WM8781 digital filter characteristics scale with sample rate.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Sample Rate (Single Rate 48Hz typically)
+/- 0.01dB
0
0.4535fs
Passband
-6dB
0.4892fs
Passband Ripple
+/- 0.01
dB
Stopband
0.5465fs
Stopband Attenuation
f > 0.5465fs
-65
dB
Group Delay
22
fs
ADC Sample Rate (Dual Rate 96kHz typically)
+/- 0.01dB
0
0.4535fs
Passband
-6dB
0.4892fs
Passband Ripple
+/- 0.01
dB
Stopband
0.5465fs
Stopband Attenuation
f > 0.5465fs
-65
dB
Group Delay
22
fs
Table 8 Digital Filter Characteristics
ADC FILTER RESPONSES
-80
-60
-40
-20
0
0
0.5
1
1.5
2
2.5
3
Response (dB)
Frequency (Fs)
-0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Response (dB)
Frequency (Fs)
Figure 12 Digital Filter Frequency Response
Figure 13 ADC Digital Filter Ripple
Production Data
WM8781
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PD, April 2006, Rev 4.1
17
ADC HIGH PASS FILTER
The WM8781 has a digital highpass filter to remove DC offsets. The filter response is characterised by the following
polynomial.
Figure 14 ADC Highpass Filter Response
1 - z
-1
1 - 0.9995z
-1
H(z) =
-15
-10
-5
0
0
0.0005
0.001
0.0015
0.002
Response (dB)
Frequency (Fs)
WM8781
Production Data
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PD, April 2006, Rev 4.1
18
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 15 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C8
10
F
De-coupling for DVDD and AVDD
C2 and C7
0.1
F
De-coupling for DVDD and AVDD
C5 and C6
10
F
Analogue input AC coupling caps
R1
10k
Current limiting resistors
R2 and R5
10k
Internal op-amp input resistor
R3 and R6
5k
Internal op-amp feedback resistor
R4
3.3k
Common mode resistor
C4
0.1
F
C3
10
F
Reference de-coupling capacitors for VMID pin
C9
0.1
F
C10
10
F
Reference de-coupling capacitors for VREFP pin
Table 9 External Components Description
Production Data
WM8781
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PD, April 2006, Rev 4.1
19
PACKAGE DIMENSIONS
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
DM0015.C
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
Symbols
Dimensions
(mm)
MIN
NOM
MAX
A
-----
-----
2.0
A
1
0.05
-----
-----
A
2
1.65
1.75
1.85
b
0.22
0.30
0.38
c
0.09
-----
0.25
D
6.90
7.20
7.50
e
0.65 BSC
E
7.40
7.80
8.20
5.00
5.30
5.60
L
0.55
0.75
0.95
REF:
A A2
A1
SEATING PLANE
-C-
0.10 C
10
1
D
11
20
e
b
E1
E
-
JEDEC.95, MO 150
0
o
4
o
8
o
E
1
L
1
1.25 REF
c
L
GAUGE
PLANE
0.25
L
1
WM8781
Production Data
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PD, April 2006, Rev 4.1
20
IMPORTANT NOTICE
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service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
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standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
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