REV 1.2.0 2/13/01 James Tsang
Characteristics subject to change without notice.
1 of 19
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X1203
2-Wire
TM
RTC
Real Time Clock/Calendar/Alarm
FEATURES
2 alarms--interrupt output
--Settable on the second, minute, hour, day,
month, or day of the week
--Repeat alarm for time base generation
2-wire interface interoperable with I
2
C
--400kHz data transfer rate
Secondary power supply input with internal
switch-over circuitry
Low power CMOS
--<1A operating current
--<3mA active current during program
--<400A active current during data read
Typical nonvolatile write cycle time: 5ms
High reliability
Small package options
--8-lead SOIC package, 8-lead TSSOP package
DESCRIPTION
The X1203 is a Real Time Clock with clock/calendar
circuits and two alarms. The dual port clock and alarm
registers allow the clock to operate, without loss of
accuracy, even during read and write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
An alarm match of the RTC sets an interrupt flag and
activates an interrupt pin. An alternative alarm function
provides a pulsed interrupt for long time constant time-
bases.
The device offers a backup power input pin. This
V
BACK
pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational from
2.7 to 5.5 Volts and the RTC portion of the X1203
device remains fully operational down to 1.8 Volts.
BLOCK DIAGRAM
X1
X2
Oscillator
Frequency
Timer
Logic
Divider
Calendar
8
32.768kHz
Control
Registers
1Hz
Time
Keeping
Registers
Alarm Regs
Compare
Mask
IRQ
Control
Decode
Logic
Alarm
(EEPROM)
(EEPROM)
SCL
SDA
Serial
Interface
Decoder
Interrupt Enable
Registers
Status
(SRAM)
Alarm
Alarm
(SRAM)
X1203
Characteristics subject to change without notice.
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PIN CONFIGURATION
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speeds.
V
BACK
This input provides a backup supply voltage to the
device. V
BACK
supplies power to the device in the
event the V
CC
supply fails.
Interrupt Output - IRQ
This is an interrupt signal output. This signal notifies a
host processor that alarm has occurred and requests
action. It is an open drain active LOW output.
X1, X2
The X1 and X2 pins are the input and output, respec-
tively, of an inverting amplifier that can accept an external
32.768kHz square wave reference on X1 or can be con-
figured for use as an on-chip oscillator. A 32.768kHz
quartz crystal such as a Citizen CFS-206 is used with the
on-chip oscillator. The crystal supplies a timebase for a
clock/oscillator, see figure 1. Using an external time-
base, the internal clock is driven by the external signal
on X1, with X2 left unconnected.
Figure 1. Recommended Crystal Connection
POWER CONTROL OPERATION
The Power control circuit accepts a V
CC
and a V
BACK
input. The power control circuit will switch to V
BACK
when V
CC
< V
BACK
0.2V. It will switch back to V
CC
when V
CC
exceeds V
BACK
.
Figure 2. Power Control
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal network or timebase to maintain an
accurate internal representation of the year, month,
day, date, hour, minute, and seconds. The RTC has
leap-year correction and a century byte. The clock will
also correct for months having fewer than 31 days and
will have a bit that controls 24-hour or AM/PM format.
After power up, when both V
CC
and V
BACK
fail, the
clock will not advance unless at least one byte is written
to the RTC register.
Reading the Real Time Clock
The RTC is read by initiating a read command and
specifying the address corresponding to the register of
the real time clock. The RTC registers can then be read
in a sequential read mode. Since the clock runs contin-
uously and a read takes a finite amount of time, there
is the possibility that the clock could change during the
X1203
X1
X2
V
BACK
V
CC
IRQ
SCL
SDA
V
SS
1
2
3
4
7
8
6
5
8-Pin TSSOP
X1203
X1
X2
V
BACK
V
CC
IRQ
SCL
SDA
V
SS
1
2
3
4
7
8
6
5
8-Pin SOIC
X1
X2
68pF
12pF
360K
10M
V
BACK
V
CC
= V
BACK
-0.2V
Internal
Voltage
V
CC
X1203
Characteristics subject to change without notice.
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course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a sepa-
rate latch to avoid time changes during the read opera-
tion. The clock continues to run. Alarms occurring
during a read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC reg-
isters. To avoid changing the current time by an incom-
plete write operation, the current time value is loaded
into a separate buffer at the falling edge of the clock on
the ACK bit before the RTC data input bytes, the clock
continues to run. The new serial input data replaces the
values in the buffer. This new RTC value is loaded back
into the RTC register by a stop bit at the end of a valid
write sequence. An invalid write operation aborts the
time update procedure and the contents of the buffer are
discarded. After a valid write operation the RTC will
reflect the newly loaded data beginning with the first
"one second" clock cycle after the stop bit. The RTC
continues to update the time while an RTC register write
is in progress and the RTC continues to run during any
nonvolatile write sequences. A single byte may be writ-
ten to the RTC without affecting the other bytes.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area log-
ically separated from the array and are only accessible
following a slave byte of "1101111x" and reads or
writes to addresses [0000h:003Fh].
CCR Access
The contents of the CCR can be modified by performing
a byte or a page write operation directly to any address
in the CCR. Prior to writing to the CCR (except the status
register), however, the WEL and RWEL bits must be
set using a two step process (See section "Writing to
the Clock/Control Registers.")
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes)
2. Alarm 1 (8 bytes)
3. Control (1 byte)
4. Real Time Clock (8 bytes)
5. Status (1 byte)
Sections 1) through 3) are nonvolatile and Sections 4)
and 5) are volatile. Each register is read and written
through buffers. The non volatile portion (or the counter
portion of the RTC) is updated only if RWEL is set and
after a valid write operation and stop bit. A sequential
read or page write operation provides access to the
contents of only one section of the CCR per operation.
Access to another section requires a new operation.
Continued reads or writes, once reaching the end of a
section, will wrap around to the start of the section. A
read or page write can begin at any address in the CCR.
Section 5) is a volatile register. It is not necessary to
set the RWEL bit prior to writing the status register.
Section 5) supports a single byte read or write only.
Continued reads or writes from this section terminates
the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read. The
read instruction latches all Clock registers into a buffer,
so an update of the clock does not change the time
being read. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next register.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24-hour time selection bit. The enable
bits specify which registers to use in the comparison
between the alarm and real time registers. For example:
The user can set the X1203 to alarm every Wednesday
at 8:00AM by setting the EDWn, the EHRn and EMNn
enable bits to `1' and setting the DWAn, HRAn and
MNAn Alarm registers to 8:00AM Wednesday.
A daily alarm for 9:30PM results when the EHRn and
EMNn enable bits are set to `1' and the HRAn and
MNAn registers set 9:30PM.
Setting the EMOn bit in combination with other
enable bits and a specific alarm time, the user can
establish an alarm that triggers at the same time
once a year.
X1203
Characteristics subject to change without notice.
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When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits, or by setting the AL0E and AL1E bits
to `1' and monitoring the IRQ output. The AL0E and
AL1E bits enable the circuit that triggers the output
IRQ pin when an alarm occurs. Writing a `0' to one of
the bits disables the output IRQ for that alarm condi-
tion, but the alarm condition can still be checked by
polling the alarm flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to `0',
there are no alarms.
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
Bit
Factory
Settings
7
6
5
4
3
2
1
0
(optional)
Range
003F
Status
SR
BAT
AL1
AL0
0
0
RWEL
WEL
RTCF
01h
0037
RTC
(SRAM)
Y2K
0
0
Y2K21
Y2K20
Y2K13
0
0
Y2K10
20
xxh
0036
DW
0
0
0
0
0
DY2
DY1
DY0
0-6
xxh
0035
YR
Y23
Y22
Y21
Y20
Y13
Y12
Y11
Y10
0-99
xxh
0034
MO
0
0
0
G20
G13
G12
G11
G10
1-12
xxh
0033
DT
0
0
D21
D20
D13
D12
D11
D10
1-31
xxh
0032
HR
T24
0
H21
H20
H13
H12
H11
H10
0-23
xxh
0031
MN
0
M22
M21
M20
M13
M12
M11
M10
0-59
xxh
0030
SC
0
S22
S21
S20
S13
S12
S11
S10
0-59
xxh
0011
Control
(EEPROM)
INT
IM
AL1E
AL0E
0
0
0
0
0
00h
000F
Alarm1
(EEPROM)
Y2K1
0
0
A1Y2K21
A1Y2K20
A1Y2K13
0
0
A1Y2K10
20
20h
000E
DWA1
EDW1
0
0
0
0
DY2
DY1
DY0
0-6
00h
000D
YRA1
Unused--Default = RTC Year value
000C
MOA1
EMO1
0
0
A1G20
A1G13
A1G12
A1G11
A1G10
1-12
00h
000B
DTA1
EDT1
0
A1D21
A1D20
A1D13
A1D12
A1D11
A1D10
1-31
00h
000A
HRA1
EHR1
0
A1H21
A1H20
A1H13
A1H12
A1H11
A1H10
0-23
00h
0009
MNA1
EMN1
A1M22
A1M21
A1M20
A1M13
A1M12
A1M11
A1M10
0-59
00h
0008
SCA1
ESC1
A1S22
A1S21
A1S20
A1S13
A1S12
A1S11
A1S10
0-59
00h
0007
Alarm0
(EEPROM)
Y2K0
0
0
A0Y2K21
A0Y2K20
A0Y2K13
0
0
A0Y2K10
20
20h
0006
DWA0
EDW0
0
0
0
0
DY2
DY1
DY0
0-6
00h
0005
YRA0
Unused--Default = RTC Year value
0004
MOA0
EMO0
0
0
A0G20
A0G13
A0G12
A0G11
A0G10
1-12
00h
0003
DTA0
EDT0
0
A0D21
A0D20
A0D13
A0D12
A0D11
A0D10
1-31
00h
0002
HRA0
EHR0
0
A0H21
A0H20
A0H13
A0H12
A0H11
A0H10
0-23
00h
0001
MNA0
EMN0
A0M22
A0M21
A0M20
A0M13
A0M12
A0M11
A0M10
0-59
00h
0000
SCA0
ESC0
A0S22
A0S21
A0S20
A0S13
A0S12
A0S11
A0S10
0-59
00h
X1203
Characteristics subject to change without notice.
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REV 1.2.0 2/13/01
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REAL TIME CLOCK REGISTERS
Year 2000 (Y2K)
The X1203 has a century byte that "rolls over" from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Day of the Week Register (DW)
This register provides a Day of the week status and
uses three bits DY2 to DY0 to represent the seven days
of the week. The counter advances in the cycle 0-1-2-
3-4-5-6-0-1-2-... The assignment of a numerical value
to a specific day of the week is arbitrary and may be
decided by the system software designer. The Clock
Default value defines as `0'.
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with T24 = 1), DT (Date)
is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
24-Hour Time
If the T24 bit of the HR register is 1, the RTC will use a
24-hour format. If the T24 bit is 0, the RTC will use 12-
hour format and bit H21 will function as an AM/PM indi-
cator with a `1' representing PM. The clock defaults to
standard time with H21 = 0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1203 does not correct for
the leap year in the year 2100.
STATUS REGISTER (SR)
The status register is located in the RTC area at address
003Fh. This is a volatile register only and is used to con-
trol the WEL and RWEL write enable latches, read an
optional low voltage sense bit, and read the two alarm
bits. This register is logically separated from both the
array and the clock/control registers (CCR).
Table 2. Status Register (SR)
BAT: Battery Supply--Volatile
This bit set to "1" indicates that the device is operating
from V
BACK
, not V
CC
. It is a read only bit and is set/
reset by hardware.
AL1, AL0: Alarm Bits--Volatile
These bits announce if either alarm 1 or alarm 2 match
the real time clock. If there is a match, the respective
bit is set to `1'. The falling edge of the last data bit in a
SR Read operation resets the flags.
Note:
Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
RWEL: Register Write Enable Latch--Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to "1" prior
to any writes to the clock/control registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence.
WEL: Write Enable Latch--Volatile
The WEL bit controls the access to the CCR during a
write operation. This bit is a volatile latch that powers
up in the LOW (disabled) state. While the WEL bit is
LOW, writes to the CCR will be ignored (no acknowl-
edge will be issued after the Data Byte). The WEL bit is
set by writing a "1" to the WEL bit and zeroes to the
other bits of the status register. Once set, WEL
remains set until either reset to 0 (by writing a "0" to the
WEL bit and zeroes to the other bits of the status regis-
ter) or until the part powers up again. Writes to WEL bit
do not cause a non volatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
Addr
7
6
5
4
3
2
1
0
003Fh
BAT
AL1
AL0
x
x
RWEL
WEL
RTCF
Default
0
0
0
0
0
0
0
1
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