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Электронный компонент: X22C10SI

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X22C10
1
Nonvolatile Static RAM
Xicor, Inc. 1991,1995 Patents Pending
Characteristics subject to change without notice
3815-2.4 7/26/96 T0/CO/D3 SH
FEATURES
High Performance CMOS
--120ns RAM Access Time
High Reliability
--Store Cycles: 1,000,000
--Data Retention: 100 Years
Low Power Consumption
--Active: 40mA Max.
--Standby: 100
A Max.
Infinite Array Recall, RAM Read and Write Cycles
Nonvolatile Store Inhibit: V
CC
= 3.5V Typical
Fully TTL and CMOS Compatible
JEDEC Standard 18-Pin 300-mil DIP
100% Compatible with X2210
--With Timing Enhancements
DESCRIPTION
The X22C10 is a 64 x 4 CMOS NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a non-
volatile E
2
PROM. The NOVRAM design allows data to
be easily transferred from RAM to E
2
PROM (STORE)
and from E
2
PROM to RAM (RECALL). The STORE
operation is completed within 5ms or less and the
RECALL is completed within 1
s.
Xicor NOVRAMs are designed for unlimited write opera-
tions to the RAM, either RECALLs from E
2
PROM or
writes from the host. The X22C10 will reliably endure
1,000,000 STORE cycles. Inherent data retention is
greater than 100 years.
NONVOLATILE E
2
PROM
MEMORY ARRAY
ROW
SELECT
STATIC RAM
MEMORY ARRAY
COLUMN SELECT
INPUT
DATA
CONTROL
CONTROL
LOGIC
VCC
VSS
COLUMN
I/O CIRCUITS
STORE
RECALL
I/O1
I/O2
I/O3
I/O4
CS
WE
A3
A4
A5
ARRAY
RECALL
STORE
A0
A1
A2
3815 FHD F01
256 Bit
X22C10
64 x 4
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
3815 FHD F02
PLASTIC DIP
CERDIP
NC
A4
A3
A2
A1
A0
CS
VSS
STORE
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VCC
NC
A5
I/O4
I/O3
I/O2
I/01
WE
X22C10
RECALL
3815 FHD F08.1
A4
A3
A2
A1
A0
CS
VSS
STORE
1
VCC
A5
I/O4
I/O3
I/O2
I/O1
WE
RECALL
X22C10
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SOIC
SOIC
X22C10
2
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (A
0
A
5
)
The address inputs select a 4-bit memory location
during a read or write operation.
Chip Select (
CS
)
The Chip Select input must be LOW to enable read or
write operations with the RAM array.
CS
HIGH will place
the I/O pins in the high impedance state.
Write Enable (
WE
)
The Write Enable input controls the I/O buffers, deter-
mining whether a RAM read or write operation is en-
abled. When
CS
is LOW and
WE
is HIGH, the I/O pins
will output data from the selected RAM address loca-
tions. When both
CS
and
WE
are LOW, data presented
at the I/O pins will be written to the selected address
location.
Data In/Data Out (I/O
1
I/O
4
)
Data is written to or read from the X22C10 through the
I/O pins. The I/O pins are placed in the high impedance
state when either
CS
is HIGH or during either a store or
recall operation.
STORE
The
STORE
input, when LOW, will initiate the transfer of
the entire contents of the RAM array to the E
2
PROM
array. The
WE
and
RECALL
inputs are inhibited during
the store cycle. The store operation is completed in 5ms
or less.
A store operation has priority over RAM read/write
operations. If
STORE
is asserted during a read opera-
tion, the read will be discontinued. If
STORE
is asserted
during a RAM write operation, the write will be immedi-
ately terminated and the store performed. The data at
the RAM address that was being written will be unknown
in both the RAM and E
2
PROM arrays.
RECALL
The
RECALL
input, when LOW, will initiate the transfer
of the entire contents of the E
2
PROM array to the RAM
array. The transfer of data will be completed in 1
s or
less.
An array recall has priority over RAM read/write opera-
tions and will terminate both operations when
RECALL
is asserted.
RECALL
LOW will also inhibit the
STORE
input.
Automatic Recall
Upon power-up the X22C10 will automatically recall
data from the E
2
PROM array into the RAM array.
Write Protection
The X22C10 has three write protect features that are
employed to protect the contents of the nonvolatile
memory.
V
CC
Sense--All functions are inhibited when V
CC
is
<3.5V typical.
Write Inhibit--Holding either
STORE
HIGH or
RECALL
LOW during power-up or power-down will
prevent an inadvertent store operation and E
2
PROM
data integrity will be maintained.
Noise Protection--A
STORE
pulse of typically less
than 20ns will not initiate a store cycle.
PIN NAMES
Symbol
Description
A
0
A
5
Address Inputs
I/O
1
I/O
4
Data Inputs/Outputs
WE
Write Enable
CS
Chip Select
RECALL
Recall
STORE
Store
V
CC
+5V
V
SS
Ground
NC
No Connect
3815 PGM T01
X22C10
3
ABSOLUTE MAXIMUM RATINGS
Temperature under Bias .................. 65
C to +135
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to V
SS .......................................
1V to +7V
D.C. Output Current ............................................ 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300
C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
CAPACITANCE T
A
= +25
C, f = 1MHz, V
CC
= 5V
Symbol
Parameter
Max.
Units
Test Conditions
C
I/O
(1)
Input/Output Capacitance
8
pF
V
I/O
= 0V
C
IN
(1)
Input Capacitance
6
pF
V
IN
= 0V
3815 PGM T03
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
l
CC
V
CC
Supply Current,
40
mA
CS
= V
IL
, I/Os = Open, All Others =
RAM Read/Write
V
IH
, Addresses = 0.4V/2.4V Levels @
f = 8MHz
I
SB1
V
CC
Standby Current
2
mA
Store or Recall Functions Not Active,
(TTL Inputs)
I/Os = Open, All Other Inputs = V
IH
I
SB2
V
CC
Standby Current
100
A
Store or Recall functions Not Active,
(CMOS Inputs)
I/Os = Open, All Other Inputs =
V
CC
0.3V
I
LI
Input Leakage Current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= V
SS
to V
CC
V
lL
(2)
Input LOW Voltage
1
0.8
V
V
IH
(2)
Input HIGH Voltage
2
V
CC
+ 1
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 4.2mA
V
OH
Output HIGH Voltage
2.4
V
I
OH
= 2mA
3815 PGM T02.3
Supply Voltage
Limits
X22C10
5V
10%
3815 PGM T13
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Military
55
C
+125
C
3815 PGM T12.1
Notes: (1) This parameter is periodically sampled and not 100% tested.
(2) V
IL
min. and V
IH
max. are for reference only and are not tested.
X22C10
4
MODE SELECTION
CE
WE
RECALL
STORE
I/O
Mode
H
X
H
H
Output High Z
Not Selected
(3)
L
H
H
H
Output Data
Read RAM
L
L
H
H
Input Data HIGH
Write "1" RAM
L
L
H
H
Input Data LOW
Write "0" RAM
X
H
L
H
Output High Z
Array Recall
H
X
L
H
Output High Z
Array Recall
X
H
H
L
Output High Z
Nonvolatile Store
(4)
H
X
H
L
Output High Z
Nonvolatile Store
(4)
3815 PGM T05.1
POWER-UP TIMING
Symbol
Parameter
Max.
Units
t
PUR
(5)
Power-up to Read Operation
100
s
t
PUW
(5)
Power-up to Write or Store Operation
5
ms
3815 PGM T07
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
Data Changes Per Bit
Store Cycles
1,000,000
Store Cycles
Data Retention
100
Years
3815 PGM T06
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
Input Rise and
Fall Times
10ns
Input and Output
Timing Levels
1.5V
3815 PGM T04.1
EQUIVALENT A.C. LOAD CIRCUIT
Notes: (3) Chip is deselected but may be automatically completing a store cycle.
(4)
STORE
= LOW is required only to initiate the store cycle, after which the store cycle will be automatically completed
(e.g.
STORE
= X).
(5) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These
parameters are periodically sampled and not 100% tested.
3815 FHD F09.1
919
497
OUTPUT
100pF
5V
X22C10
5
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
Min.
Max.
Units
t
RC
Read Cycle Time
120
ns
t
AA
Access Time
120
ns
t
CO
Chip Select to Output Valid
120
ns
t
OH
Output Hold from Address Change
0
ns
t
LZ
(6)
Chip Select to Output in Low Z
0
ns
t
HZ
(6)
Chip Deselect to Output in High Z
50
ns
3815 PGM T08
Read Cycle
3815 FHD F03
CS
ADDRESS
tRC
tCO
tA
tHZ
tLZ
DATA I/O
tOH
DATA VALID
Note:
(6) t
LZ
min. and t
HZ
min. are periodically sampled and not 100% tested.