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DS029 (v1.3) June 25, 2000
www.xilinx.com
1
Product Specification
1-800-255-7778
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
XQ4000X Series Features
Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing)
Ceramic and plastic packages
Also available under the following standard microcircuit
drawings (SMD)
-
XQ4013XL 5962-98513
-
XQ4036XL 5962-98510
-
XQ4062XL 5962-98511
-
XQ4085XL 5962-99575
For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
Available in -3 speed
System featured Field-Programmable Gate Arrays
-
SelectRAMTM memory: on-chip ultra-fast RAM with
synchronous write option
dual-port RAM option
-
Abundant flip-flops
-
Flexible function generators
-
Dedicated high-speed carry logic
-
Wide edge decoders on each edge
-
Hierarchy of interconnect lines
-
Internal 3-state bus capability
-
Eight global low-skew clock or signal distribution
networks
System performance beyond 50 MHz
Flexible array architecture
Low power segmented routing architecture
Systems-oriented features
-
IEEE 1149.1-compatible boundary scan logic
support
-
Individually programmable output slew rate
-
Programmable input pull-up or pull-down resistors
-
12 mA sink current per XQ4000XL output
Configured by loading binary file
-
Unlimited reprogrammability
Readback capability
-
Program verification
-
Internal node observability
Development system runs on most common computer
platforms
-
Interfaces to popular design environments
-
Fully automatic mapping, placement and routing
-
Interactive design editor for design optimization
Highest capacity--over 180,000 usable gates
Additional routing over XQ4000E
-
Almost twice the routing capacity for high-density
designs
Buffered Interconnect for maximum speed
New latch capability in configurable logic blocks
Improved VersaRingTM I/O interconnect for better Fixed
pinout flexibility
-
Virtually unlimited number of clock signals
Optional multiplexer or 2-input function generator on
device outputs
5V tolerant I/Os
0.35
m SRAM process
Introduction
The QPROTM XQ4000XL Series high-performance,
high-capacity Field Programmable Gate Arrays (FPGAs)
provide the benefits of custom CMOS VLSI, while avoiding
the initial cost, long development cycle, and inherent risk of
a conventional masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
Refer to the complete Commercial XC4000XL Series Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)
0
QPRO XQ4000XL Series QML
High-Reliability FPGAs
DS029 (v1.3) June 25, 2000
0
2
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
2
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
R
Table 1: XQ4000XL Series High Reliability Field Progammable Gate Arrays
Device
Logic
Cells
Max
Logic
Gates
(No
RAM)
(1)
Max.
RAM
Bits (No
Logic)
Typical Gate
Range
(Logic and
RAM)
(1)
CLB
Matrix
Total
CLBs
Number
of
Flip-Flops
Max.
User
I/O
Packages
XQ4013XL
2432
13,000
18,432
10,000-30,000
24x24
576
1,536
192
PG223, CB228,
PQ240, BG256
XQ4036XL
3078
36,000
41,472
22,000-65,000
36x36
1,296
3,168
288
PG411, CB228,
HQ240, BG352
XQ4062XL
5472
62,000
73,728
40,000-130,000
48x48
2,304
5,376
384
PG475, CB228,
HQ240, BG432
XQ4085XL
7448
85,000
100,352
55,000-180,000
56x56
3,136
7,168
448
PG475, CB228,
HQ240, BG432
Notes:
1.
Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM.
QPRO XQ4000XL Series QML High-Reliability FPGAs
DS029 (v1.3) June 25, 2000
www.xilinx.com
3
Product Specification
1-800-255-7778
R
XQ4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for production.
Preliminary:
Based on preliminary characterization. Further changes are not expected.
Unmarked:
Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c.
parameter delay specifications included in this document
are derived from measuring internal test patterns. All speci-
fications are representative of worst-case supply voltage
and junction temperature conditions. The parameters
included are common to popular designs and typical appli-
cations. For design considerations requiring more detailed
timing information, see the appropriate family AC supple-
ments available on the Xilinx web site at:
http://www.xilinx.com/partinfo/databook.htm
.
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
Symbol
Description
Units
V
CC
Supply voltage relative to GND
0.5 to 4.0
V
V
IN
Input voltage relative to GND
(2)
0.5 to 5.5
V
V
TS
Voltage applied to High-Z output
(2)
0.5 to 5.5
V
V
CCt
Longest supply voltage rise time from 1V to 3V
50
ms
T
STG
Storage temperature (ambient)
65 to +150
C
T
SOL
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
+260
C
T
J
Junction temperature
Ceramic package
+150
C
Plastic package
+125
C
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2.
Maximum DC overshoot or undershoot above V
CC
or below GND must be limited to either 0.5V or 10 mA, whichever is easier to
achieve. During transitions, the device pins may undershoot to 2.0 V or overshoot to V
CC
+ 2.0V, provided this over- or undershoot
lasts less than 10 ns and with the forcing current being limited to 200 mA.
Symbol
Description
Min
Max
Units
V
CC
Supply voltage relative to GND, T
J
= 55
C to +125
C
Plastic
3.0
3.6
V
Supply voltage relative to GND, T
C
= 55
C to +125
C
Ceramic
3.0
3.6
V
V
IH
High-level input voltage
(2)
50% of V
CC
5.5
V
V
IL
Low-level input voltage
0
30% of V
CC
V
T
IN
Input signal transition time
-
250
ns
Notes:
1.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C.
2.
Input and output measurement threshold is ~50% of V
CC
.
QPRO XQ4000XL Series QML High-Reliability FPGAs
4
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
R
XQ4000XL DC Characteristics Over Recommended Operating Conditions
Power-On Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current
capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast
ramp-up time requires more current than a slow ramp-up
time. The slowest ramp-up time is 50 ms. Current capacity
is not specified for a ramp-up time faster than 2 ms. The cur-
rent capacity varies linealy with ramp-up time, e.g., an
XQ4036XL with a ramp-up time of 25 ms would require a
capacity predicted by the point on the straight line drawn
from 1A at 120
s to 500 mA at 50 ms at the 25 ms time
mark. This point is approximately 750 mA
.
Symbol
Description
Min
Max
Units
V
OH
High-level output voltage at I
OH
= 4 mA, V
CC
min (LVTTL)
2.4
-
V
High-level output voltage at I
OH
= 500
A, (LVCMOS)
90% V
CC
-
V
V
OL
Low-level output voltage at I
OL
= 12 mA, V
CC
min (LVTTL)
(1)
-
0.4
V
Low-level output voltage at I
OL
= 1500
A, (LVCMOS)
-
10% V
CC
V
V
DR
Data retention supply voltage (below which configuration data may be lost)
2.5
-
V
I
CCO
Quiescent FPGA supply current
(2)
-
5
mA
I
L
Input or output leakage current
10
+10
A
C
IN
Input capacitance (sample tested)
BGA, PQ, HQ, packages
-
10
pF
PGA packages
-
16
pF
I
RPU
Pad pull-up (when selected) at V
IN
= 0V (sample tested)
0.02
0.25
mA
I
RPD
Pad pull-down (when selected) at V
IN
= 3.6V (sample tested)
0.02
0.15
mA
I
RLL
Horizontal longline pull-up (when selected) at logic Low
0.3
2.0
mA
Notes:
1.
With up to 64 pins simultaneously sinking 12 mA.
2.
With no output current loads, no active input or Longline pull-up resistors, all I/O pins in a High-Z state and floating.
Product
Description
Ramp-up Time
Fast (120
s)
Slow (50 ms)
XQ4013 - 36XL
Minimum required current supply
1A
500 mA
XC4062XL
Minimum required current supply
2A
500 mA
XC4085XL
(1)
Minimum required current supply
2A
(1)
500 mA
Notes:
1.
The XC4085XL fast ramp-up time is 5 ms.
2.
Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a
larger initialization current.
3.
This specification applies to Commercial and Industrial grade products only.
4.
Ramp-up Time is measured from 0V
DC
to 3.6V
DC
. Peak current required lasts less than 3 ms, and occurs near the internal power
on reset threshold voltage. After initialization and before configuration, I
CC
max is less than 10 mA.
QPRO XQ4000XL Series QML High-Reliability FPGAs
DS029 (v1.3) June 25, 2000
www.xilinx.com
5
Product Specification
1-800-255-7778
R
XQ4000XL AC Switching Characteristic
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)
Global Buffer Switching Characteristics
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
Symbol
Description
Device
All
Min
-3
-1
Units
Max
Max
T
GLS
Delay from pad through Global Low Skew buffer, to any
clock K
XQ4013XL
0.6
3.6
-
ns
XQ4036XL
1.1
4.8
-
ns
XQ4062XL
1.4
6.3
-
ns
XQ4085XL
1.6
-
5.7
ns
Symbol
Description
Device
All
Min
-3
-1
Units
Max
Max
T
GE
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6.
XQ4013XL
0.4
2.4
-
ns
XQ4036XL
0.3
3.1
-
ns
XQ4062XL
0.3
4.9
-
ns
XQ4085XL
0.4
-
4.7
ns
Symbol
Description
Device
All
Min
-3
-1
Units
Max
Max
T
GE
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8.
XQ4013XL
0.7
2.4
-
ns
XQ4036XL
0.9
4.7
-
ns
XQ4062XL
1.2
5.9
-
ns
XQ4085XL
1.3
-
5.5
ns