DS092 (v1.2) May 13, 2002
www.xilinx.com
1
Advance Product Specification
1-800-255-7778
2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Optimized for 1.8V systems
-
As fast as 4.0 ns pin-to-pin logic delays
-
As low as 15
A quiescent current
-
64 macrocells with up to 1,600 logic gates
-
Fast input registers
-
Slew rate control on individual outputs
-
LVCMOS 1.8V through 3.3V
-
1.5V I/O compatible
-
LVTTL 3.3V
Available in multiple package options
-
44-pin PLCC with 33 user I/O
-
44-pin VQFP with 33 user I/O
-
56-ball CP BGA with 45 user I/O
-
100-pin VQFP with 64 user I/O
Advanced system features
-
Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
-
IEEE1149.1 JTAG Boundary Scan Test
-
Optional Schmitt-trigger input (per pin)
-
Fast Zero PowerTM (FZP) 100% CMOS product
term generation
-
Flexible clocking modes
Optional DualEDGE triggered registers
-
Global signal options with macrocell control
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
-
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
-
Advanced design security
-
Open-drain output option for Wired-OR and LED
drive
-
Optional configurable grounds on unused I/Os
-
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
-
PLA architecture
Superior pinout retention
100% product term routability across function
block
-
Hot pluggable
Refer to the CoolRunnerTM-II family data sheet for architec-
ture description.
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "fast input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asyncho-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see
Table 1
). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
0
XC2C64 CoolRunner-II CPLD
DS092 (v1.2) May 13, 2002
0
0
Advance Product Specification
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XC2C64 CoolRunner-II CPLD
2
www.xilinx.com
DS092 (v1.2) May 13, 2002
1-800-255-7778
Advance Product Specification
R
Fast Zero Power Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
Fast Zero PowerTM (FZP), a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. FZP design technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high performance
and low power operation.
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See
Table 1
for I/O stan-
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II CPLDs are also 1.5V I/O compatible with the
use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C64
I/O Types
Output
V
CCIO
Input
V
CCIO
Input
V
REF
Board
Termination
Voltage V
T
LVTTL
3.3
3.3
N/A
N/A
LVCMOS33
3.3
3.3
N/A
N/A
LVCMOS25
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
1.5V I/O
1.5
1.5
N/A
N/A
Figure 1: I
CC
vs Frequency
Table 2: I
CC
vs Frequency (LVCMOS 1.8V T
A
= 25C)
(1)
Frequency (MHz)
0
25
50
75
100
150
175
200
225
250
270
Typical -5, -7.5 I
CC
(mA)
0.015
1.85
3.69
5.55
7.35
10.87
12.54
14.22
15.91
17.56
18.9
Typical -4 I
CC
(mA)
Notes:
1.
16-bit up/down, resettable binary counter (one counter per function block).
Frequency (MHz)
DS092_01_030102
I CC
(mA)
0
0
5
10
15
20
300
250
200
150
100
-5, -7.5
50
XC2C64 CoolRunner-II CPLD
DS092 (v1.2) May 13, 2002
www.xilinx.com
3
Advance Product Specification
1-800-255-7778
R
Recommended Operating Conditions
DC Electrical Characteristics
(Over Recommended Operating Conditions)
Absolute Maximum Ratings
Symbol
Description
Value
Units
V
CC
Supply voltage relative to ground
0.5 to 2.0
V
V
CCIO
Supply voltage for output drivers
0.5 to 4.0
V
V
JTAG
JTAG input voltage limits
0.5 to 4.0
V
V
AUX
JTAG input supply voltage
0.5 to 4.0
V
V
IN
Input voltage relative to ground
(1)
0.5 to 4.0
V
V
TS
Voltage applied to 3-state output
(1)
0.5 to 4.0
V
T
STG
Storage Temperature (ambient)
65 to +150
C
T
SOL
Maximum Soldering temperature (10s @ 1/16in. = 1.5mm)
+260
C
T
J
Junction Temperature
+150
C
Notes:
1.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to 2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
Symbol
Parameter
Min
Max
Units
V
CC
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0C to +70C
1.7
1.9
V
Industrial T
A
= 40C to +85C
1.7
1.9
V
V
CCIO
Supply voltage for output drivers @ 3.3V operation
3.0
3.6
V
Supply voltage for output drivers @ 2.5V operation
2.3
2.7
V
Supply voltage for output drivers @ 1.8V operation
1.7
1.9
V
Supply voltage for output drivers @ 1.5V operation
1.4
1.6
V
V
AUX
JTAG programming pins
1.7
3.6
V
Symbol
Parameter
Test Conditions
Min.
Max.
Units
I
CCSB
Standby current (-5, -7)
V
CC
= 1.9V, V
CCIO
= 3.6V
100
A
I
CCSB
Standby current (-4)
V
CC
= 1.9V, V
CCIO
= 3.6V
mA
I
CC
Dynamic current (-5, -7)
f = 1 MHz
mA
f = 50 MHz
mA
I
CC
Dynamic current (-4)
f = 1 MHz
mA
f = 50 MHz
mA
C
JTAG
JTAG input capacitance
f = 1 MHz
pF
C
CLK
Global clock input capacitance
f = 1 MHz
pF
C
IO
I/O capacitance
f = 1 MHz
pF
XC2C64 CoolRunner-II CPLD
DS092 (v1.2) May 13, 2002
www.xilinx.com
5
Advance Product Specification
1-800-255-7778
R
LVCMOS 1.8V DC Voltage Specifications
1.5V DC Voltage Specifications
(1)
Symbol
Parameter
Test Conditions
Min.
Max.
Units
V
CCIO
Input source voltage
1.7
1.9
V
V
IH
High level input voltage
0.7 x V
CCIO
3.9
V
V
IL
Low level input voltage
0.3
0.2 x V
CCIO
V
V
OH
High level output voltage
I
OH
= 8 mA, V
CCIO
= 1.7V
V
CCIO
0.45
-
V
I
OH
= 0.1 mA, V
CCIO
= 1.7V
V
CCIO
0.2
-
V
V
OL
Low level output voltage
I
OL
= 8 mA, V
CCIO
= 1.7V
-
0.45
V
I
OL
= 0.1 mA, V
CCIO
= 1.7V
-
0.2
V
I
IL
Input leakage current
V
IN
= 0 or V
CCIO
to 3.9V
10
10
A
I
IH
I/O High-Z leakage
V
IN
= 0 or V
CCIO
to 3.9V
10
10
A
C
JTAG
JTAG input capacitance
f = 1 MHz
pF
C
CLK
Global clock input capacitance
f = 1 MHz
pF
C
IO
I/O capacitance
f = 1 MHz
pF
Symbol
Parameter
Test Conditions
Min.
Max.
Units
V
CCIO
Input source voltage
1.4
1.6
V
V
IH
High level input voltage
0.7 x V
CCIO
3.9
V
V
IL
Low level input voltage
0.3
0.3
V
V
OH
High level output voltage
I
OH
= 4 mA, V
CCIO
= 1.4V
V
CCIO
0.45
V
I
OH
= 0.1 mA, V
CCIO
= 1.4V
V
CCIO
0.2
V
V
OL
Low level output voltage
I
OL
= 8 mA, V
CCIO
= 1.4V
0.4
V
I
OL
= 0.1 mA, V
CCIO
= 1.4V
0.2
V
I
IL
Input leakage current
V
IN
= 0 or V
CCIO
to 3.9V
10
10
A
I
IH
I/O High-Z leakage
V
IN
= 0 or V
CCIO
to 3.9V
10
10
A
C
JTAG
JTAG input capacitance
f = 1 MHz
pF
C
CLK
Global clock input capacitance
f = 1 MHz
pF
C
IO
I/O capacitance
f = 1 MHz
pF
Notes:
1.
Hysteresis used on 1.5V inputs.
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