January 10, 2000
1
Virtual IP Group, Inc.
1095 E. Duane Ave., Suite 211
Sunnyvale, CA 94086 USA
Phone:
+1 408-733-3344
Fax:
+1 408-733-9922
E-mail:
sales@virtualipgroup.com
URL: www.virtualipgroup.com
Features
Available under terms of the SignOnce IP License
Supports Spartan, Spartan
TM
-II, Virtex
TM
, and Virtex
TM
-E
devices
Multiple, programmable, multi-mode timers
Real-time clock
Event counter
Digital one-shot
Programmable rate generator
Square wave generator
Applications
Binary rate multiplier
Complex waveform generator
Complex motor controller
Baud rate generator
General Description
The M8254 is a programmable interval timer/counter core
designed for use with standard micro-processor systems. It
has three 16 bit counters, each of which is programmable
to generate an interrupt at the end of a user-defined inter-
val.
Notes:
1. Assuming all core I/O are routed off-chip.
2. Utilization numbers for Virtex are in CLB slices.
AllianceCORETM Facts
Core Specifics
Supported Family
Spartan
Virtex
Device Tested
S40-3
V300-4
CLBs
260
244
2
Clock IOBs
3
3
IOBs
1
19
19
Performance (MHz)
12.4 MHz
34 MHz
Xilinx Core Tools
M1.3
M1.5i
Special Features
None
None
Provided with Core
Documentation
Core Design Document
Design File Formats
EDIF netlist,.ngd,
Verilog Source RTL available extra
Constraints File
m8254.ucf
Verification
Test vectors
Instantiation
Templates
VHDL, Verilog
Reference Designs
& Application Notes
None
Additional Items
None
Simulation Tool Used
Verilog XL, version 2.6
Support
Support provided by Virtual IP Group Inc.
M8254 Programmable Timer
January 10, 2000
Product Specification
M8254 Programmable Timer
January 10, 2000
2
Functional Description
The M8254 Core is partitioned into modules as shown in
Figure1 and described below.
Bus Interface Block
This block contains decoders to generate counter select
and the counter control select signals.
Counter 0-2 Blocks
These independently programmable counter blocks gener-
ate output based on the mode selected.
Core Modifications
Virtual IP Group, Inc. can modify this core to vary the num-
ber of timers.
Pinout
The pinout has not been fixed to specific FPGA I/O allowing
flexibility with the user application. Signal names are pro-
vided in the block diagram shown in Figure 1 and described
in Table 1.
Verification Methods
The core has been tested with in-house developed test vec-
tors that are provided with the core.
Table 1: Core Signal Pinout
Recommended Design Experience
Knowledge of microprocessor based systems is required.
The user must be familiar with HDL design methodology, in-
stantiation of Xilinx netlists in a hierarchical design environ-
ment and usage of Xilinx Alliance or Foundation
development tools.
Signal
Signal
Direction
Description
Bus Interface Signals
a0i, a1i
Input
Address Signals
ncsi
Input
Chip select, active low
nrdi
Input
Read signal, active low
nwri
Input
Write signal, active low
dbus[7:0]
In/Out
8-bit bidirectional CPU data
bus
1
Counter Signals
out0o
Output
Output of counter 0
clk0i
Input
Clock input for counter 0
gate0i
Input
Gate input for counter 0
out1o
Output
Output of counter 1
clk1i
Input
Clock input for counter 1
gate1i
Input
Gate input for counter 1
out2o
Output
Output of counter 2
clk2i
Input
Clock input for counter 2
gate2i
Input
Gate input for counter 2
Notes:
1. Bus expanded into individual nets in the design.
Figure 1: M8254 Block Diagram
Virtual IP Group Inc.
January 10, 2000
3
Ordering Information
This AllianceCORE product is available from Xilinx Alli-
anceCORE partner, Virtual IP Group, Inc., under terms of
the SignOnce IP License. To learn about the SignOnce IP
License program, contact Virtual IP Group, visit www.xil-
inx.com/ipcenter/signonce.htm, or write to commonli-
cense@xilinx.com.
Please contact Virtual IP Group, Inc. for pricing and addi-
tional information about this AllianceCORE product.
Related Information
Xilinx Programmable Logic
For information on Xilinx programmable logic or develop-
ment system software, contact your local Xilinx sales office,
or:
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Phone:
+1 408-559-7778
Fax:
+1 408-559-7114
URL:
www.xilinx.com
For general Xilinx literature, contact:
Phone:
+1 800-231-3386 (inside the US)
+1 408-879-5017 (outside the US)
E-mail:
literature@xilinx.com
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