DS073 (v1.0) July 26, 2000

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Advance Product Specification

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Features

One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices

Simple interface to the FPGA; configurable to use a
one user I/O pin

Cascadable for storing longer or multiple bitstreams

Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions

Supports fast configuration

Low-power CMOS Floating Gate process

3.3V supply voltage

Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20

Programming support by leading programmer
manufacturers.

Design support using the Xilinx Alliance and
Foundation series software packages.

Dual configuration modes for the XC17V16 and
XC17V08

Serial slow/fast configuration (up to 33 MHz)

Parallel (up to 264 MHz)

Guaranteed 20 year life data retention

Description

Xilinx introduces the high-density XC17V00 family of config-
uration PROMs which provide an easy-to-use, cost-effec-
tive method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities.

When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.

When the FPGA is in SelectMAP mode, an external oscilla-
tor will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the PROMs DATA (D0-D7) pins. The data will
be clocked into the FPGA on the following rising edge of the
CCLK. SelectMAP does not utilize a Length Count, so a
free-running oscillator may be used. See

Figure 3

Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.

For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.

XC17V00 Series Configuration
PROM

DS073 (v1.0) July 26, 2000

Advance Product Specification

XC17V00 Series Configuration PROM

DS073 (v1.0) July 26, 2000

www.xilinx.com

Advance Product Specification

1-800-255-7778

Pin Description

DATA[0:7]

Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the D0 pin is I/O.
Note that OE can be programmed to be either active High or
active Low.

Note: XC17V04, XC17V02, and XC17V01 have serial output
only.

CLK

Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.

RESET/OE

When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The polar-
ity of this input pin is programmable as either RESET/OE or
OE/RESET. To avoid confusion, this document describes
the pin as RESET/OE, although the opposite polarity is pos-
sible on all devices. When RESET is active, the address
counter is held at "0", and puts the DATA output in a
high-impedance state. The polarity of this input is program-
mable. The default is active High RESET, but the preferred
option is active Low RESET, because it can be driven by the
FPGAs INIT pin.

The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have differ-
ent methods to invert this pin.

When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I

standby mode.

CEO

Chip Enable output, to be connected to the CE input of the
next PROM in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.

BUSY (XC17V16 and XC17V08 only)

If BUSY pin is floating, the user must program the BUSY bit
which will cause BUSY pin to go Low internally. When
asserted High, output data are held and when BUSY pin
goes Low, data output will resume.

Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
ation, this pin must be connected to V

. Failure to do so

may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
V

floating!

and GND

Positive supply and ground pins.

PROM Pinouts for XC17V16 and XC17V08

Capacity

Pin Name

44-pin VQFP

44-pin PLCC

BUSY

CLK

RESET/OE
(OE/RESET)

GND

6, 18, 28, 27, 41

3, 12, 24, 34, 43

CEO

8, 16, 17, 26, 36,

14, 22, 23, 32,

42, 44

Devices

Configuration Bits

XC17V16

16,777,216

XC17V08

8,388,608

XC17V00 Series Configuration PROM

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DS073 (v1.0) July 26, 2000

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Advance Product Specification

PROM Pinouts for XC17V04, XC17V02, and
XC17V01

Capacity

Controlling PROMs

Connecting the FPGA device with the PROM.

The DATA output(s) of the of the PROM(s) drives the
D

input of the lead FPGA device.

The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).

The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).

The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V

glitch.

Other methods--such as driving RESET/OE from LDC
or system reset--assume the PROM internal
power-on-reset is always in step with the FPGA's
internal power-on-reset. This may not be a safe
assumption.

The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the D

pin.

The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.

SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.

Pin Name

8-pin

VOIC

20-pin

SOIC

20-pin

PLCC

44-pin

VQFP

44-pin

PLCC

DATA

CLK

RESET/OE
(OE/RESET)

GND

18, 41

24, 3

CEO

Devices

Configuration Bits

XC17V04

4,194,304

XC17V02 2,701,312

XC17V01

1,679,360

Xilinx FPGAs and Compatible PROMs

Device

Configuration

Bits

PROM

XCV50

559,200

XC17V01

XCV100

781,216

XC17V01

XCV150

1,040,096

XC17V01

XCV200

1,335,840

XC17V01

XCV300

1,751,808

XC17V02

XCV400 2,546,048 XC17V02

XCV600 3,607,968 XC17V04

XCV800 4,715,616 XC17V08

XCV1000

6,127,744

XC17V08

XCV50E

630,048

XC17V01

XCV100E

863,840

XC17V01

XCV200E

1,442,106

XC17V01

XCV300E

1,875,648

XC17V02

XCV400E 2,693,440 XC17V02

XCV405E

3,340,400

XC17V04

XCV600E

3,961,632

XC17V04

XCV812E

6,519,648

XC17V08

XCV1000E

6,587,520

XC17V08

XCV1600E

8,308,992

XC17V08

XCV2000E

10,159,648

XC17V16

XCV2600E

12,922,336

XC17V16

XCV3200E

16,283,712

XC17V16

Notes:
1.

The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.

Xilinx FPGAs and Compatible PROMs

Device

Configuration

Bits

PROM

XC17V00 Series Configuration PROM

DS073 (v1.0) July 26, 2000

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Advance Product Specification

1-800-255-7778

FPGA Master Serial Mode Summary

The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are estab-
lished by a configuration program. The program is loaded
either automatically upon power up, or on command,
depending on the state of the three FPGA mode pins. In
Master Serial mode, the FPGA automatically loads the con-
figuration program from an external memory. The Xilinx
PROMs have been designed for compatibility with the Mas-
ter Serial mode.

Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA
mode-select pins are Low (M0=0, M1=0, M2=0). Data is
read from the PROM sequentially on a single data line. Syn-
chronization is provided by the rising edge of the temporary
signal CCLK, which is generated during configuration.

Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the PROM is
read sequentially, accessed via the internal address and bit
counters which are incremented on every valid rising edge
of CCLK.

If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up resistor.

Programming the FPGA With Counters
Unchanged Upon Completion

When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left

unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.

This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
therefore, reads the remaining data in the PROM and inter-
prets it as preamble, length count etc. Since the FPGA is
the master, it issues the necessary number of CCLK pulses,
up to 16 million (2

) and DONE goes High. However, the

FPGA configuration will be completely wrong, with potential
contentions inside the FPGA and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.

Cascading Configuration PROMs

For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded PROMs provide additional memory. After the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See

Figure 3

After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA RESET pin goes
Low, assuming the PROM reset polarity option has been
inverted.

To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of DIN.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XC17V04SO20I

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: XC17V04SO20I