YAMAHA CORPORATION

YSS901CATALOG

CATALOG No.: LSI-4SS901A0

1999. 1

YSS901

Preliminary

Stereo dipole

g Outline

YSS901 is a device that uses the stereo dipole system (SD) with which the transaural system can be constructed.
When a stereophonic signal that has been processed with the SD system of this device is inputted to two
speakers located adjacently at the center of the field (or to two speakers contained in one cabinet), the virtual
sound positioning function of this system produces the stereophonic sound similar to the one that can be
obtained by using an ordinary stereophonic sound replay system through the central two speakers.
YSS901 has built-in one bit Delta-Sigma type A/D and D/A converters for each of the two channels at its input
and output respectively. Thanks to these built-in converters, this device can process analog stereophonic sound
signal through the converters in addition to digital stereophonic sound signal.
This device performs an advanced convolution through DSP using the FIR filter.

g Features

Two channel virtual sound positioning by using the stereo dipole system.

Processes analog or digital signals at each of the two channels.

Four types of digital data format are available, including 48 fs Serial-DAC16, 18 and 20 bits, and 64 fs.

Six types of parameter coefficients are built in the device. Additional parameter coefficients can be

downloaded externally.

The parameter control is made through the DC switches or synchronous three-wire serial system.

Uses a clock of 2.822 MHz from the crystal. External clock can also be used.

Has a built-in PLL circuit for generating clock for operation.

Internal operating frequency of 512 fs.

Allows fading in or out the output of the results of the convolution when switching the coefficient.

Power supply voltage: 5 V

Si-gate CMOS process.

64 QFP

YSS901

g Pin configuration

<64QFP TOP VIEW>

YSS901

123456789

TSTNI

AILRET

AIR

LOUT

ROUT

TSTNO

AVDD

DSEL2

AVSS

DIN

DOUT

BCLK

DSEL1

DSEL0

SYNCN

CTLSEL

CSEL1

BSFT0

CSN

SCK

RESETN

XTAL

TST2

TSTSEL

DVSS

TSTCK

PLLC

DVSS

EXTAL

AIL

AIRRET

AILOUT

AIROUT

DVSS

DVDD

VREF

CSEL0

CSEL2

BSFT1

DVDD

TST1

N.C

YSS901

g Pin Description

No.

Pin name

I/O

Function

DVDD

Digital signal power supply : +5 V

CTLSEL

Selection of control method

SYNCN

Digital input/output synchronization signal

BCLK

Digital input/output bit clock

CSN

Serial control interface chip select signal

DOUT

Digital signal output

DIN

Digital signal input

DSEL2

Analog/digital input selection

DSEL1

Digital input/output format selection

DSEL0

Digital input/output format selection

DVDD

Digital signal power supply : +5 V

TST2

Test (To be open.)

DVSS

Digital signal ground

AVSS

Analog signal ground

AIRRET

Right channel analog signal input return

AIROUT

Right channel analog signal input out

AIR

Right channel analog signal input

AILRET

Left channel analog signal input return

AILOUT

Left channel analog signal input out

AIL

Left channel analog signal input

VREF

Analog signal VREF

AVDD

Analog signal power supply : +5 V

LOUT

Left channel analog signal output

ROUT

Right channel analog signal output

PLLC

PLL auxiliary input

AVSS

Analog signal ground

EXTAL

Crystal clock input

XTAL

Crystal clock output

DVSS

Digital signal ground

TSTCK

Test (Connect with DVSS.)

TST1

Test (To be open.)

TSTNI

Test (Connect with DVSS.)

TSTNO

Test (To be open.)

DVDD

Digital signal power supply: +5 V

TSTSEL

Test (Connect with DVSS.)

CSEL2

Coefficient selection (Enabled when CTLSEL = 0)

CSEL1

Coefficient selection (Enabled when CTLSEL = 0)

CSEL0

Coefficient selection (Enabled when CTLSEL = 0)

RESETN

Reset signal input

BSFT1

Bit shift selection (Enabled when CTLSEL = 0)

BSFT0

Bit shift selection (Enabled when CTLSEL = 0)

SCK

Serial control interface clock input

Serial control interface data input

DVSS

Digital signal ground

Notes:
1. Pins of No. 1 to 4, 16 to 20, 32 to 36, 48 to 52 and 64 are to be open.
2.

I: input pin

O: output pin

AI: analog signal input pin

AO: analog output pin.

YSS901

g Outline of Functions

Clock signals

XTAL, EXTAL

and

PLLC

For the clock signal, use the crystal connected to XTAL EXTAL pin with which the clock signal is obtained by the
self-oscillation at the crystal oscillation circuit, or external signal supplied through EXTAL pin. The frequency of the
clock obtained by the self-oscillation is 2.822 MHz (or 44.1 kHz * 64). The internal operation is carried out with 512
fs clock that is made by the PLL.
Insert an analog filter in between PLLC and GND pins.

2. Data input/output signals

Analog/digital input selection pin:

DSEL2

This pin is used to select a type of the input signal. DSEL2 = 0 selects the digital signal input, or DSEL2 = 1 selects
the analog signal input.

2-1) Digital signal

Digital signal input/output pins:

DIN, BCLK, SYNCN

and

DOUT

Digital signals should be inputted through DIN, BCLK and SYNCN pins.
DIN signal (PCM data) must be in synchronous with BCLK (bit clock) and SYNCN (word clock) signals.
Digital signal is outputted from DOUT pin.

Input/output format designation pins:

DSEL1

and

DSEL0

These pins are used to designate a data format for DAC. The settings of DSEL1 and DSEL0 and their output formats
are as follows.

DSEL1 DSEL0

DAC output format

48 fs 16 bits Data LSB justified

48 fs 18 bits Data LSB justified (Bits 1 and 0 are "0".)

48 fs 20 bits Data LSB justified (Bits 3 through 0 are "0".)

64 fs 16 bits Data MSB justified (Delay by one bit)

For the details of the format, refer to "Serial Data Interface" explained later in this document.

2-2) Analog signal

Analog input/output pins:

AIL, AILOUT, AILRET, LOUT, AIR, AIROUT, AIRRET

and

ROUT

Analog signals should be inputted through AIL and AIR pins. The signals that have been processed by the stereo
dipole (SD) are outputted from LOUT and ROUT pins respectively. Add an analog filter circuit, an example of
which is shown later in this document.

Center voltage pin

VREF

This pin outputs a reference voltage for analog signal processing. Connect an appropriate capacitor between VREF
and GND pins.

3. Controlling functions

3-1) Control method selection pin:

CTLSEL

This pin is used for selection of a control method as described below.

CTLSEL = 0 : Selection of CSEL2, CSEL1 or CSEL0 by means of DC switch (H/L) is enabled.
CTLSEL = 1 : Selection of CSN, SI or SCK through the microcomputer is enabled.

Электронный компонент: YSS901