YAMAHA CORPORATION

YSS901CATALOG

CATALOG No.: LSI-4SS901A0

1999. 1

YSS901

Preliminary

Stereo dipole

g Outline

YSS901 is a device that uses the stereo dipole system (SD) with which the transaural system can be constructed.
When a stereophonic signal that has been processed with the SD system of this device is inputted to two
speakers located adjacently at the center of the field (or to two speakers contained in one cabinet), the virtual
sound positioning function of this system produces the stereophonic sound similar to the one that can be
obtained by using an ordinary stereophonic sound replay system through the central two speakers.
YSS901 has built-in one bit Delta-Sigma type A/D and D/A converters for each of the two channels at its input
and output respectively. Thanks to these built-in converters, this device can process analog stereophonic sound
signal through the converters in addition to digital stereophonic sound signal.
This device performs an advanced convolution through DSP using the FIR filter.

g Features

Two channel virtual sound positioning by using the stereo dipole system.

Processes analog or digital signals at each of the two channels.

Four types of digital data format are available, including 48 fs Serial-DAC16, 18 and 20 bits, and 64 fs.

Six types of parameter coefficients are built in the device. Additional parameter coefficients can be

downloaded externally.

The parameter control is made through the DC switches or synchronous three-wire serial system.

Uses a clock of 2.822 MHz from the crystal. External clock can also be used.

Has a built-in PLL circuit for generating clock for operation.

Internal operating frequency of 512 fs.

Allows fading in or out the output of the results of the convolution when switching the coefficient.

Power supply voltage: 5 V

Si-gate CMOS process.

64 QFP

YSS901

g Pin configuration

<64QFP TOP VIEW>

YSS901

123456789

TSTNI

AILRET

AIR

LOUT

ROUT

TSTNO

AVDD

DSEL2

AVSS

DIN

DOUT

BCLK

DSEL1

DSEL0

SYNCN

CTLSEL

CSEL1

BSFT0

CSN

SCK

RESETN

XTAL

TST2

TSTSEL

DVSS

TSTCK

PLLC

DVSS

EXTAL

AIL

AIRRET

AILOUT

AIROUT

DVSS

DVDD

VREF

CSEL0

CSEL2

BSFT1

DVDD

TST1

N.C

YSS901

g Pin Description

No.

Pin name

I/O

Function

DVDD

Digital signal power supply : +5 V

CTLSEL

Selection of control method

SYNCN

Digital input/output synchronization signal

BCLK

Digital input/output bit clock

CSN

Serial control interface chip select signal

DOUT

Digital signal output

DIN

Digital signal input

DSEL2

Analog/digital input selection

DSEL1

Digital input/output format selection

DSEL0

Digital input/output format selection

DVDD

Digital signal power supply : +5 V

TST2

Test (To be open.)

DVSS

Digital signal ground

AVSS

Analog signal ground

AIRRET

Right channel analog signal input return

AIROUT

Right channel analog signal input out

AIR

Right channel analog signal input

AILRET

Left channel analog signal input return

AILOUT

Left channel analog signal input out

AIL

Left channel analog signal input

VREF

Analog signal VREF

AVDD

Analog signal power supply : +5 V

LOUT

Left channel analog signal output

ROUT

Right channel analog signal output

PLLC

PLL auxiliary input

AVSS

Analog signal ground

EXTAL

Crystal clock input

XTAL

Crystal clock output

DVSS

Digital signal ground

TSTCK

Test (Connect with DVSS.)

TST1

Test (To be open.)

TSTNI

Test (Connect with DVSS.)

TSTNO

Test (To be open.)

DVDD

Digital signal power supply: +5 V

TSTSEL

Test (Connect with DVSS.)

CSEL2

Coefficient selection (Enabled when CTLSEL = 0)

CSEL1

Coefficient selection (Enabled when CTLSEL = 0)

CSEL0

Coefficient selection (Enabled when CTLSEL = 0)

RESETN

Reset signal input

BSFT1

Bit shift selection (Enabled when CTLSEL = 0)

BSFT0

Bit shift selection (Enabled when CTLSEL = 0)

SCK

Serial control interface clock input

Serial control interface data input

DVSS

Digital signal ground

Notes:
1. Pins of No. 1 to 4, 16 to 20, 32 to 36, 48 to 52 and 64 are to be open.
2.

I: input pin

O: output pin

AI: analog signal input pin

AO: analog output pin.

YSS901

g Outline of Functions

Clock signals

XTAL, EXTAL

and

PLLC

For the clock signal, use the crystal connected to XTAL EXTAL pin with which the clock signal is obtained by the
self-oscillation at the crystal oscillation circuit, or external signal supplied through EXTAL pin. The frequency of the
clock obtained by the self-oscillation is 2.822 MHz (or 44.1 kHz * 64). The internal operation is carried out with 512
fs clock that is made by the PLL.
Insert an analog filter in between PLLC and GND pins.

2. Data input/output signals

Analog/digital input selection pin:

DSEL2

This pin is used to select a type of the input signal. DSEL2 = 0 selects the digital signal input, or DSEL2 = 1 selects
the analog signal input.

2-1) Digital signal

Digital signal input/output pins:

DIN, BCLK, SYNCN

and

DOUT

Digital signals should be inputted through DIN, BCLK and SYNCN pins.
DIN signal (PCM data) must be in synchronous with BCLK (bit clock) and SYNCN (word clock) signals.
Digital signal is outputted from DOUT pin.

Input/output format designation pins:

DSEL1

and

DSEL0

These pins are used to designate a data format for DAC. The settings of DSEL1 and DSEL0 and their output formats
are as follows.

DSEL1 DSEL0

DAC output format

48 fs 16 bits Data LSB justified

48 fs 18 bits Data LSB justified (Bits 1 and 0 are "0".)

48 fs 20 bits Data LSB justified (Bits 3 through 0 are "0".)

64 fs 16 bits Data MSB justified (Delay by one bit)

For the details of the format, refer to "Serial Data Interface" explained later in this document.

2-2) Analog signal

Analog input/output pins:

AIL, AILOUT, AILRET, LOUT, AIR, AIROUT, AIRRET

and

ROUT

Analog signals should be inputted through AIL and AIR pins. The signals that have been processed by the stereo
dipole (SD) are outputted from LOUT and ROUT pins respectively. Add an analog filter circuit, an example of
which is shown later in this document.

Center voltage pin

VREF

This pin outputs a reference voltage for analog signal processing. Connect an appropriate capacitor between VREF
and GND pins.

3. Controlling functions

3-1) Control method selection pin:

CTLSEL

This pin is used for selection of a control method as described below.

CTLSEL = 0 : Selection of CSEL2, CSEL1 or CSEL0 by means of DC switch (H/L) is enabled.
CTLSEL = 1 : Selection of CSN, SI or SCK through the microcomputer is enabled.

YSS901

3-2) Speaker arrangement angle and virtual sound position angle

3-2-1) Setting by means of DC switches:

CSEL2, CSEL1, CSEL0

and

CTLSEL

By setting CTLSEL to "0", and setting CSEL 2, 1 and 0 as following, the positioning angle between the front two
speakers and the virtual sound positioning angle can be selected.

stereo dipole

Stereo Input

Real Source

Virtual Source

Listener

Speaker positioning Virtual

CSEL2 CSEL1 CSEL0 angle (a) sound position (b)

0 0 0 10 degrees 60 degrees

0 0 1 10 degrees 120 degrees

0 1 0 15 degrees 60 degrees

0 1 1 15 degrees 120 degrees

1 0 0 20 degrees 60 degrees

1 0 1 20 degrees 120 degrees

1 1 0 External coefficien1t downloadable

1 1 1 Through (SD effect is disabled.)

* Your original coefficients can be written by an external microprocessor.

(Technical material is under preparation)

3-2-2) Control through CPU

CSN, SCK, SI

and

CTLSEL

Data can be written into the control registers through the serial microcomputer interface by using three pins including
CSN, SCK and SI.

For the details of the read/write timing, refer to the format diagram shown in the next page.

3-3) Bit shift

BSFT1, BSFT0

and

CTLSEL

This function is used to specify the amount of bit shift after the addition of the results of filtering.
CTLSEL = 0 enables the settings of BSF1 and BSF0.
The relation between the combinations of settings of BSF1 and BSF0 and the amount of bit shift is as shown below.

BSFT1 BSFT 0 Bit shift

None

-1 bit

-2 bit

-3 bit

CTLSEL = 1 enables the control of bit shift amount through the microcomputer interface.

4. Initial clear

RESETN

This LSI requires an initial clear at power on moment.

5. LSI test pins

TST1, TST2, TSTCK, TSTSEL, TSTNI

and

TSTNO

TST1, TST2 and TST0 are to be open. TSTCK, TSTSEL and TSTNI should be connected with DVSS.

YSS901

g Serial Microcomputer Interface

Format for writing data through microcomputer

After setting the address (A0 and A1) through SI, it is possible to write data (D0 to D7) into the specified address
when R/W bit has been set to "0". The address map is as shown below.

Address

Data

Description

A1, A0

0 0

CSEL0

CSEL1

CSEL2

BSFT0

BSFT1

D5 to D7

To be "0".

0 1

Write address selection

Write address counter clear

RAM clear

D3 to D7

To be "0".

1 0

D7 to D0

Coefficient data to be written (higher byte)

1 1

D7 to D0

Coefficient data to be written (lower byte)

How to write coefficient data into RAM

Two coefficients are used as a set, each constituted with 16 bits x 125 taps.
The first coefficient ("coef1" shown in the block diagram) is written into RAM address 0-124, and the second one
("coef2" shown in the block diagram) into RAM address 125-249.

The address counter for writing the data uses seven (7) bits, the upper bit (8th bit) uses "write address selection" of
D2 with A1, A0 = 0 1.

Data writing procedure

(1) Clear the RAM and write address counter. (RAM clear needs up to 2 fs to be completed.)
(2) When the RAM has been cleared, write data into higher byte and then into lower byte starting at the first

byte of the first coefficient. (When the writing into the lower byte has been completed, the data is actually
written into RAM. Wait 1 fs before writing the data into higher byte of the next coefficient.)

(3) When the first coefficient has been written, write the second one by using the same procedure. Set the

"write address selection" bit to "1" when writing data into the 4th tap and after of the second coefficient.

YSS901

g Serial Data Interface

Timing of the serial data interface as shown below

BCLK

SYNCN

DIN,DOUT

(1) Dac 48fs 16bit format

(2) Dac 48fs 18bit format

(3) Dac 48fs 20bit format

(4) 64fs YAMAHA-DSP format

BCLK

SYNCN

DIN,DOUT

BCLK

SYNCN

DIN,DOUT

BCLK

SYNCN

DIN,DOUT

YSS901

g Electrical Characteristics

1. Absolute Maximum Rating

Items

Symbol

Min.

Max.

Unit

Power supply Voltage

VDD

Vss-0.5

Vss+7.0

Input Voltage

Vss-0.5

VDD1+0.5

Input Current

-20

+20

Storage Temperature

Tstg

-50

125

2. Recommended Operating Conditions

Items

Symbol

Min.

Typ.

Max.

Unit

Power supply Voltage

VDD

4.75

5.0

5.25

Operating Temperature

Top

3. DC Characteristics (Condition: Under Recommended Operating Conditions)

Items

Symbol

Condition

Min.

Typ.

Max.

Unit

Input Voltage H level

VIH2 *1

2.2

Input Voltage L level

VIL2 *1

0.8

Output Voltage H level

VOH IOH = -80

mA *2

VDD1-1.0

Output Voltage L level

VOL

IOL = 1.6 mA *2

0.4

Output Capacitance

Power Consumption

500

*1 Applicable to input terminals other than analog terminals
*2 Applicable to output terminals other than analog terminals

YSS901

g Design Example

The figure below shows basic design example that uses YSS901.

Lin

Rin

Analog I/O

Lout

Rout

Digital I/O

Control

XTAL

DC Switch

Serial Ctl

(from CPU)

100k

1.8k

1000p

8.2k

10k

220

560

10k

470p

680

22p

2.8224M

10/16

0.1

YSS901

123456789

TSTNI

AILRET

AIR

LOUT

ROUT

TSTNO

AVDD

DSEL2

AVSS

DIN

DOUT

BCLK

DSEL1

DSEL0

SYNCN

CTLSEL

CSEL1

BSFT0

CSN

SCK

RESETN

XTAL

TST2

TSTSEL

DVSS

TSTCK

PLLC

DVSS

EXTAL

AIL

AIRRET

AILOUT

AIROUT

DVSS

DVDD

VREF

CSEL0

CSEL2

BSFT1

DVDD

TST1

N.C

YSS901

Yamaha reserves the right to make changes to its Products and to this document
without notice. The information contained in this document has been carefully checked
and is believed to be reliable. However, Yamaha assumes no responsibilities for
inaccuracies and makes no commitment to update or to keep current the information
contained in this document.

These Yamaha Products are designed only for commercial and normal industrial
applications, and are not suitable for other uses, such as medical life support
equipment, nuclear facilities, critical care equipment or any other application the failure
of which could lead to death, personal injury or environmental or property damage. Use
of the Products in any such application is at the customer's sole risk and expense.

Yamaha assumes no liability for incidental , consequential, or special damages or injury
that may result from misapplication or improper use or operation of the Products.

Yamaha makes no warranty or representation that the Products are subject to
intellectual property license from Yamaha or any third party, and Yamaha makes no
warranty excludes any liability to the Customer or any third party arising from or related
to the Products' infringement of any third party's intellectual property rights, including
the patent, copyright, trademark or trade secret rights of any third party.

Examples of use described herein are merely to indicate the characteristics and
performance of Yamaha products. Yamaha assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the
examples described herein. Yamaha makes no warranty with respect to the products,
express or implied, including, but not limited to the warranties of merchantability, fitness
for a particular use and title.

IMPORTANT NOTICE

The specifications of this product are subject to improvement changes without prior notice.

AGENCY

�

1999

Address inquiries to:
Semiconductor Sales & Marketing Department

Head Office

203, Matsunokijima, Toyooka-mura
Iwata-gun, Shizuoka-ken, 438-0192
Electronic Equipment Business section
Tel. 81-539-62-4918

Fax. 81-539-62-5054

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2-17-11, Takanawa, Minato-ku,
Tokyo, 108-8568
Tel. 81-3-5488-5431

Fax. 81-3-5488-5088

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-13-17, Namba Naka, Naniwa-ku,

Osaka City, Osaka, 556-0011
Tel. 81-6-6633-3690

Fax. 81-6-6633-3691

U.S.A. Office

YAMAHA Systems Technology.
100 Century Center Court, San Jose, CA95112
Tel. 1-408-467-2300

Fax. 1-408-437-8791

Электронный компонент: YSS901-E