YSS912C

AC3D2

Dolby Digital (AC-3) / Pro Logic / DTS decoder + Sub DSP

YSS912C CATALOG

CATALOG No.:LSI-4SS912C2

1999. 3

INTRODUCTION

The YSS912C is one chip LSI consisting two built-in DSP's ; Dolby Digital (AC-3) / Pro Logic / DTS decoder
(Main DSP) and a sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as
virtual surround, by down-loading the program and coefficient. Sub DSP is compatible with YSS902, the Sub DSP
programs developed for YSS902 are also applicable to YSS912C.

FEATURERS

Pin compatible with YSS902 (AC3D).

Dolby Digital (AC-3) / Pro Logic and DTS decode.
24 bit DSP. (Group-A Dolby Digital decoder)

No external memory is required (Memory for center and surround channel delay is included) when DTS

decoding as well as AC-3 / Pro Logic.

Possible to decode multi-language encoded data. (possible to decode based on data-stream-number)
AC-3 karaoke mode.
Original compression mode as well as four compression modes recommended by Dolby. (when AC-3 decoding)

Included de-emphasis filter.
Pro Logic decoding for Dolby digital 2 channels decoded signal as well as ordinary PCM.

High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original

surround , filtering, virtual surround etc.

Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz)

Reads Dolby Digital (AC-3)/DTS decode information through the microprocessor interface.
Provide total sixteen I/O ports.
Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format.
Has a built-in PLL oscillation circuit to generates its own operating clock.

Internal operating clock is 30 MHz.
Supply Voltage: 3.3v for core logic. 5v for I/Os.
Power saving mode.
Si-gate CMOS process.
100 QFP.(YSS912C-F)

Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation.

"DTS" is a registered trademark of DTS, Inc.
Use of this LSI must be licensed by both Dolby Laboratories Licensing Corporation and DTS, Inc.

YSS912C

PIN CONFIGURATION

VDD1

RAMCEN

RAMA16

RAMA15

SDIB0
SDIB1

SDIB2

VSS

AVDD
SDIB3

TEST
TEST

AVSS

VDD2

SDOA2

SDOA1

SDOA0

RAMA14
RAMA13
RAMA12

RAMA11
RAMA10

VSS

VDD1

OPOR

VSS

VDD2

RAMA9

RAMA8

RAMA7

SDOB2

SDOB1

SDOB0

SDBCK1

WCK1

VSS

SI
SO

VSS

RAMD7

RAMD6
RAMD5
RAMD4

RAMD3

RAMD2
RAMD1
RAMD0
VDD1

RAMA2
SCK

/CS

/CSB
RAMA3
TEST

/IC

RAMA4
VSS
RAMA5

RAMA6

/SDBCK0

SURENC
KARAOKE
MUTE
CRC
NONPCM

VDD2

VSS

IPOR

VDD2

VSS

RAMOEN

RAMWEN

RAMA1

RAMA0

SDIA1

SDIA0

SDBCK0

WCK0

VDD2

2
3

4
5
6

7
8

9
10

11
12
13

14
15

16
17
18

19
20
21

22
23
24
25

26
27

28
29

100

CPO

DTSDATA

AC3DATA

SDOB3

OVFB

< 100QFP TOP VIEW >

YSS912C

PIN FUNCTION

No.

Name

I/O

FUNCTION

VDD1

+5V power supply (for I/Os)

RAMCEN

External SRAM interface /CE

RAMA16

External SRAM interface address 16

RAMA15

External SRAM interface address 15

SDIB0

I+

PCM input 0 to Sub DSP

SDIB1

I+

PCM input 1 to Sub DSP

SDIB2

I+

PCM input 2 to Sub DSP

Crystal oscillator connection (12.288 MHz)

Crystal oscillator connection

VSS

Ground

AVDD

+3.3 V power supply (for PLL circuit)

SDIB3

I+

PCM input 3 to Sub DSP

TEST

Test terminal (to be open in normal use)

TEST

Test terminal (to be open in normal use)

OVFB

Detection of overflow at Sub DSP

DTSDATA

Detection of DTS data

AC3DATA

Detection of AC-3 data

SDOB3

PCM output from Sub DSP

CPO

Output terminal for PLL, to be connected to ground through the external analog filter circuit

AVSS

Ground (for PLL circuit)

VDD2

+3.3 V power supply (for core logic)

SDOA2

PCM output from Main DSP (C, LFE)

SDOA1

PCM output from Main DSP (LS, RS )

SDOA0

PCM output from Main DSP (L, R)

RAMA14

External SRAM interface address 14

RAMA13

External SRAM interface address 13

RAMA12

External SRAM interface address 12

RAMA11

External SRAM interface address 11

RAMA10

External SRAM interface address 10

VSS

Ground

VDD1

+5V power supply (for I/Os)

OPORT0

Output port for general purpose

OPORT1

Output port for general purpose

OPORT2

Output port for general purpose

OPORT3

Output port for general purpose

OPORT4

Output port for general purpose

OPORT5

Output port for general purpose

OPORT6

Output port for general purpose

OPORT7

Output port for general purpose

VSS

Ground

VDD2

+3.3 V power supply (for core logic)

RAMA9

External SRAM interface address 9

RAMA8

External SRAM interface address 8

RAMA7

External SRAM interface address 7

SDOB2

PCM output from Sub DSP

SDOB1

PCM output from Sub DSP

SDOB0

PCM output from Sub DSP

SDBCK1

I+

Bit clock input for SDOA, SDIB, SDOB

SDWCK1

I+

Word clock input for SDOA, SDIB, SDOB

VSS

Ground

VDD2

+3.3 V power supply (for core logic)

NONPCM

Detection of non-PCM data

CRC

Detection of AC-3 CRC error

MUTE

Detection of auto mute

55 KARAOKE

Detection of AC-3 karaoke data

YSS912C

No.

Name

I/O

FUNCTION

SURENC

Detection of AC-3 2/0 mode Dolby surround encoded input

/SDBCK0

Inverted SDBCK0 clock output (refer to Block diagram)

RAMA6

External SRAM interface address 6

RAMA5

External SRAM interface address 5

VSS

Ground

RAMA4

External SRAM interface address 4

/IC

Initial clear

TEST

Test terminal (to be open in normal use)

RAMA3

External SRAM interface address 3

/CSB

Is+

Sub DSP Chip select

/CS

Microprocessor interface Chip select input

Microprocessor interface Serial data output

Microprocessor interface / Sub DSP Serial data input

SCK

Microprocessor interface / Sub DSP clock input

RAMA2

External SRAM interface address 2

VDD1

+5V power supply (for I/Os)

RAMD0

I+/ O

External SRAM interface data (STREAM0 output when External SRAM is not in use)

RAMD1

I+/ O

External SRAM interface data (STREAM1 output when External SRAM is not in use)

RAMD2

I+/ O

External SRAM interface data (STREAM2 output when External SRAM is not in use)

RAMD3

I+/ O

External SRAM interface data (STREAM3 output when External SRAM is not in use)

RAMD4

I+/ O

External SRAM interface data (STREAM4 output when External SRAM is not in use)

RAMD5

I+/ O

External SRAM interface data (STREAM5 output when External SRAM is not in use)

RAMD6

I+/ O

External SRAM interface data (STREAM6 output when External SRAM is not in use)

RAMD7

I+/ O

External SRAM interface data (STREAM7 output when External SRAM is not in use)

VSS

Ground

VDD2

+3.3 V power supply (for core logic)

SDWCK0

Word clock input for SDIA, SDOA, SDIB, SDOB

SDBCK0

Bit clock input for SDIA, SDOA, SDIB, SDOB

SDIA0

AC-3 bitstream (or PCM) data input for Main DSP

SDIA1

AC-3 bitstream (or PCM) data input for Main DSP

RAMA1

External SRAM interface address 1

RAMA0

External SRAM interface address 0

RAMWEN

External SRAM interface /WE

RAMOEN

External SRAM interface /OE

VSS

Ground

VDD2

+3.3 V power supply (for core logic)

IPORT7

I+