YTD436 is a high-performance communication LSI for the ISDN BRI user-network
interface function (digital four-wire time-division full-duplex operation), supporting D
channel layer 1 and layer 2 functions in one 100-pin SQFP chip.
YTD436 supports layer 1 (physical layer) control function conforming to ITU-T
Recommendation I.430 and fully supports layer 2 (LAPD protocol) function conforming to
ITU-T Recommendations Q.920 and Q.921. ETSI (European Telecommunication Standards
Institute) and North American standard operating modes are also supported.
In addition, YTD436 includes layer 3 processor interface function which operate in DMA
transfer mode or I/O transfer mode. This gives a great advantage for mounting and
functional designing of both "active" (CPU on board) terminal equipment and "passive" (no
CPU on board) PC cards.
The layer 1 function has a built-in S/T reference point analog driver/receiver to support the
S/T reference point interface. In order to support the U interface, YTD436 also has a I.430
TTL interface (no built-in analog driver/receiver) suitable for connecting to an NT1 chip or
a DSU module.
YTD436
ISTC
ISDN BRI controller with S/T ref. pt. analog D/R
YTD436 CATALOG
CATALOG No.:4TD436A4
2001.1
- 2 -
Features
1. Layer 1 function
Conforms to ITU-T Recommendation I.430 (1992 edition) and
TTC Standard JT-I430 (1997 edition) (default)
- 192 kbps transmission rate
- Interface structure : 2B + D (B = 64 kbps, D = 16 kbps)
- Frame assembling and disassembling function
- Collision control (built-in random number (Ri) reset),
priority control (built-in retransmission control), and state transition control
- Programmable T3 and T4 timers
Supports ETSI ETS 300 012 (April 1992) and ANSI T1.605 operating modes
Leased line capability (JT-I430-a)
Built-in driver and receiver
- I.430 TTL interface (when the driver / receiver is disconnected)
- No external relay or common-mode choke needed
- Supports 1-to-2 pulse transformer
Abundant Test functions (for testing and maintenance)
- Demo mode in which no switch simulator is needed.
- Three kinds of loop-back modes (Loop-back 1 to 3)
- INFO signals output for testing
- Test pulse output for pulse shape check
Multiframing capability
INFO1 transmission and INFO4 reception monitor pins
Power down monitor pin
I.430 transmission frame phase adjustment function
2. Layer 2 function
Conforms to ITU-T Recommendation Q.920 (1992 edition) and Q.921 (1997 edition)
and TTC Standard JT-Q920 (1993 edition) and JT-Q921 (1998 edition)
- HDLC frame control (Flag control, FCS generation/checking,
Automatic zero insertion/deletion, Abort pattern transmission/detection, etc.)
- LAPD status control (Sequence control, Flow control, SAPI control)
- Built-in timer for time-out check
Supports ETSI ETS 300 125 (September 1991), National ISDN-1/2,
AT&T 5ESS 5E9 and Nortel DMS-100 S208-6 operating modes
Multilink capability
(circuit switching
2 links, packet switching/teleaction communications
2 links)
Automatic assigned TEI/non-automatic assigned TEI (VC/PVC)
Leased line mode (disable layer 2 function)
- 3 -
3. Layer 3 interface function
Connects to 8-bit or 16-bit microprocessor
(8086 family, 80186 family, 6800 family, 68000 family)
Operates in one of two data transfer modes :
- DMA transfer mode (with the built-in 16-bit address DMA controller)
- I/O transfer mode (with the built-in FIFO)
Primitive logical interface
4.
B channel interface
Data rate setting : 64 k, 56 k and 32 kbps
Serial mode
- B channel I/O clock selection function
Internal clock mode
Inputs/outputs the B channel data with 64 k, 56 k or 32 kHz internal clock
External clock mode (PCM Highway mode)
Inputs/outputs the B channel data with a 128 k to 2048 kHz external clock
- B channel selection function
Internal clock mode
Selects/switches B channel I/O pins
External clock mode (PCM Highway mode)
Selects/switches B channel time slots
Parallel mode
- LSB/MSB switching function
- Bit shift function
- Data transfer mode
DMA transfer mode with the DMA request function
I/O transfer mode with the built-in FIFO
5.
Low-power operation
(Host processor clock control function, Powerdown mode)
6.
High-performance CMOS technology
7.
100-pin SQFP
8.
DigitalSupply Voltage (+5V or +3.3V ), Analog +5V supply
- 4 -
Applications
ISDN telephone
Video telephone
Telemeter
PBX
Terminal adapter (TA)
Other ISDN terminals
- 5 -
Functional Comparison of YAMAHA ISDN S/T Interface LSIs
Note 1:
Note 2:
Note 3:
YM7405B
YTD418
YTD423
YTD436
YTD410
FUNCTION
1
2
2
2
2
2
2
2
2
(2)
1
Circuit Switching
Dch Packet Switching
(Teleaction Communication)
Internal
Internal
Internal
Internal
External
[YTD421B]
External
56, 64
32, 56, 64
32, 56, 64
64
64
External
External
External
[YTD421B]
Internal
DMA Transfer
DMA Transfer
DMA Transfer
DMA Transfer
or
I/O Transfer
DMA Transfer
or
I/O Transfer
DMA Transfer
or
I/O Transfer
DMA Transfer
or
I/O Transfer
(Note 1)
1992 edition
1992 edition
1993 edition
1993 edition
1993 edition
1993 edition
1993 edition
1993 edition
+5
65
2
30
21
80 Pin QFP
100 pin SQFP
100 pin SQFP
1
125
75
85
+5
+5
+5
+5 or
+3.3
(Note 2)
75 (@+5V)
40 (@+3.3V)
less than 0.5
(Note 3)
1993 edition
1993 edition
1992 edition
1992 edition
1992 edition
1992 edition
1997 edition
1993 edition
1998 edition
1997 edition
1992 edition
1992 edition
1992 edition
1992 edition
Layer 1
I.430
Q.920
Q.921
JT-Q920
JT-Q921
JT-I430
ITU-T Recommendation
TTC Standard
ITU-T Recommendation
TTC Standard
S/T Reference Point Analog Driver/Receiver
D Channel Layer 3 Data Transfer Method
HDLC Controller and
DMA Controller for B Channel Data
B Channel Data Transfer Method
B Channel Internal Clock Mode (kHz)
Maximum D
Channel Links
ETSI
ETS 300 012, ETS 300 125
North American Switches
National ISDN-1/2, AT&T 5ESS,
Nortel DMS-100
Layer 2
(LAPD)
B Channel External Clock Mode
Clock Output Function for MPU
Signal Output Function for Testing
Supply Voltage (V)
DMA Transfer: Request function only
I/O transfer: 4 byte FIFO
With respect to Digital Supply Voltage
State at Line interface disconnection + Power down (SLEEP state)
Power Consumption
during Operation [typ.] (mW)
Power Consumption
during Sleep [typ.] (mW)
80 pin QFP
100 pin TQFP
80 pin QFP
100 pin TQFP
Package
- 6 -
BLOCK DIAGRAM
User Network Interface Block Diagram
YTD436 is the most-suited LSI for terminal equipment such as ISDN telephones and video telephones
and for PHS base stations.
YTD436 contains layer 1 and layer 2 functions, analog driver/receiver for the S/T reference point, DMA
request function for B channel data transfer, and DMA controller for D channel data transfer. Because of
this, terminal equipment can be optimally configured by adding few circuits such as the layer 3 control
processor.
ISDN
Network
YTD436
User's premises
TE1
(ISDN terminal)
NT2
(PBX, etc...)
NT1
(DSU)
TE2
Non-ISDN
terminal
TE2
TA
(Terminal Adapter)
TE1
TE1
DSU
with built-in DSU
T
S/T
R
U
R
S
S
U
S/T
YTD428 (DSU)
(
(
- 7 -
YTD436 Peripheral LSI Interface Block Diagram
YTD436
Memory
Peripheral LSI
B1, B2
Clock
MPU
System
interrupt controller
(8086 , 68000 etc.)
A0 -
A15
D0 -
D15
CS
CS
A0 -
A15
D0 -
D7
R/W
R/W
CS
A0 -
A15
D0 -
D15
LI1
LI2
LO1
LO2
Decoder
Power supply
detection
circuit
A0 -
A15
D0 -
D15
System data bus
(D0
-
D15)
System address bus
(A0
-
A15)
Control signal bus
R/W
R/W
- 8 -
YTD436 Internal Block Diagram
Frame
disassembly
HDLC frame
disassembly
HDLC frame
assembly
Buffer
Buffer
Buffer
Dch
DMAC
Dch
FIFO
Bch
FIFO
Internal
controller
Priority,
collision control
Bch interface
Frame
synchronization
Frame
assembly
Layer 1 control block
Driver/Receiver
block
Layer 2 control block
Layer 3 interface block
Internal bus
Microprocessor
bus
HW/B1, B2 bit
D,E
Clock
generator
To internal clock
CLKOUT
B
S
Q
B
D
D
DPLL
SYNC
Multi-frame
control
Transformer
receiver
Transformer
driver
NRZ/AMI
AMI/NRZ
HRD,
LRD
HTD,
LTD
B channel control block
MPU interface
B1 channel buffer
B1 channel buffer
B2 channel buffer
B2 channel buffer
- 9 -
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A14
A13
A12
A11
A10
A9
DV
SS
DV
DD
A8
A7
A4
A3
A2
A1
D10
D11
D12
D13
D14
D15
DV
SS
X2
HTD
LICT
RM
CLKOUT
51
52
53
54
55
56
57
58
59
60
61
62
63
64
66
67
68
69
70
71
72
73
74
75
65
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
LTD
HRD
INF4
LRD
PSDET
CKOSEL
AS / RD
X1
A6
A5
LI1
CX2
PDET
DV
SS
PDSEL
PDOWN
CS
INF1
DV
DD
YTD436-S
100pin SQFP
DV
SS
A15
WAKEUP
RBHW / RB1
16/8
RX
LO2
CL56K
CL8K
CL4K
TSYNC / TB2
EXTCLK / CL64K
CL128K / CL32K
TBHW / RB2
RSYNC / TB1
CLKSEL
VDSEL
LI2
LO1
AV
SS
AV
DD
CX1
AEN
R/W / WR
MWR
D9
D7
D6
D5
D4
D3
D2
D1
D0
SYSCLK
DMARQR1
DTACK / READY
BR / HLDRQ
DMARQR2
DMARQT1
D8
DV
SS
DV
DD
DMAAK1
BG / HLDAK
BGACK
DMAAK2
DMARQT2
RESET
TEST1
80/68
UBE
A0 / LBE
INT
MRD
- 10 -
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
r
e
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m
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P
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T
g
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0
5
-
5
2
1
+
C
(Based on DV
SS
= AV
SS
= 0.0 V)
Recommended Operating Conditions
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4
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2
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3
6
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3
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5
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O
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o
0
3
-
5
8
C
(Based on DV
SS
= AV
SS
= 0.0 V)
- 11 -
DC Characteristics
When DVDD = 5 V
5 %, AVDD = 5 V
5 % (VDSEL="H", Top = - 30 to + 85 C)
r
e
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e
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P
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(
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4
.
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(
5
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-
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1
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2
.
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1
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(
7
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N
, 9)
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.
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m
)
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1 )
8
.
4
A
m
(
7
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N
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1 )
4
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A
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8
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N
, 0
1 )
1
.
0
A
m
Note 1:
With respect to X1, PSDET, PDET, PDSEL, WAKEUP, RESET, CLKSEL, TEST1, VDSEL
pins (except for the analog pins).
Note 2: With respect to other pins (except for the analog pins).
Note 3: CLKOUT pin
Test condition: I
DOH
= - 1.0 mA, I
DOL
= 2.0 mA
other output pins
Test condition: I
DOH
= - 0.4 mA, I
DOL
= 1.2 mA
Note 4:
HTD, LTD, INT pin Test condition : I
DOL
= 1.2 mA
INF1 pin
Test condition : I
DOL
= 3 mA
RBHW pin
Test condition : R
L
= 500
Note 5:
With respect to cases in which D0 - D15, and A0 - A15 pins are in the input state and MWR and
MRD pins are in Hi-Z state.
Note 6: RUN state (connecting with a B channel, transferring all "0", SYSCLK = 8 MHz, using internal
driver/receiver, assuming as V
DIH
= DV
DD
, V
DIL
= DV
SS
)
Note 7: SLEEP state
Note 8: SLEEP state + Line interface disconnection
Note 9: When SYSCLK is stopped.
Note 10: When using internal driver/receiver
- 12 -
When DVDD = 3.3 V
0.3 V, AVDD = 5 V
5 % (VDSEL="L", Top = - 30 to + 85 C)
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8
.
4
A
m
(
4
e
t
o
N
, 7)
4
.
0
A
m
(
5
e
t
o
N
, 7)
1
.
0
A
m
Note 1:
HTD, LTD, INT, INF1 pin Test condition : I
DOL
= 1.2 mA
RBHW pin
Test condition : R
L
= 500
Note 2:
With respect to cases in which D0 - D15, and A0 - A15 pins are in the input state and MWR and
MRD pins are in Hi-Z state.
Note 3: RUN state (connecting with a B channel, transferring all "0", SYSCLK = 8 MHz, using internal
driver/receiver, assuming as V
DIH
= DV
DD
, V
DIL
= DV
SS
)
Note 4: SLEEP state
Note 5: SLEEP state + Line interface disconnection
Note 6: When SYSCLK is stopped.
Note 7: When using internal driver/receiver
- 13 -
PACKAGE OUTLINE
The specifications of this product are subject to improvement changes without prior notice.
AGENCY
All rights reserved
2001
Address inquiries to:
Semiconductor Sales & Marketing Department
Head Office
203, Matsunokijima, Toyooka-mura
Iwata-gun, Shizuoka-ken, 438-0192
Tel. 81-539-62-4918 Fax. 81-539-62-5054
Tokyo Office
2-17-11, Takanawa, Minato-ku,
Tokyo, 108-8568
Tel. 81-3-5488-5431 Fax. 81-3-5488-5088
Osaka Office
Namba Tsujimoto Nissei Bldg, 4F
1
-13-17, Namba Naka, Naniwa-ku,
Osaka City, Osaka, 556-0011
Tel. 81-6-6633-3690 Fax. 81-6-6633-3691
Yamaha reserves the right to make changes to its Products and to this document
without notice. The information contained in this document has been carefully checked
and is believed to be reliable. However, Yamaha assumes no responsibilities for
inaccuracies and makes no commitment to update or to keep current the information
contained in this document.
These Yamaha Products are designed only for commercial and normal industrial
applications, and are not suitable for other uses, such as medical life support
equipment, nuclear facilities, critical care equipment or any other application the failure
of which could lead to death, personal injury or environmental or property damage. Use
of the Products in any such application is at the customer's sole risk and expense.
Yamaha assumes no liability for incidental , consequential, or special damages or injury
that may result from misapplication or improper use or operation of the Products.
Yamaha makes no warranty or representation that the Products are subject to
intellectual property license from Yamaha or any third party, and Yamaha makes no
warranty excludes any liability to the Customer or any third party arising from or related
to the Products' infringement of any third party's intellectual property rights, including the
patent, copyright, trademark or trade secret rights of any third party.
Examples of use described herein are merely to indicate the characteristics and
performance of Yamaha products. Yamaha assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on
the examples described herein. Yamaha makes no warranty with respect to the
products, express or implied, including, but not limited to the warranties of
merchantability, fitness for a particular use and title.
1.
2.
3.
4.
5.
IMPORTANT NOTICE
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