Page:

Rev. 4.0 December, 1997

P R E L I M I N A R Y D A T A S H E E T

EA-224

 4-Port Fast Ethernet Access Controller

(XpressFlow

T M

2001 Series 10/100 Ethernet Switch Chipset)

1. DISTINCTIVE

CHARACTERISTICS

4 independent 10/100Mbps Ethernet Access Ports

Direct interface with 10BaseT transceiver

IEEE 802.3u compliant MII (Media Independent In-
terface) and Serial Management interface

Direct interface with 100BaseTX, -T2, -T4, or -TF
physical transceivers

State of the art 0.5 micron 3.3Volt CMOS process
352-PIN BGA package
Operating frequency

-33

33 MHz maximum

-40

40 MHz maximum

-50

50 MHz maximum

32-bit Local Buffer Memory Interface

Supports 128k to 1M bytes

Utilize high performance 32-bit Synchronous
Burst SRAM

Hardware assisted Buffer and Queue Management

to minimized CPU overhead

16-bit Processor Bus I/O Interface

Allows host to access Control Registers & Local
Buffer Memory

Supports Big and Little Endian CPUs

Direct interface with various different standard
microprocessors including 386, 486 families and
Motorola MPC series embedded processors.

32-bit XpressFlow Bus Interface

Uses Granule for frame transferring between
Access Controllers

Supports unicast, multicast, and broadcast frames

Also detects IEEE 802.3X MAC Control frames

Works together with SC-201 XpressFlow Engine

Capable to forward frames at full line-rate

Distributed Flow CachingTM to reduce frame for-
warding latency

Supports both Half & Full Duplex operation
Programmable Flow Control Enable

Jam Fake Collision for Half Duplex Mode

Transmit Flow Control Frame for IEEE 802.3x
Full Duplex Mode

Three frame forwarding modes

Store-&-Forward

Safe Cut-Thru (Runt Free)

Turbo Cut-Thru (10Mbps Mode only)

Automatically selects the optimized mode for
forwarding

Allows manual frame forwarding mode selection
override

Multi-Media ready with QoS supports

Four frame transmission priority queues

Complies with IEEE 802.1 Bridge Standard

Assigns one unique MAC Address for each port

VLAN ID Tagging & Stripping

Auto padding if necessary after stripping

Automatic retry frame transmission

Transmit collision

Transmit buffer under-run

Automatic receive filtering for bad frames for Store

& Forward Mode

Bad FCS

Short events or frames under 64 bytes

Long events or frames over 1518 bytes

Automatic statistic collection for RMON

LOCAL

BUFFER

MEMORY

Management BUS

XpressFlow BUS

EA-224

4-Port Ethernet

Access Controller

10/100M BaseTx Xceiver

Port

10/100M BaseTx Ports

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

Rev. 4.0 December, 1997

2. GENERAL DESCRIPTION:

The EA-224 provides four
10/100Mbps Ethernet network ac-
cess interface ports. MII interface
is used to connect external PHY
devices for 100 Mbps Ethernet.
They also can direct connect with
standard 10Mbps serial interface.

The EA-224 provides the Ethernet
MAC protocols, handles the local
buffer memory interface and
management, arbitrates among
multiple priority queues, and in-
terfaces with the

XpressFlow

En-

gine and other Access Controllers
through the

XpressFlow

message

passing protocol.

2.1 Related Components:

SC-201

XpressFlow Engine

EA-208E

8-port 10Mbps

Ethernet Access Controller

EA-208

6-port 10 + 2-port

10/100 Ethernet Access Con-
troller

EA-222

2-port 10/100 Fast

Ethernet Access Controller

2.2 Typical Application:

A 16-port Ethernet Switch with
4 Fast Ethernet Up-Links

Local

Buffer

Memory

Management BUS

SWITCH BUS

Switch Bus

Interafce

MAC Port #0 to #3

Port 0

4-Port 100Base-Tx PHY

Managem

Bus Interafce

Local

Buffer

Memory

Interface

Automatic

Buffer

Manager

MAC Interface

Port 0

EA-224

Block Diagram 

EA-224 4-Port Ethernet Access Controller

Address

Mapping

Table

Flash

ROM

SC201

XpressFlow

Engine

EA208E

8-Port

Ethernet

Access

Controller

Management Bus

Buffer

RAM

Switch

Manager

CPU

DRAM

RS232 Local

Control Console

Buffer

RAM

8 Ethernet ports

Buffer

RAM

8 Ethernet ports

XpressFlow Bus

EA208E

8-Port

Ethernet

Access

Controller

Buffer

RAM

Four 100M

Fast Ethernet ports

EA224

4-Port

Ethernet

Access

Controller

System Block Diagram --

16-Port Ethernet Switch with 4 Fast Ethernet Up-Links

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

Rev. 4.0 December, 1997

3. PIN ASSIGNMENT

3.1 Logic Symbol

EA-224

T _ M O D E

M _ M D C
M _ M D I O

XpressFlow

Bus Interface

Management Bus

Interface

Test Pin

P_D[15:0]

P _ C S #

P _ A D S #

P _ R W C

P _ B S 1 6 #

P _ R D Y #

P _ I N T

P _ R S T #

P _ C L K

P_A[11:1]

Control Buffer

Memory Interface

MII Serial

M a n a g e m ' t

M m _ R X D [ 3 : 0 ]
M m _ R X D V
M m _ R X C
M m _ R X E R

M m _ T X E R
M m _ T X C
M m _ T X E N
M m _ T X D [ 0 ]
M m _ T X D [ 1 ]
M m _ T X D [ 2 ]
M m _ T X D [ 3 ]

Port [3:0]

10/100 MII Interface

M m _ C O L
M m _ C R S
M m _ L N K

T m _ R X D

T m _ R X C

T m _ T X C
T m _ T X E N
T m _ T X D

T m _ L P B K
T m _ F D

T m _ C O L
T m _ C R S
T m _ L N K

M I I M o d e

1 0 B a s e T
Serial Xface

S_D[31:0]

S _ M S G E N #

S _ E O F #

S _ I R D Y

S _ T A B T #

S _ O V L D #

S _ H P R E Q #

S _ R E Q #

S _ G N T #

S _ C L K

L_D[31:0]

L_OE[3:0]#

L _ A D S C #

L _ C L K

L_A[18:2]

L _ W E [ 3 : 0 ] #

L _ B W E [ 3 : 0 ] #

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

3.2 Pin Assignment (Preliminary)

Note:

Active low signal

Input

Input signal

I-ST

Input signal with Schmitt-Trigger

Output

Output signal (Tri-State driver)

Out-OD

Output signal with Open-Drain driver

I/O-TS

Input & Output signal with Tri-State driver

I/O-OD

Input & Output signal with Open-Drain driver

5VT

Input with 5V Tolerance

Output signal with programmable polarity.

Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)

These pins are reserved for internal use only. They should be left unconnected.

Pin No(s).

Symbol

Type

Max

/ I

Name & Functions

Management Bus Interface

J25,K26,L24,K25,L26,
M24,L25,M26,N24,M25,
P24,N26,N25,R24,P26,
P25

P_D[15:0]

TTL I/O-TS
(5VT)

16mA

Management Bus Data Bit [15:0]

C26,D24,C25,E24,D26,
D25,F24,E26,E25,G24,
F26

P_A[11:1]

TTL In (5VT)

Management Bus Address Bit [11:1]

F25

P_ADS#

TTL In (5VT)

Management Bus Address Strobe

H25

P_RWC

TTL In (5VT)

Management Bus Read/Write Control

J24

P_RDY#

TTL Out-OD

16mA

Management Bus Data Ready

G25

P_BS16#

TTL Out-OD

16mA

Management Bus 16 bit Data Bus

G26

P_CS#

TTL In (5VT)

Management Bus Chip Select

H26

P_INT

CMOS Output

4mA

Management Bus Interrupt Request

J26

P_RST#

TTL In-ST
(5VT)

Management Bus Master Reset

K24

P_CLK

TTL In (5VT)

Management Bus Bus Clock

XpressFlow Bus Interface
C23,A23,B22,C22,A22

S_D[31:27] /
P_C[0:4]

CMOS I/O-TS

12 mA

XpressFlow Bus Data Bit [31:27] or
Management Bus Interface Configuration
bit [0:4]

B21,D20,C21,A21,B20,
A20,C20,B19,A19,C19,
B18,A18,B17,C18,A17,
D17,B16,C17,A16,B15,
A15,C16,B14,D15,A14,
C15,B13

S_D[26:0]

CMOS I/O-TS

12mA

XpressFlow Bus Data Bit [26:0]

B12

S_MSGEN#

CMOS I/O-TS

12 mA

XpressFlow Bus Message Envelope

A12

S_EOF#

CMOS I/O-TS

12mA

XpressFlow Bus End of Frame

C14

S_IRDY

CMOS I/O-TS

12 mA

XpressFlow Bus Initiator Ready

C13

S_TABT#

CMOS I/O-OD

12 mA

XpressFlow Bus Target Abort

B23

S_HPREQ#

CMOS I/O-OD

12mA

XpressFlow Bus High Priority Request

A24

S_REQ#

CMOS Output

4mA

XpressFlow Bus Bus Request to
SC201

B24

S_GNT#

CMOS Input

XpressFlow Bus Bus Grant from SC201

A13

S_OVLD#

CMOS Input

XpressFlow Bus Bus Overload

D13

S_CLK

CMOS Input

XpressFlow Bus Clock

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

Pin No(s).

Symbol

Type

Max

/ I

Name & Functions

Control Buffer Memory Interface

M4,N2,L3,M1,M2,L1,K3,
L2,K4,K1,J3,K2,J1,J2,
H3,H1,H2,G3,G1,G2,F1,
F3,F2,E1,E3,E2,D1,D3,
D2,C1,C2,B1

L_D[31:0]

TTL I/O-TS

8mA

Local Memory Bus Data Bit [31:0]

A6,B6,C8,A7,D8,D7,C9,
A8,B8,A9,C10,B9,D10,
A10,C11,B10,A11

L_A[18:2]

CMOS Output

8mA

Local Memory Bus Address Bit [17:2]

L_A[19] /
L_OE[3]#

CMOS Output

8mA

Local Memory Bus Address Bit [19] or
Memory Read Chip Select [3]

D5,A5,A3

L_OE[2:0]#

CMOS Output

2mA

Local Memory Read Chip Select [2:0]

D7,E4,B5,C4

L_WE[3:0]#

CMOS Output

2mA

Local Memory Write Chip Select [3:0]

C6,B4,A4,C5

L_BWE[3:0]#

CMOS Output

8mA

Local Memory Byte Write Enable, Byte
[3:0]

L_ADSC#

CMOS Output

8mA

Local Memory Controller Address Status

L_CLK

CMOS Output

8mA

Local Memory Clock input

Fast Ethernet Access Port [3:0]

T24

M_MDC

CMOS Output

4mA

MII Management Data Clock (common
for all MII Ports Port [1:0])

R26

M_MDIO

TTL IO-TS
(5VT)

4mA

MII Management Data I/O (common for
all MII Ports Port [1:0]))

AB2,U25,AE26,AF5

M[3:0]_RXD[3] TTL In (5VT)

Port [3:0] MII Receive Data Bit [3]

AB1,V24,AD25,AE6

M[3:0]_RXD[2] TTL In (5VT)

Port [3:0] -- Receive Data Bit [2]

AA3,U26,AD26,AD6

M[3:0]_RXD[1] TTL In (5VT)

Port [3:0] -- Receive Data Bit [1]

AC2,T25

M[3:2]_RXD[0] TTL In (5VT)

Port [3:0] -- Receive Data Bit [0]

AC25,AF6

M[1:0]_RXD[0] TTL In (5VT)

Y3,V26,AF24,AD5

M[3:0]_RXDV TTL In (5VT)

Port [3:0] -- Receive Data Valid

AC1,U24

M[3:2]_RXC

TTL In (5VT)

Port [3:0] -- Receive Clock

AC24,AE7

M[1:0]_RXC

TTL In (5VT)

AA1,V25,AD23,AE5

M[3:0]_RXER

Port [3:0] -- Receive Error

AA2,W24,AE24,AF4

M[3:0]_TXER

CMOS Output

4mA

Port [3:0] -- Transmit Error

W2,AA25,AE22,AD1

M[3:0]_TXC

TTL In (5VT)

Port [3:0] -- Transmit Clock

W1,AA24,AF22,AF2

M[3:0]_TXEN

CMOS Output

4mA

Port [3:0] -- Transmit Enable

V3,AA26,AD21,AE3

M[3:0]_TXD[3] CMOS Output

4mA

Port [3:0] -- Transmit Data Bit [3]

Y2,Y26,AE23,AF3

M[3:0]_TXD[2] CMOS Output

4mA

Port [3:0] -- Transmit Data Bit [2]

W3,W26,AD22,AD4

M[3:0]_TXD[1] CMOS Output

4mA

Port [3:0] -- Transmit Data Bit [1]

Y1,W25,AF23,AE4

M[3:0]_TXD[0] CMOS Output

4mA

Port [3:0] -- Transmit Data Bit [0]

V1,AB26

M[3:2]_COL

TTL In (5VT)

Port [3:0] -- Collision Detected

AD20,AC3

M[1:0]_COL

TTL In (5VT)

U3,AB24

M[3:2]_CRS

TTL In (5VT)

Port [3:0] -- Carrier Sense

AF21,AD2

M[1:0]_CRS

TTL In (5VT)

V2,AB25

M[3:2]_LNK

TTL In (5VT)

Port [3:0] -- Link Status

AE21,AB3

M[1:0]_LNK

TTL In (5VT)

Test Facility

A25

T_MODE

CMOS I/O-TS

2mA

Test Pin Set Test Mode upon Reset,
and provides test status output during
test mode

N1,M3,P2,P1,N3,R2,P3,
R1,T2,R3,T1,R4,U2,T3,
U1,U4

T_D[15:10]

CMOS Output

4mA

Test Pins Reserved for internal use
only

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

3.3 Pin Reference Table: (352 pin BGA)

Pin # Signal Name

Pin #

Signal Name

Pin #

Signal Name

Pin #

Signal Name

Pin #

Signal Name

F26

P_A[1]

D17

S_D[11]

L_D[3]

AF23 M1_TXD[0] / T1_TXD

T_D[8]

G24

P_A[2]

A17

S_D[12]

L_D[4]

AF22 M1_TXEN / T1_TXEN

T_D[9]

E25

P_A[3]

C18

S_D[13]

L_D[5]

AE22 M1_TXC / T1_TXC

T_D[10]

E26

P_A[4]

B17

S_D[14]

L_D[6]

AE24 M1_TXER

T_D[11]

F24

P_A[5]

A18

S_D[15]

L_D[7]

AD23 M1_RXER

T_D[12]

D25

P_A[6]

B18

S_D[16]

L_D[8]

AC24 M1_RXC / T1_RXC

T_D[13]

D26

P_A[7]

C19

S_D[17]

L_D[9]

AF24 M1_RXDV

T_D[14]

E24

P_A[8]

A19

S_D[18]

L_D[10]

AC25 M1_RXD[0] / T1_RXD

T_D[15]

C25

P_A[9]

B19

S_D[19]

L_D[11]

AD26 M1_RXD[1]

D24

P_A[10]

C20

S_D[20]

L_D[12]

AD25 M1_RXD[2]

VDD

C26

P_A[11]

A20

S_D[21]

L_D[13]

AE26 M1_RXD[3]

D11

VDD

F25

P_ADS#

B20

S_D[22]

L_D[14]

AB25 M2_LNK / T2_LNK

D16

VDD

G26

P_CS#

A21

S_D[23]

L_D[15]

AB24 M2_CRS / T2_CRS

D21

VDD

H25

P_RWC

C21

S_D[24]

L_D[16]

AB26 M2_COL / T2_COL

VDD

G25

P_BS16#

D20

S_D[25]

L_D[17]

AA26 M2_TXD[3] / T2_FD

F23

VDD

J24

P_RDY#

B21

S_D[26]

L_D[18]

Y26

M2_TXD[2] / T2_LPBK

VDD

J26

P_RST#

A22

S_D[27] / P_C[4]

L_D[19]

W26

M2_TXD[1]

L23

VDD

H26

P_INT

C22

S_D[28] / P_C[3]

L_D[20]

W25

M2_TXD[0] / T2_TXD

VDD

K24

P_CLK

B22

S_D[29] / P_C[2]

L_D[21]

AA24 M2_TXEN / T2_TXEN

T23

VDD

P25

P_D[0]

A23

S_D[30] / P_C[1]

L_D[22]

AA25 M2_TXC / T2_TXC

AA4

VDD

P26

P_D[1]

C23

S_D[31] / P_C[0]

L_D[23]

W24

M2_TXER

AA23

VDD

R24

P_D[2]

L_D[24]

V25

M2_RXER

AC6

VDD

N25

P_D[3]

A11

L_A[2]

L_D[25]

U24

M2_RXC / T2_RXC

AC11

VDD

N26

P_D[4]

B10

L_A[3]

L_D[26]

V26

M2_RXDV

AC16

VDD

P24

P_D[5]

C11

L_A[4]

L_D[27]

T25

M2_RXD[0] / T2_RXD

AC21

VDD

M25

P_D[6]

A10

L_A[5]

L_D[28]

U26

M2_RXD[1]

GND

N24

P_D[7]

D10

L_A[6]

L_D[29]

V24

M2_RXD[2]

GND

M26

P_D[8]

L_A[7]

L_D[30]

U25

M2_RXD[3]

A26

GND

L25

P_D[9]

C10

L_A[8]

L_D[31]

M3_LNK / T3_LNK

GND

M24

P_D[10]

L_A[9]

M3_CRS / T3_CRS

B25

GND

L26

P_D[11]

L_A[10]

T24

M_MDC

M3_COL / T3_COL

B26

GND

K25

P_D[12]

L_A[11]

R26

M_MDIO

M3_TXD[3] / T3_FD

GND

L24

P_D[13]

L_A[12]

M3_TXD[2] / T3_LPBK

C24

GND

K26

P_D[14]

L_A[13]

AB3

M0_LNK / T0_LNK

M3_TXD[1]

GND

J25

P_D[15]

L_A[14]

AD2

M0_CRS / T0_CRS

M3_TXD[0] / T3_TXD

GND

L_A[15]

AC3

M0_COL / T0_COL

M3_TXEN / T3_TXEN

D14

GND

D13

S_CLK

L_A[16]

AE3

M0_TXD[3] / T0_FD

M3_TXC / T3_TXC

D19

GND

A13

S_OVLD#

L_A[17]

AF3

M0_TXD[2] / T0_LPBK

AA2

M3_TXER

D23

GND

B23

S_HPREQ#

L_A[18]

AD4

M0_TXD[1]

AA1

M3_RXER

GND

A24

S_REQ#

L_A[19] / OE[3]#

AE4

M0_TXD[0] / T0_TXD

AC1

M3_RXC / T3_RXC

J23

GND

B24

S_GNT#

L_OE[2]#

AF2

M0_TXEN / T0_TXEN

M3_RXDV

GND

B12

S_MSGEN#

L_OE[1]#

AD1

M0_TXC / T0_TXC

AC2

M3_RXD[0] / T3_RXD

P23

GND

A12

S_EOF#

L_OE[0]

AF4

M0_TXER

AA3

M3_RXD[1]

GND

C14

S_IRDY

L_WE[3]#

AE5

M0_RXER

AB1

M3_RXD[2]

W23

GND

C13

S_TABT#

L_WE[2]#

AE7

M0_RXC / T0_RXC

AB2

M3_RXD[3]

AC4

GND

B13

S_D[0]

L_WE[1]#

AD5

M0_RXDV

AC8

GND

C15

S_D[1]

L_WE[0]#

AF6

M0_RXD[0] / T0_RXD

A25

T_MODE

AC13

GND

A14

S_D[2]

L_BWE[3]#

AD6

M0_RXD[1]

AC18

GND

D15

S_D[3]

L_BWE[2]#

AE6

M0_RXD[2]

T_D[0]

AC23

GND

B14

S_D[4]

L_BWE[1]#

AF5

M0_RXD[3]

T_D[1]

AD3

GND

C16

S_D[5]

L_BWE[0]#

AE21 M1_LNK / T1_LNK

T_D[2]

AD24

GND

A15

S_D[6]

L_ADSC#

AF21 M1_CRS / T1_CRS

T_D[3]

AE1

GND

B15

S_D[7]

L_CLK

AD20 M1_COL / T1_COL

T_D[4]

AE2

GND

A16

S_D[8]

L_D[0]

AD21 M1_TXD[3] / T1_FD

T_D[5]

AE25

GND

C17

S_D[9]

L_D[1]

AE23 M1_TXD[2] / T1_LPBK

T_D[6]

AF1

GND

B16

S_D[10]

L_D[2]

AD22 M1_TXD[1]

T_D[7]

AF25

GND

Note:

Output signals with programmable polarity.

Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)

These pins are reserved for internal use only. They should be left unconnected.

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

4. FUNCTIONAL DESCRIPTION

4.1 Local Memory (Local Buffer Memory) Interface

Use industry standard Synchronous Burst Mode SRAM up to 1M bytes

32k x 32, 64k x 32, 128k x 32, or 256k x 32

Provides 4 individual

Byte Write Enable

controls ( L_BWE[3:0]# )

Provides separate Read and Write Chip Selects ( L_OE[3:0]# and L_WE[3:0]# ) for each memory chip

Supports back to back Read or Write operations across memory chips

4.1.1 Pin Description

Symbol

Type

Name & Functions

L_D[31:0]

TTL

I/O-TS

Local Memory Data Bus Bit [31:0]

a 32-bit synchronous data bus.

L_A[18:2]

CMOS
Output

Local Memory Address Bus Bit [18:2]

Bit [18:2] of a synchronous

address bus. The memory address is sampled when L_CS# is enabled
and L_ADSC# is asserted.

L_A[19] /
L_OE[3]#

CMOS
Output

Local Memory Address Bus Bit [19] or Local Memory Read Chip
Select [3]

Depends on memory configuration, this pin can be used as

the Local Memory Address Bit [19] or as the Local Memory Read Chip
Select [3].

L_OE[2:0]#

CMOS
Output

Local Memory Read Chip Select [2:0]

allows up to read one of the 4

banks of memory.

L_WE[3:0]#

CMOS
Output

Local Memory Write Chip Select [3:0]

allows up to write one of the 4

banks of memory.

L_BWE[3:0]#

CMOS
Output

Local Memory Byte Write Enable [3:0]

use to write individual bytes.

L_ADSC#

CMOS
Output

Local Memory Controller Address Status

to load a new address.

L_CLK

CMOS
Output

Local Memory Clock

a synchronous clock to memory devices.

Note:

These pins have weak internal pull up resistors (50k to 100k Ohms each).

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

4.1.2 Supported Memory Configurations

Read/Write Chip Select and High Address Bits

Chip #3

Chip #2

Chip #1

Chip #0

RAM Chip

Size

# of RAM

Chips

Total Buffer

Memory Size

L_WE[3]#

L_A[19] /

L_OE[3]#

L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#

32k x 32

128k bytes

----

L_WE[0]#

L_OE[0]#

256k bytes

----

L_WE[1]#

L_OE[1]#

L_WE[0]#

L_OE[0]#

512k bytes

L_WE[3]#

L_OE[3]#

L_WE[2]#

L_OE[2]#

L_WE[1]#

L_OE[1]#

L_WE[0]#

L_OE[0]#

64k x 32

256k bytes

----

L_WE[0]#

L_OE[0]#

512k bytes

----

L_WE[1]#

L_OE[1]#

L_WE[0]#

L_OE[0]#

1M bytes

L_WE[3]#

L_OE[3]#

L_WE[2]#

L_OE[2]#

L_WE[1]#

L_OE[1]#

L_WE[0]#

L_OE[0]#

128k x32

512k bytes

----

L_WE[0]#

L_OE[0]#

1M bytes

----

L_WE[1]#

L_OE[1]#

L_WE[0]#

L_OE[0]#

256k x32

1M bytes

----

L_A[19]

----

L_WE[0]#

L_OE[0]#

4.1.3 Bus Cycle Waveforms

A3+1

A3+2

A3+3

A4+1

A4+2

A4+3

D3+1

D3+2

D3+3

D4+1

D4+2

D4+3

L_CLK

L_ADSC#

L_CS#

L_A[19:2]

L_WE[3:0]#

L_BWE[3:0]#

L_OE[3:0]#

L_D[31:0] (Wr)

L_D[31:0] (Rd)

Typical Local Memory Access Operations

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

Rev. 4.0 December, 1997

4.2 Management Bus Interface

Supports various industry standard micro-
processors including:

Intel 186, 386, and 486 family or equivalent

Motorola MPC series embedded processors

Easily adapts to other industry standard CPUs

Provides separate Address and Data bus

Supports Big & Little Endian byte ordering

Supports 16-bit Data Bus

Supports early RDY cycle

Meets timing requirement for Intel/AMD
186 family processors

Supports 1X or 2X CPU Clock

2X CPU Clock for 386 family processors

Provides a single interrupt signal to Switch
Manager CPU

4.2.1 Pin Description

Symbol

Type

Name & Functions

P_C[4:0]

CMOS Input

Processor Configuration bit [4:0]

: During the Reset Cycle, the

P_C[4:0] pins provides the processor configuration. By using external
weak pull-up or -down resistors, they define the External Management
Bus Interface Configuration. These inputs are sampled at the trailing
edge of the Reset cycle.

C[0] Defines the CPU Clock input is 1X or 2X clock
C[1] Selects either Big or Little Endian byte ordering
C[2] Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] Defines the CPU Bus width For EA-208, it is default to 16-bit CPU

Bus interface, and the setting of this bit is ignored.

C[4] Defines the timing relationship between P_RDY and P_D[15:0] valid.

If C[4] is High, the P_D[15:0] are valid along in the same clock period
as P_RDY is asserted. If C[4] is Low, the P_RDY is asserted one
clock period early ahead of the P_D[15:0] are valid.

C[0]

C[1]

C[2]

C[3]

C[4]

CPU Clock

Byte Order

RWC

Bus Size

RDY Timing

1X Clock

Little Endian

P_R/W#

n/a

Normal

2x Clock

Big Endian

P_W/R#

n/a

Early

After RESET, these pins are used as

XpressFlow

Bus Data bit [31:27].

P_A[11:1] TTL In (5VT)

Address Bus Bit [11:1]

I/O port address

P_D[15:0] TTL I/O-TS

(5VT)

Data Bus Bit [15:0]

a 16-bit synchronous data bus.

P_ADS#

TTL In (5VT)

Address Strobe

indicates valid address is on the bus

P_RWC

TTL Input
(5VT)

Read/Write Control

indicates the current bus cycle is a read or write

cycle. C[1] defines the polarity of this signal during the Reset cycle.

C[1]=0

P_R/W# is used for PowerPC or other similar processors.

C[1]=1

P_W/R# is used for 386, 486 or other similar processors

P_RDY#

TTL Out-OD

Data Ready

timing indicates for bus data valid

P_BS16# TTL Out-OD

Bus Size 16

response to bus master that the EA208 only supports 16-

bit data bus width.

P_CS#

TTL Input
(5VT)

Chip Select

indicates the

XpressFlow

Engine is the target for the cur-

rent bus operation.

P_INT

CMOS Out-
put

Interrupt Request

to Switch Manager CPU

The polarity of this signal

output is programmable via chip configuration register

P_RST#

TTL In-ST
(5VT)

CPU Reset

Synchronous reset Input from Switch Manager CPU

P_CLK

TTL In (5VT)

CPU Clock

2X Clock for 386 family, and 1X Clock for the others

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

4.2.5 Register Map

Note:

All 32-bit registers are D-word aligned.

All 16-bit registers are also D-word aligned and right justified.

For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.

For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.

This is a Global Register. CPU is allowed to write the Global Register of all devices by a sin-

gle operation.

These registers are reserved for system diagnostic usage only.

I/O Offset

Register

Description

Little

Endian

Big

Endian

Reg.

Size

W/R

Note:

Device Configuration Registers (DCR)

GCR

Global Control Register

hF00

hF02

16-bit

W/--

DCR0

Device Status Register

hF00

hF02

16-bit

--/R

DCR1

Signature & Revision Register

hF10

hF12

16-bit

--/R

DCR2

ID Register

hF20

hF22

16-bit

W/R

DCR3

Device Configuration Register

hF30

hF32

16-bit

W/R

DCR4

Interfaces Status Register

hF40

hF42

16-bit

--/R

DTSR

Test Register

hF70

hF72

16-bit

W/R

Interrupt Controls

ISR

Interrupt Status Register Unmasked

hF80

hF82

16-bit

--/R

ISRM

Interrupt Status Register Masked

hF90

hF92

16-bit

--/R

IMSK

Interrupt Mask Register

hFA0

hFA2

16-bit

W/R

IAR

Interrupt Acknowledgment Register

hFB0

hFB2

16-bit

W/--

Buffer Memory Interface

MWAR

Memory Write Address Reg. Single Cycle

hE08

32-bit

W/R

MRAR

Memory Read Address Reg. Single Cycle

hE18

32-bit

W/R

MBAR

Memory Address Register Burst Mode

hE28

32-bit

W/R

MWBS

Memory Write Burst Size (in D-words)

hE40

hE42

16-bit

W/R

MRBS

Memory Read Burst Size (in D-words)

hE50

hE52

16-bit

W/R

MWDR

Memory Write Data Register

hE68

32-bit

W/--

MWDX

Memory Write Data Reg. Byte Swapping

hE6C

32-bit

W/--

MRDR

Memory Read Data Register

hE68

32-bit

--/R

MRDX

Memory Read Data Reg. Byte Swapping

hE6C

32-bit

--/R

FCB Buffer & Stack Management

FCBBA

Frame Control Buffer Base Address

hD00

hD02

16-bit

W/R

FCBAG

Frame Control Buffer Buffer Aging Status

hD30

hD32

16-bit

--/R

FCBSL

Frame Ctrl Buffer Stack Size Limit

hD90

hD92

16-bit

W/R

FCBST

Frame Ctrl Buffer Stack Buffer Low Threshold

hDA0

hDA2

16-bit

W/R

FCBSS

Frame Ctrl Buffer Stack Allocation Status

hDB0

hDB2

16-bit

--/R

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

I/O Offset

Register

Description

Little

Endian

Big

Endian

Reg.

Size

W/R

Note:

Access Control Function (Chip Level controls)

AVXR

VLAN Control Table (VCT) Index Register

hC00

hC02

16-bit

W/--

AVDR

VCT Data Register

hC10

hC12

16-bit

W/R

AVTC

VLAN Type Code

hC20

hC22

16-bit

W/R

AXSC

Transmission Scheduling Control Register

hC30

hC32

16-bit

W/R

AMIIC

MII Command Register

hC40

32-bit

W/--

AMIIS

MII Status Register

hC40

32-bit

--/R

AFCR

Flow Control Register

hC70

hC72

16-bit

W/R

AMAR0

Multicast Address. for MAC Control Frames

Byte [1,0]

hC80

hC82

16-bit

W/R

AMAR1

Byte [3,2]

hC90

hC92

16-bit

W/R

AMAR2

Byte [5,4]

hCA0

hCA2

16-bit

W/R

AMCT

MAC Control FrameType Code Register

hCB0

hCB2

16-bit

W/R

ADAR0

Base MAC Address Register Byte [1,0]

hCC0

hCC2

16-bit

W/R

ADAR1

Base MAC Address Register Byte [3,2]

hCD0

hCD2

16-bit

W/R

ADAR2

Base MAC Address Register Byte [5,4]

hCE0

hCE2

16-bit

W/R

Ethernet MAC Port Control Registers (substitute [n] with Port Number, n = {0..3] )

ECR0

MAC Port Control Register

16-bit

W/R

ECR1

MAC Port Configuration Register

16-bit

W/R

ECR2

MAC Port Interrupt Mask Register

hn20

hn22

16-bit

W/R

ECR3

MAC Port Interrupt Status Register

hn30

hn32

16-bit

--/R

EXSR

MAC Tx Status Register

hn40

hn42

16-bit

--/R

EXEC

MAC Tx Error Counters

hn50

hn52

16-bit

--/R

ERSR

MAC Rx Status Register

hn68

32-bit

--/R

EREC

MAC Rx Error Counters

hn78

32-bit

--/R

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

4.3 XpressFlow Bus Operation

Zarlink's optimized

XpressFlow

Bus architec-

ture

Provides up to 1.6G bps switching bandwidth

-33

1.07G bps

-40

1.28G bps

-50

1.60G bps

Full multi bus master structure

Allows Access Controllers to communicate
with

XpressFlow

Engine and other Access

Controllers via a message passing protocol

Two level bus request priorities

High priority for Data Messages

for forwarding an Ethernet frame from
receiving port to transmission port

Low priority for Command Messages

for passing control information between
devices

4.3.1 Pin Description

Symbol

Type

Name & Functions

S_D[31:0]

CMOS
I/O-TS

Data Bus Bit [31:0]

a 32-bit synchronous data bus.

Note:

During the system RESET period, Data Bit [31:27] are used
as Processor Interface Configuration bit [0:3]

S_MSGEN#

CMOS
I/O-TS

Message Envelope

encompasses the entire period of a message

transfer. Targets use the leading edge of this signal to detect the be-
ginning of a message transfer, and to decode the message header for
the intended target(s).

S_EOF#

CMOS
I/O-TS

End of Frame

only used by frame data transfer messages to identify

the end of frame condition. This signal is synchronous with the Rx
Frame Status word appended to the end of the message.

S_IRDY

CMOS
I/O-TS

Initiator Ready

a normal true signal. When negated, it indicates the

initiator had asserted wait state(s) in between command words. Target
should use this signal as enable signal for latching the data from the
bus.

S_TABT#

CMOS

I/O-OD

Target Abort

when asserted, the target had aborted the reception of

current message on the bus.

S_HPREQ#

CMOS

I/O-OD

High Priority Request

indicates one or more Bus Requester is re-

questing for high priority message transfer.

S_REQ#

CMOS
Output

Bus Request

Bus Request signal from Access Controller to Bus Ac-

cess Arbitrator in

XpressFlow

Engine

S_GNT#

CMOS

Input

Bus Grant

Bus Grant signal from Bus Arbitrator to Bus Requester

S_OVLD#

CMOS

Input

Bus Over-load

when asserted, all data forwarding bus bandwidth has

been allocated. Cannot support additional load for data forwarding traf-
fic.

S_CLK

CMOS

Input

XpressFlow Bus Clock

up to 50MHz system clock

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

4.4 MII Interface

Fully compliant with IEEE 802.3u Media Inde-
pendent Interface for connecting with external
10/100M Ethernet Physical Layer Transceiver

Supports both 10Mbps 10BaseT interface and
100Mbps 100BaseTx interface

Supports both half and full duplex operation

Shared Station Management interface (one for
all MII channels with in the Access Controller)

All ports can also support 10Mbps Serial In-
terface

If 10Mbps Serial Interface is used, the MII
port pin assignment are re-mapped for
10Mbps Serial Interface.

4.4.1 Pin Description

Symbol

Type

Name & Functions

M_MDC

CMOS
Output

MII Management Data Clock

(common for all MII Ports) used to syn-

chronize the MII data stream (MDIO) for transferring between the Ac-
cess Controller and the MII Tranceivers.

M_MDIO

TTL

IO-TS

(5VT)

MII Management Data I/O

(common for all MII Ports) a serial man-

agement data stream synchronous with MDC.

Mm_RXD[3:0] TTL In

(5VT)

Receive Data [3:0]

(one set for each MII Port) a four-bit transmit data

nibble. Bit 0 is the least significant bit, and bit 3 is the most significant
bit.

Mm_RXDV

TTL In

(5VT)

Receive Data Valid

(one for each MII Port) instructs the MAC to be-

gin moving data nibbles from the receive data lines.

Mm_RXC

TTL In

(5VT)

Receive Clock

(one for each MII Port) a 25MHz clock input with 35%

to 65% duty cycles.

Mm_RXER

TTL In

(5VT)

Receive Error

(one for each MII Port)

Mm_TXER

CMOS
Output

Transmit Error

(one for each MII Port)

Mm_TXC

TTL In

(5VT)

Transmit Clock

(one for each MII Port) a continuous clock input with

35% to 65% duty cycles.

Mm_TXEN

CMOS
Output

Transmit Enable

(one for each MII Port) instructs the transceiver to

begin moving data nibbles on the transmit data lines.

Mm_TXD[3:0] CMOS

Output

Transmit Data [3:0]

(one set for each MII Port) a four-bit transmit

data nibble. Bit 0 is the least significant bit, and bit 3 is the most signifi-
cant bit.

Mm_COL

TTL In

(5VT)

Collision Detected

(one for each MII Port)

Mm_CRS

TTL In

(5VT)

Carrier Sense

(one for each MII Port)

Mm_LNK

TTL In

(5VT)

Link Status 

(one for each MII Port)

The polarity of this signal is programmable via Port Configuration Reg-
ister

Note:

"m" is the port number [3:0].

These signals have programmable output polarity.

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

4.4.2 PIN Mapping between MII Interface and 10Mbps Serial Interface

MII Interface

10Mbps Serial Interface

Symbol

Type

Symbol

Type

Name & Functions

Mm_RXD[3:1] TTL In

(5VT)

Not used by Serial Interface Ports.

Has a weak

internal pull-up resistor.

Mm_RXD[0]

TTL In

(5VT)

Tm_RXD

TTL In

(5VT)

Receive Data

(one for each Serial Interface

Port) a receive data stream.

Mm_RXDV

TTL In

(5VT)

Not used by Serial Interface Ports.

Has a weak

internal pull-up resistor.

Mm_RXC

TTL In

(5VT)

Tm_RXC

TTL In

(5VT)

Receive Clock

(one for each Serial Interface

Port)

Mm_RXER

TTL In

(5VT)

Not used by Serial Interface Ports.

Has a weak

internal pull-up resistor.

Mm_TXER

CMOS
Output

Not used by Serial Interface Ports.

Mm_TXC

TTL In

(5VT)

Tm_TXC

TTL In

(5VT)

Transmit Clock

(one for each Serial Inter-

face Port) a continuous clock input with 35% to
65% duty cycles.

Mm_TXEN

CMOS
Output

Tm_TXEN

CMOS
Output

Transmit Enable

(one for each Serial Inter-

face Port)

Mm_TXD[0]

CMOS
Output

Tm_TXD

CMOS
Output

Transmit Data

(one for each Serial Interface

Port) a transmit data stream.

Mm_TXD[1]

CMOS
Output

Not used by Serial Interface Ports

Mm_TXD[2]

CMOS
Output

Tm_LPBK

CMOS
Output

Loop Back Enable

(one for each Serial In-

terface Port)

The polarity of this signal is pro-

grammable via Port Configuration Register

Mm_TXD[3]

CMOS
Output

Tm_FD

CMOS
Output

Full Duplex Mode

(one for each Serial In-

terface Port)

The polarity of this signal is pro-

grammable via Port Configuration Register

Mm_COL

TTL In

(5VT)

Tm_COL

TTL In

(5VT)

Collision Detected

(one for each Serial In-

terface Port)

Mm_CRS

TTL In

(5VT)

Tm_CRS

TTL In

(5VT)

Carrier Sense

(one for each Serial Interface

Port)

Mm_LNK

TTL In

(5VT)

Tm_LNK

TTL In

(5VT)

Link Status 

(one for each Port)

The polarity

of this signal is programmable via Port Configu-
ration Register

Note:

"m" is the port number [3:0].

These signals have programmable output polarity.

4.5 Test Facility

Symbol

Type

Name & Functions

T_MODE

CMOS

I/O TS

Test Mode Selection & Test Output

Set Test Mode upon Reset, and

provides test status output during test mode

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

5. DC SPECIFICATION

5.1 ABSOLUTE MAXIMUM RATINGS

Storage Temperature

-65

°C to +150°C

Operating Temperature

°C to +70°C

Supply Voltage V

with Respect to V

+3.0 V to +3.6 V

Voltage on 5V Tolerant Input Pins

-0.5 V to (V

+ 2.5 V)

Voltage on Other Pins

-0.5 V to (V

+ 0.5 V)

Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not
implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.

5.2 DC CHARACTERISTICS

= +3.0 V to +3.6 V

AMBIENT

= 0

°C to +70°C

Preliminary

Symbol

Parameter Description

Min

Typ

Max

Unit

osc

Frequency of Operation ( -33)

33.3333

MHz

Frequency of Operation ( -40)

40.0000

MHz

Frequency of Operation (-50)

50.0000

MHz

Supply Power @ 33.3333 MHz (V

=3.3 V)

TBD

Supply Power @ 40 MHz (V

=3.3 V)

TBD

Supply Power @ 50 MHz (V

=3.3 V)

TBD

OH-CMOS

Output High Voltage (CMOS) I

= maximum

- 0.5

OL-CMOS

Output Low Voltage (CMOS) I

= maximum

0.45

OH-TTL

Output High Voltage (TTL) I

= maximum

2.4

OL-TTL

Output Low Voltage (TTL) I

= maximum

0.45

IH-CMOS

Input High Voltage (CMOS)

VDD

70%

+ 10%

IL-CMOS

Input Low Voltage (CMOS)

-0.5

VDD

30%

IH-TTL

Input High Voltage (TTL)

2.0

+ 10%

IL-TTL

Input Low Voltage (TTL)

-0.3

+0.8

IH-5VT

Input High Voltage (TTL 5V tolerant)

2.0

+ 1.8

IL-5VT

Input Low Voltage (TTL 5V tolerant)

-0.3

+0.8

Input Leakage Current (0.1 V V

)

(all pins except those with internal pull-
up/pull-down resistors)

±10

µA

Output Leakage Current (0.1 V V

OUT

)

±15

µA

Input Leakage Current V

= V

- 0.1 V

(pins with internal pull-down resistors)

µA

Input Leakage Current V

= 0.1 V

(pins with internal pull-up resistors)

-60

µA

Input Capacitance

OUT

Output Capacitance

I/O

I/O Capacitance

Notes:

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

-33

-40

-50

Symbol

Parameter

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Note:

S_D[31:0] output valid delay

= 50pf

S_MSGEN# output valid delay

= 50pf

S_EOF# output valid delay

= 50pf

S_IRDY output valid delay

= 50pf

S_TABT# output valid delay

= 50pf

S_HPREQ# output valid delay

= 50pf

S_REQ# output valid delay

= 20pf

S12

S_D[31:0] output float delay

S13

S_MSGEN# output float delay

S14

S_EOF# output float delay

S15

S_IRDY output float delay

S17

S_D[31:0] input set-up time

4.5

S18

S_D[31:0] input hold time

1.5

S19

S_MSGEN# input set-up time

4.5

S20

S_MSGEN# input hold time

1.5

S21

S_EOF# input set-up time

4.5

S22

S_EOF# input hold time

1.5

S23

S_IRDY input set-up time

4.5

S24

S_IRDY input hold time

1.5

S27

S_TABT# input set-up time

4.5

S28

S_TABT# input hold time

1.5

S29

S_HPREQ# input set-up time

4.5

S30

S_HPREQ# input hold time

1.5

S31

S_GNT# input set-up time

4.5

S32

S_GNT# input hold time

1.5

S33

S_OVLD# input set-up time

4.5

S34

S_OVLD# input hold time

1.5

AC Characteristics XpressFlow Bus Interface

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

6.2 CPU Bus Interface:

P16-min

P15

P_CLK

P_D[31:0]

CPU Bus Interface 

Output float delay timing

P16-min

P16-max

P17-min

P17-max

P18-min

P18-max

P_CLK

P_D[15:0]

P_RDY#

P_INT

CPU Bus Interface

Output valid delay timing

P11

P10

P12

P_CLK

P_RST#

P_ADS#

P_W/R#

P_CS#

P_A[11:1]

P_D[15:0]

CPU Bus Interface 

Input setup and hold timing

-33

-40

-50

Symbol

Parameter

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Note:

P_RST# input setup time

4.5

P_RST# input hold time

1.5

P_ADS# input set-up time

4.5

P_ADS# input hold time

1.5

P_W/R# input set-up time

4.5

P_W/R# input hold time

1.5

P_CS# input set-up time

4.5

P_CS# input hold time

1.5

P_A[11:1] input set-up time

4.5

P10

P_A[11:1] input hold time

1.5

P11

P_D[31:0]# input set-up time

4.5

P12

P_D[31:0]# input hold time

1.5

P15

P_D[31:0]# output float delay

P16

P_D[31:0]# # output valid delay

= 60pf

P17

P_RDY# output valid delay

= 60pf

P18

P_INT# output valid delay

= 20pf

AC Characteristics -- CPU Bus Interface

XpressFlow-2001 Series 

EA-224

Ethernet Switch Chip-set

4-Port 10/100M Ethernet Access Controller

6.3 Local Memory Interface:

L_CLK

L_D[31:0]

Local Memory Interface 

Input setup and hold timing

L3-min

L10

L_CLK

L_D[31:0]

Local Memory Interface 

Output float delay timing

L3-min

L3-max

L4-min

L4-max

L5-min

L5-max

L6-min

L6-max

L7-min

L7-max

L8-min

L8-max

L9-min

L9-max

L_CLK

L_D[31:0]

L_A[19:2]

L_CS[3:0]#

L_ADSC#

L_BWE[3:0]#

L_WE#]

L_OE#

Local Memory Interface 

Output valid delay timing

-33

-40

-50

Symbol

Parameter

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Min

(ns)

Max

(ns)

Note:

L_D[31:0]# input set-up time

4.5

L_D[31:0]# input hold time

1.5

L_D[31:0]# output valid delay

= 30pf

L_A[19:2] output valid delay

= 30pf

L_CS[3:0]# output valid delay

L_ADSC# output valid delay

= 30pf

L_BWE[3:0]# output valid delay

= 30pf

L_WE# output valid delay

= 10pf

L_OE# output valid delay

= 10pf

L10

L_D[31:0]# output float delay

AC Characteristics Local Memory Interface

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