Document Outline

• Features
• Figure 1 - 24 10/100Mbps + 2Gbps Port System Configuration
• Description
  • Figure 2 - System Block Diagram
• 1.0 Ball Signal Descriptions and Assignments
  • 1.1 Ball Signal Assignments
• 2.0 Ball-Signal Descriptions
  • CPU Bus Interface
  • Frame Buffer Interface (continued)
• 3.0 The Media Access Control (MAC) and GIGABIT (GMAC)
  • 3.1 MAC/GMAC Configuration
  • 3.2 The Inter-frame Gap
  • 3.3 Ethernet Frame Limits
  • 3.4 Collision Handling and Avoidance
  • 3.5 Auto-negotiation
  • 3.6 VLAN Support
  • 3.7 MAC Control Frames
  • 3.8 Flow Control
    • 3.8.1 Collision-Based Flow Control
    • 3.8.2 IEEE 802.3x Flow Control
      • Figure 3 - Frame with Carrier Extension and Frame Bursting
  • 3.9 Frame Bursting
• 4.0 Frame Engine Description
  • 4.1 Transmission scheduling
  • 4.2 Buffer Management
• 5.0 Frame Buffer Memory
  • 5.1 Frame Buffer Memory configuration
    • Table 1 - Type and Size of Memory Chips
    • Figure 4 - Frame Buffer Memory Configuration
  • 5.2 Frame Buffer memory usage
    • Table 2 - Frame Buffer Memory Usage for Managed Mode
    • Table 3 - Frame Buffer Memory Usage For Unmanaged Mode
    • 5.2.1 Memory Allocation of a Managed System
      • Figure 5 - Memory Map of Managed System
    • 5.2.2 Frame Data Buffers
    • 5.2.3 Transmission Queues
    • 5.2.4 Mailing List
    • 5.2.5 VLAN Table
    • 5.2.6 VLAN MAC Association Table
    • 5.2.7 Unmanaged System memory allocation
      • Figure 6 - Memory Map of an Unmanaged System
  • 5.3 The Frame Memory Interface
    • 5.3.1 Local memory interface
• 6.0 Search Engine
  • Figure 7 - Typical Packet Header Information
  • 6.1 Layer 2 Search Process
    • 6.1.1 VLAN Unaware
    • 6.1.2 VLAN Aware
  • 6.2 Address and VLAN learning
  • 6.3 Flooding and Packet Control
  • 6.4 Packet Filtering
  • 6.5 Address Aging
  • 6.6 IP Multicast
• 7.0 The High Density Instruction Set Computer (HISC)
  • 7.1 Description
  • 7.2 HISC architecture
  • 7.3 HISC Operations
    • 7.3.1 Resource Initialization
    • 7.3.2 Resource Management
    • 7.3.3 Switching Database Management
    • 7.3.4 Send and Receive Frames for Management CPU
    • 7.3.5 Communication Between HISC and Switching Hardware
    • 7.3.6 Communication Between Search Engine and HISC
    • 7.3.7 Communication Between HISC and Frame Engine
  • 7.4 Communication Between Management CPU and HISC
    • 7.4.1 CPU-HISC Communication Using Queues
    • 7.4.2 Mailbox
    • 7.4.3 CPU-HISC MAIL
    • 7.4.4 HISC-CPU Mail
• 8.0 The XPipe
  • 8.1 XPipe Connection
    • Figure 8 - XPipe System Block Diagram for the MDS213
    • Table 4 - Summary Description of the Source and Target End Signals
    • Figure 9 - XPipe Message Header
  • 8.2 XPipe Timing
    • Figure 10 - Basic Timing Diagram of XPipe
• 9.0 Physical Layer (PHY) Interface
  • 9.1 Reduced MII (RMII)
    • Table 5 - RMII Specification Signals
  • 9.2 The Gigabit Media Independent Interface (GMII)
    • 9.2.1 The MII Management Interface
    • 9.2.2 MII Command and Status Registers
  • 9.3 The Physical Coding Sublayer with Ten Bit Interface (TBI):
• 10.0 The Control Bus
  • Figure 11 - CPU Interface Configuration in Managed Mode
  • Figure 12 - Control Bus Configuration in Unmanaged Mode
  • 10.1 External CPU Support
    • 10.1.1 Power On/Reset Configuration
      • Table 6 - Bootstrapping Options
    • 10.1.2 CPU Bus Clock Interface
    • 10.1.3 Address And Data Buses
    • 10.1.4 Bus Master
    • 10.1.5 Input/Output Mapped Interface
    • 10.1.6 Interrupt Request
  • 10.2 Control Bus Cycle Waveforms
    • Figure 13 - Control Bus I/O
  • 10.3 The CPU Interface in Unmanaged Mode
    • 10.3.1 Arbiter
      • Figure 14 - Block Diagram of the Arbiter
  • 10.4 CPU Interface in managed mode
    • 10.4.1 CPU Access
      • Figure 15 - Little and Big Endian Byte Swapping Operation
      • Figure 16 - An example of byte swapping
• 11.0 The LED Interface
  • 11.1 LED interface
    • Figure 17 - LED Interface Connections
    • 11.1.1 Function Description
      • Table 7 - LED Signal Names and Descriptions
    • 11.1.2 Port Status
    • 11.1.3 LED Interface Time Diagram
      • Figure 18 - Time Diagram of LED Interface
• 12.0 Data Forwarding Protocol and Data Flow
  • 12.1 Data Forwarding Protocol
    • 12.1.1 Frame Reception
    • 12.1.2 Unicast Frame Forwarding
    • 12.1.3 Multicast Frame Forwarding
  • 12.2 Flow for Data Frame
    • 12.2.1 Unicast Data Frame to Local Device
    • 12.2.2 Unicast Data Frame to Remote Device
    • 12.2.3 Multicast Data Frame
  • 12.3 Flow for CPU Control Frame
    • 12.3.1 CPU Transmitting Unicast CPU Frame
    • 12.3.2 CPU Transmitting Multicast CPU Frame
    • 12.3.3 CPU Receiving Unicast Frame
    • 12.3.4 CPU Receiving Multicast frame
• 13.0 Port Mirroring
  • 13.1 Features
    • Figure 19 - Configuration of Mirror Port for MDS213
  • 13.2 Physical Pins
    • 13.2.1 Setting Register For Port Mirroring
      • 13.2.1.1 APMR- Port Mirroring Register
• 14.0 Virtual Local Area Networks (VLAN)
  • 14.1 Introduction
  • 14.2 VLAN Implementation
    • 14.2.1 Static Definitions of VLAN Membership
    • 14.2.2 Dynamic Learning of VLAN Membership
    • 14.2.3 Dynamic Learning of Remote VLAN
    • 14.2.4 MDS213 Data Structures For VLAN Implementation
      • Figure 20 - Data Structure Diagram
      • 14.2.4.1 VLAN ID Table
        • Figure 21 - VLAN ID Table
      • 14.2.4.2 VLAN MAC Table
        • Figure 22 - VLAN MAC Table
      • 14.2.4.3 VLAN Port Mapping Table (VMAP)
      • 14.2.4.4 Port VLAN ID (PVID) Register
• 15.0 IP Multicast
  • 15.1 Introduction
  • 15.2 IGMP and IP Multicast Filtering
  • 15.3 Implementation in MDS213
    • 15.3.1 MCT Table
      • 15.3.1.1 MCT Structure For Unicast Frame
    • 15.3.2 MCT structure for IP Multicast Packet
• 16.0 Quality of Service (QOS)
  • 16.1 Weighted Round Robin Transmission Strategy
  • 16.2 Buffer Management Functions
• 17.0 Port Trunking
  • 17.1 Unicast Packet Forwarding
    • Figure 23 - Port Mapping Table
  • 17.2 Multicast Packet Forwarding
    • 17.2.1 Select One Forwarding Port per Trunk Group
      • Figure 24 - Forwarding Port Mask Table
    • 17.2.2 Blocking Multicast Packets Back to the Source Trunk
      • Figure 25 - Multicast Packet Forwarding Example
  • 17.3 MAC Address Assignment
• 18.0 Register Definitions
  • 18.1 Register MAP
    • Table 8 - MDS212 Register Map (continued)
  • 18.2 Register definitions
    • 18.2.1 Device Configuration Register
      • 18.2.1.1 GCR - Global Control Register
        • Table 9 - Global Control Register
      • 18.2.1.2 DCR0 - Device Status Register
        • Table 10 - Device Status Register
      • 18.2.1.3 DCR1 - Signature, Revision & ID Register
      • 18.2.1.4 DCR2 - Device Configuration Register
      • 18.2.1.5 DCR3 - Interfaces Status Register
      • 18.2.1.6 MEMP - Memory Packed Register
    • 18.2.2 Interrupt Control Registers
    • 18.2.3 Buffer Memory interface register
      • 18.2.3.1 MWARS - Memory Write Address Register - Single Cycle
      • 18.2.3.2 MRARS - Memory Read Address Register - Single Cycle
      • 18.2.3.3 Address Registers For Burst Cycle
      • 18.2.3.4 Memory Read/Write Data Registers
      • 18.2.3.5 VTBP - VLAN ID Table Base Pointer
      • 18.2.3.6 MBCR - Multicast Buffer Control Register
      • 18.2.3.7 AMA - RAM Counter Block Access Register
      • 18.2.3.8 Reserve Register 1
      • 18.2.3.9 Reserve Register 2
    • 18.2.4 Frame Control Buffers Management Register
      • 18.2.4.1 FCBSL - FCB Queue
      • 18.2.4.2 FCBST - FCB QUEUE - Buffer Low Threshold
      • 18.2.4.3 BCT - (FCB) Buffer Counter Threshold
      • 18.2.4.4 BCHL - Buffer Counter Hi-low Selection
    • 18.2.5 Queue Management Register
      • 18.2.5.1 CINQ - CPU Input Queue
      • 18.2.5.2 COTQ - CPU Output Queue
    • 18.2.6 Switching Control register
      • 18.2.6.1 HPCR - HISC Processor Control Register
      • 18.2.6.2 HMCL0 - HISC Micro-code Loading Port - Low
      • 18.2.6.3 HMCL1 - HISC Micro-code Loading Port - High
      • 18.2.6.4 MS0R Micro Sequence 0 Register
      • 18.2.6.5 MS0R Micro Sequence 1 Register
      • 18.2.6.6 Flooding Control Register
      • 18.2.6.7 MCAT - MCT Aging Timer
      • 18.2.6.8 Tpmxr � Trunk Port Mapping Table Index Register
      • 18.2.6.9 TPMTD - Trunking Port Mapping Table Data Register
      • 18.2.6.10 PTR - Pacing Time Regulation
      • 18.2.6.11 MTCR - MCT Threshold & Counter Register
    • 18.2.7 Link List Management
      • 18.2.7.1 LKS - Link List Status Register
      • 18.2.7.2 AMBX - Mail Box Access Port
      • 18.2.7.3 AFML - Free Mail Box List Access Port
    • 18.2.8 Access Control Function
      • 18.2.8.1 AVTC - VLAN Type Code Register
      • 18.2.8.2 AXSC - Transmission Scheduling Control Register
      • 18.2.8.3 ATTL - Transmission Timing Control
    • 18.2.9 MII Serial Management Channel
      • 18.2.9.1 AMIIC - MII Command Register
      • 18.2.9.2 AMIIS - MII Status Register
    • 18.2.10 Flow Control Management
      • 18.2.10.1 AFCRIA - Flow Control RAM Input Address
      • 18.2.10.2 AFCRID0 - Flow Control RAM Input Data 0
      • 18.2.10.3 AFCRID1 - Flow Control RAM Input Data 1
      • 18.2.10.4 AFCR - Flow Control Register
      • 18.2.10.5 AMAR[1:0] - Multicast Address Reg. For MAC Control Frames
      • 18.2.10.6 AMCT - MAC Control Frame Type Code Register
      • 18.2.10.7 ADAR [1:0] - Base MAC Address Registers
      • 18.2.10.8 ADAOR0 - MAC Offset Address Register 0
      • 18.2.10.9 ADAOR1 - MAC Offset Address Register 1
      • 18.2.10.10 ACKTM - Timer For SOF Checking
      • 18.2.10.11 AFCHT10 - Flow Control Hold Time Of 10Mbps Port
      • 18.2.10.12 AFCHT 100 - Flow Control Hold Time Of 100Mbps Port
      • 18.2.10.13 AFCHT1000 - Flow Control Hold Time of Giga Port
      • 18.2.10.14 AFCOFT10 - Flow Control Off Time of 10Mbps PROT
      • 18.2.10.15 AFCOFT100 - Flow Control Off Time of 100Mbps PORT
      • 18.2.10.16 AFCOFT1000 - Flow Control Off Time of Giga Port
    • 18.2.11 Access Control Function Group 2 (Chip Level)
      • 18.2.11.1 APMR- PORT MIRRORING REGISTER
      • 18.2.11.2 PFR - Protocol Filtering Register
      • 18.2.11.3 THKM [0:7] - Trunking Forwarding Port Mask 0-7
      • 18.2.11.4 IPMCAS - IP Multicast MAC Address Signature
      • 18.2.11.5 IPMCMSK- IP Multicast MAC Address Mask
      • 18.2.11.6 CFCBHDL - FCB Handle Register For CPU Read
      • 18.2.11.7 CPU Access Internal RAMs (Tables)
      • 18.2.11.8 CPUIRCMD - CPU Internal RAM Command Register
      • 18.2.11.9 CPUIRDAT - CPU INTERNAL RAM DATA REGISTER
      • 18.2.11.10 CPUIRRDY - Internal Ram Read Ready For CPU
      • 18.2.11.11 LEDR- LED Register
    • 18.2.12 Ethernet MAC Port Control Registers
      • 18.2.12.1 ECR0 - ECR0 - MAC Port Control Register
      • 18.2.12.2 ECR1 - MAC Port Configuration Register
      • 18.2.12.3 ECR2 - MAC Port Interrupt Mask Register
      • 18.2.12.4 ECR3 - MAC Port Interrupt Status Register
      • 18.2.12.5 ECR4 - Port Status Counter Wrapped Signal
      • 18.2.12.6 PVID Register
• 19.0 DC Electrical Characteristics
  • 19.1 Absolute Maximum Ratings
  • 19.2 DC Electrical Characteristics
    • Recommended Operating Conditions
• 20.0 AC Specifications
  • 20.1 XPIPE Interface
    • Figure 26 - XPIPE Interface - Output Valid Delay Timing
    • Table 11 - AC Characteristics - XPipe Interface
  • 20.2 CPU BUS Interface
    • Figure 27 - AC Characteristics - CPU BUS Interface
    • Table 12 - AC Characteristics - CPU Bus Interface
  • 20.3 Local SBRAM Memory Interface
    • Figure 28 - Local Memory Interface - Input Setup and Output Valid Delay Timing
    • Table 13 - AC Characteristics - Local SBRAM Memory Interface
    • Figure 29 - Port Mirroring Interface - Input Setup and Hold Timing
    • Figure 30 - Port Mirroring Interface - Output Delay Timing
    • Figure 31 - Reduce Media Independent Interface - Input Setup and Hold Timing
    • Figure 32 - Reduce Media Independent Interface - Output Delay Timing
    • Table 14 - AC Characteristics - Port Mirroring Interface
    • Table 15 - AC Characteristics - Reduced Media Independent Interface
    • Table 16 - AC Characteristics - Gigabit Media Independent Interface
    • Figure 33 - Input Setup and Hold Timing
    • Figure 34 - Output Valid Delay Timing
    • Table 17 - AC Characteristics - Physical Media Attachment Interface
    • Figure 35 - LED Interface - Output Delay Timing
    • Table 18 - AC Characteristics - LED Interface