Document Outline

• Features
• Description
• Applications
• Switching Feature
  • Figure 2 - ATM Switch Application
  • Figure 1 - Functionl Block Diagram
• 1.0 Introduction
  • 1.1 Functional Overview of the MT90503
    • Figure 3 - Transmit Data Flow - TDM to UTOPIA
    • Figure 4 - Receive Data Flow - UTOPIA to TDM
• 2.0 Features Detailed Description
  • 2.1 UTOPIA Interface
  • 2.2 TDM Interface
  • 2.3 Clock Recovery
  • 2.4 ATM SAR
  • 2.5 Required External Components
  • 2.6 Particular Modes of Operation
  • 2.7 Miscellaneous
  • 2.8 Power
• 3.0 Pin Designations and Descriptions
  • Table 1 - CPU Bus Interface Pins
  • Table 2 - Control Memory Bus Interface Pins
  • Table 3 - Data Memory Bus Interface Pins
  • Table 4 - Data and Control Memory Clock Pins
  • Table 5 - H.100/H.110 Bus Interface Pins
  • Table 6 - Clock Recovery Pins
  • Table 7 - Test Pins
  • Table 8 - UTOPIA Interface Pins
  • Table 9 - Phase Lock Loop (PLL) Pins
  • Table 10 - Process Monitor Pins
  • Table 11 - Pin Names Listed by Location
  • Table 12 - Pinout Summary
  • Figure 5 - PLL Pin Connections
• 4.0 Functional Description
  • 4.1 CPU Interface
    • 4.1.1 CPU Interrupts
      • 4.1.1.1 Example Interrupt Flow
      • 4.1.1.2 Interrupt Initialization
      • 4.1.1.3 Interrupt Servicing
    • 4.1.2 Intel/Motorola Interface
      • Table 13 - CPU Interface Mode Selection
      • Table 14 - Control Register (0000h)
      • Table 15 - Read/Write Data Register (0004h)
      • Table 16 - Address High Register (0008h)
      • Table 17 - Address Low Register (000Ah)
      • 4.1.2.1 Extended Indirect Accessing
      • 4.1.2.2 Extended Indirect Writes
      • 4.1.2.3 Extended Indirect Reads
      • 4.1.2.4 Extended Direct Accessing
      • 4.1.2.5 Extended Direct Writes
      • 4.1.2.6 Extended Direct Reads
    • 4.1.3 MT90503 Reset Procedure
  • 4.2 TDM Module
    • 4.2.1 TDM Bus Interface
      • Figure 6 - TDM Serial to Parallel/Parallel to Serial (SPPS) Converter
      • Figure 7 - CAS and MFS Transport on the TDM Bus
    • 4.2.2 TDM Bus Clocking Mechanism
    • 4.2.3 TDM Datapath
      • Figure 8 - TDM Data Path Controller
    • 4.2.4 TDM Channel Association Structures
      • 4.2.4.1 Non CAS Operation
        • Figure 9 - TDM Channel Association Structures: TX Channel non-CAS mode
        • Figure 10 - TDM Channel Association: RX Channels (Non CAS mode)
      • 4.2.4.2 CAS Operation
        • Figure 11 - TDM Channel Association: TX Channels (CAS mode)
        • Figure 12 - TDM Channel Association: RX Channels (CAS mode)
        • Figure 13 - CAS Change Structure in Control Memory
        • Figure 14 - TX/RX Circular Buffer and Size Field
    • 4.2.5 TDM Circular Buffers
      • Figure 15 - Silent Pattern Buffer A/B in Control Memory
      • Figure 16 - TDM Circular Buffer (one MultiFrame in T1 mode)
      • Figure 17 - TDM Circular Buffer (one Super Frame in E1 mode)
    • 4.2.6 TDM Circular Buffer Pointers
      • 4.2.6.1 Non-multiframing mode
        • Figure 18 - TDM Circular Buffers (Normal mode)
      • 4.2.6.2 E1/T1 Multiframing (standard)
        • Figure 19 - TDM Circular Buffer (Complete Buffer in E1 mode, Strict Multiframing)
        • Figure 20 - TDM Circular Buffer (Complete Buffer in E1 mode, FASTCAS)
        • Figure 21 - TDM Circular Buffer (Complete Buffer in T1 mode, Strict Multiframing)
        • Figure 22 - TDM Circular Buffer (Complete Buffer in T1 mode, FASTCAS)
  • 4.3 TX_SAR Module
    • 4.3.1 Overview
      • 4.3.1.1 Support and Trunking for Different Types of ATM Cells
        • Figure 23 - ATM Cell Formats
    • 4.3.2 TX_SAR Event Schedulers
      • 4.3.2.1 Overview
      • 4.3.2.2 The Transmit Event Scheduler Process
        • Figure 24 - Transmit Event Scheduler Process
      • 4.3.2.3 Transmit Event Scheduler Fields Description
        • Table 18 - Field Description for the Transmit Event Scheduler
      • 4.3.2.4 Scheduler Events Fields Description
        • Table 19 - Scheduler Event Fields
      • 4.3.2.5 Bandwidth Limitations for Transmit Scheduler Events
        • Table 20 - Maximum number of Events per Frame for Common Transmission Speeds
        • Figure 25 - Unsyncrhonised Schedulers
        • Figure 26 - Synchronised Schedulers
        • Figure 27 - Partially Synchronised Schedulers
    • 4.3.3 Out of Bandwidth Error
      • 4.3.3.1 Percent of Bandwidth Register
      • 4.3.3.2 Distribution of Events by Software
        • Table 21 - Examples of typical Transmit Event Scheduler Sizes
    • 4.3.4 Mapping of the Transmit Event Scheduler
    • 4.3.5 TX_SAR Control Structures
      • Figure 28 - TX_SAR Event Scheduler Pointer Flow and Control Structure
      • 4.3.5.1 TX_SAR Control Structure Fields
        • Figure 29 - TX_SAR Control Structure
        • Table 22 - Description of the Fields for the TX_SAR Control Structure
    • 4.3.6 Miscellaneous TX_SAR Features
      • 4.3.6.1 T1 with CAS and E1 with CAS Cell Format Mapping
      • 4.3.6.2 Support of Partially-Filled Cells
      • 4.3.6.3 TX_SAR FIFO
  • 4.4 RX_SAR Module
    • 4.4.1 Treatment of Data Cells
    • 4.4.2 Control Structure
      • Figure 30 - RX_SAR Control Structure
      • Table 23 - Description of the Fields for the RX_SAR Structure
      • Table 24 - Payload Sizes for Various Cell Formats
    • 4.4.3 Errors
      • Table 25 - RX_SAR errors
      • Figure 31 - Overrun and Underrun Examples
    • 4.4.4 Error Report Structure
      • Figure 32 - RX_SAR Error Report Structure
      • Table 26 - Description of the Fields for the RX_SAR Error Report Structure
  • 4.5 UTOPIA Module
    • 4.5.1 Overview
      • Figure 33 - UTOPIA Module
    • 4.5.2 UTOPIA Interfaces
    • 4.5.3 Errors on received cells
    • 4.5.4 Transmit and Receive State Machines for ATM and PHY Modes
      • Figure 34 - ATM Mode State Machines
      • Figure 35 - PHY Mode State Machines
    • 4.5.5 Cell Router
      • Figure 36 - Cell Format for cells in internal UTOPIA input and output cell FIFOs
      • Figure 37 - Cell Router Flow
    • 4.5.6 Match & Mask for cell routing
      • Figure 38 - Match & Mask Example
      • 4.5.6.1 Look-Up Tables Entries
        • Figure 39 - Short and Long Look-Up Table Entries
      • 4.5.6.2 LUT Addressing
        • Figure 40 - VPI/VCI Concatenation and LUT Entry Address Example
      • 4.5.6.3 UTOPIA Clocks
    • 4.5.7 LED Operation
      • Figure 41 - UTOPIA Clock Generation
    • 4.5.8 UTOPIA Flow Control
    • 4.5.9 External Interface Signals
      • Figure 42 - External UTOPIA Interface
  • 4.6 Clock Recovery Module
    • 4.6.1 Overview
      • 4.6.1.1 Two Point Generation Modules
      • 4.6.1.2 One SRTS (synchronous residual time stamp) Generating Module
      • 4.6.1.3 Three Integer Divisor Clock Modules
      • 4.6.1.4 Two Precise Clock Modules
      • 4.6.1.5 Eleven Multiplexers
    • 4.6.2 Multiplexers
      • Table 27 - Multiplexer Registers
      • Figure 43 - Multiplexer
      • Table 28 - Source Selection
    • 4.6.3 Integer Divisor Clocks (idclk)
      • Table 29 - idclk_a Register
      • Figure 44 - Integer Clock Processor
    • 4.6.4 Precise Clocks (pclk)
      • Table 30 - pclk registers
    • 4.6.5 Point Generation
      • Table 31 - adapsrts0 Registers
      • Figure 45 - Adaptive Clock Recovery
    • 4.6.6 Adaptive Clock Recovery
      • Figure 46 - Adaptive Cell Reception Flow
      • 4.6.6.1 SRTS Clock Recovery
        • Figure 47 - Rx SRTS Clock Recovery Module
    • 4.6.7 SRTS Transmission
      • Figure 48 - Tx SRTS Clock Recovery Module
      • Table 32 - Tx SRTS Registers
    • 4.6.8 External Memory Point Format
      • Figure 49 - Clock Recovery Information Buffers
      • Table 33 - SRTS Pointer Buffer, Field Description
• 5.0 Memory
  • 5.1 Memory Overview
  • 5.2 Memory Map
    • Table 34 - MT90503 Memory Map
  • 5.3 Memory Controllers
    • 5.3.1 Data Memory
    • 5.3.2 Control Memory
    • 5.3.3 Data Memory Controller
      • Table 35 - Types of Data Memory accesses for each agent
    • 5.3.4 Control Memory Controller
      • Table 36 - Types of Control Memory Accesses For Each Agent
  • 5.4 Register Overview
  • 5.5 Detailed Register Description
    • 5.5.1 CPU Registers
      • Table 37 - CPU Control Register
      • Table 38 - CPU Status Register
      • Table 39 - CPU Interrupt Enable Register
      • Table 40 - CPU Counter Register
      • Table 41 - LED1 Register
      • Table 42 - LED2 Register
      • Table 43 - PLL Configuration Register
      • Table 44 - Intel/Motorola Address Register
      • Table 45 - Intel/Motorola Address Rise Register
      • Table 46 - Intel/Motorla Address Fall Register
      • Table 47 - Intel/Motorola Data Out Register
      • Table 48 - Intel/Motorola Data In Register
      • Table 49 - Intel/Motorola Data Rise/Fall Register
    • 5.5.2 Main Registers
      • Table 50 - Main Control Register
      • Table 51 - Main Status Register
      • Table 52 - Main Interrupt Enable Register
      • Table 53 - Main Counter Register
      • Table 54 - Interrupt Flags Register
      • Table 55 - Interrupt1 Configuration Register
      • Table 56 - Interrupt2 Configuration Register
      • Table 57 - Interrupt1 Enable Register
      • Table 58 - Interrupt2 Enable Register
      • Table 59 - Utopia Clock Register
      • Table 60 - Utopia Clock Generation A Register
      • Table 61 - Utopia Clock Generation B Register
      • Table 62 - Utopia Clock Generation C Register
      • Table 63 - Control Memory Parity0 Register
      • Table 64 - Control Memory Parity1 Register
      • Table 65 - Control Memory Configuration Register
      • Table 66 - Data Memory Parity 0 Register
      • Table 67 - Data Memory Parity 1 Register
      • Table 68 - Data Memory Configuration Register
    • 5.5.3 UTOPIA Registers
      • Table 69 - Utopia Control Register
      • Table 70 - Utopia Control1 Register
      • Table 71 - Utopia Status 0 Register
      • Table 72 - Utopia Status 2 Register
      • Table 73 - Utopia Interrupt Enable 2 Register
      • Table 74 - Utopia Counters Register
      • Table 75 - Cell Loss Counters Register
      • Table 76 - Port A Look Up Table Address Register
      • Table 77 - Port A VPI/VCI Identification Register
      • Table 78 - Port A Concatenation Register
      • Table 79 - Port A VPI Match Register
      • Table 80 - Port A VCI Mask Register
      • Table 81 - Port A VCI Match Register
      • Table 82 - Port A VCI Mask Register
      • Table 83 - Port A Cell Arrival Counter High Register
      • Table 84 - Port A Cell Arrival Counter Low Register
      • Table 85 - Port A Cell Departure Counter High Register
      • Table 86 - Port A Cell Departure Low Register
      • Table 87 - Port A Overflow0 Register
      • Table 88 - Port A Overflow1 Register
      • Table 89 - Port A Address Register
      • Table 90 - Port B Look Up Table Register
      • Table 91 - Port B VPI/VCI Identification Register
      • Table 92 - Port B Concatenation Register
      • Table 93 - Port B VPI Match Register
      • Table 94 - Port B VPI Mask Register
      • Table 95 - Port B VCI Match Register
      • Table 96 - Port B VCI Mask Register
      • Table 97 - Port B Cell Arrival Counter High Register
      • Table 98 - Port B Cell Arrival Counter Low Register
      • Table 99 - Port B Cell Departure Counter High Register
      • Table 100 - Port B Cell Departure Counter Low Register
      • Table 101 - Port B Overflow0 Register
      • Table 102 - Port B Overflow1 Register
      • Table 103 - Port C Look Up Table Register
      • Table 104 - Port C VPI/VCI Identification Register
      • Table 105 - Port C Concatenation Register
      • Table 106 - Port C VPI Match Register
      • Table 107 - Port C VPI Mask Register
      • Table 108 - Port C VCI Match Register
      • Table 109 - Port C VCI Match Register
      • Table 110 - Port C Cell Arrival Counter High Register
      • Table 111 - Port C Cell Arrival Counter Low Register
      • Table 112 - Port C Cell Departure Counter High Register
      • Table 113 - Port C Cell Departure Counter Low Register
      • Table 114 - Port C Overflow0 Register
      • Table 115 - Port C Overflow1 Register
      • Table 116 - TX_SAR Cell Arrival Counter High Register
      • Table 117 - TX_SAR Cell Arrival Counter Low Register
      • Table 118 - RX_SAR Cell Departure Counter High Register
      • Table 119 - RX_SAR Cell Departure Counter Low Register
      • Table 120 - TX_SAR Overflow0 Register
      • Table 121 - TX_SAR Overflow1 Register
      • Table 122 - HEC Byte Control Register
      • Table 123 - Unknown Header Routing Register
      • Table 124 - Unknown OAM Routing Register
      • Table 125 - GPIO Input0 Register
      • Table 126 - GPIO Input1 Register
      • Table 127 - GPIO Input2 Register
      • Table 128 - TXA Data Status Register
      • Table 129 - TXA Data Interrupt Enable Register
      • Table 130 - RXA Data Status Register
      • Table 131 - RXA Data Interrupt Enable Register
      • Table 132 - TXB Data Status Register
      • Table 133 - TXB Data Interrupt Enable Register
      • Table 134 - RXB Data Status Register
      • Table 135 - RXB Data Interrupt Enable Register
      • Table 136 - GPIO Status Register
      • Table 137 - GPIO Status Register
      • Table 138 - GPIO Output0 Register
      • Table 139 - GPIO Output1 Register
      • Table 140 - GPIO Output2 Register
      • Table 141 - GPIO Output Enable0 Register
      • Table 142 - GPIO Output Enable1 Register
      • Table 143 - GPIO Output Enable2 Register
    • 5.5.4 TDM Registers
      • Table 144 - TDM Control Register
      • Table 145 - TDM Status Register
      • Table 146 - Cut VC TSST Register
      • Table 147 - TSST Underrun Register
      • Table 148 - TSST CAS Underrun Register
      • Table 149 - TDM Interrupt 0 Register
      • Table 150 - TDM Interrupt 1 Register
      • Table 151 - TDM Interrupt Enable Misc. Register
      • Table 152 - TDM Write Pointer 0 Register
      • Table 153 - TDM Write Pointer 1 Register
      • Table 154 - TDM Read Pointer Register
    • 5.5.5 TX_SAR Registers
      • Table 155 - TX_SAR Control Register
      • Table 156 - TX_SAR Status Register
      • Table 157 - TX_SAR Interrupt Enable Register
      • Table 158 - TX_SAR Control 1 Register
      • Table 159 - TX_SAR Data Read Pointer Register
      • Table 160 - TX_SAR Data Write Pointer Register
      • Table 161 - TX_SAR Data Address Register
      • Table 162 - TX_SAR Data Cell Size Register
      • Table 163 - Percent of Bandwidth Register
    • 5.5.6 Scheduler Registers
      • Table 164 - Scheduler Test Status Register
      • Table 165 - Scheduler Status Register
      • Table 166 - Scheduler Interrupt Enable Register
      • Table 167 - Frame Latency Register
      • Table 168 - Scheduler Configuration & Enable 0 Register
      • Table 169 - Scheduler Configuration & Enable 1 Register
      • Table 170 - Scheduler Configuration & Enable 2 Register
      • Table 171 - Scheduler Configuration & Enable 3 Register
    • 5.5.7 RX_SAR Registers
      • Table 172 - RX_SAR Control Register
      • Table 173 - RX_SAR Status Register
      • Table 174 - RX_SAR Interrupt Enable Register
      • Table 175 - RX_SAR Data Read Pointer Register
      • Table 176 - RX_SAR Data Write Pointer Register
      • Table 177 - RX_SAR Data Address Register
      • Table 178 - RX_SAR Data Cell Size Register
      • Table 179 - Error Structure Read Register
      • Table 180 - Error Structure Write Register
      • Table 181 - Error Structure Address High Register
      • Table 182 - Error Structure Address Low Register
      • Table 183 - Error Structure Size Register
      • Table 184 - AAL0 Timeout High Register
      • Table 185 - AAL0 Timeout Low Register
      • Table 186 - Error Timeout High Register
      • Table 187 - Error Timeout Low Register
      • Table 188 - Treated Pulses Register
    • 5.5.8 Clock Registers
      • Table 189 - Clock Control Register
      • Table 190 - Clock Status Register
      • Table 191 - Status Interrupt Enable Register
      • Table 192 - MCLK Alarm 0 Register
      • Table 193 - MCLK Counter High Register
      • Table 194 - MCLK Counter Low Register
      • Table 195 - MCLK Alarm 1 Register
      • Table 196 - MCLK Alarm 2 Register
      • Table 197 - TX_SRTS 0 Register
      • Table 198 - TX_SRTS 1 Register
      • Table 199 - TX_SRTS 2 Register
      • Table 200 - TX_SRTS 4 Register
      • Table 201 - TX_SRTS 5 Register
      • Table 202 - Adaptive SRTS0 0 Register
      • Table 203 - Adaptive SRTS0 1 Register
      • Table 204 - Adaptive SRTS0 2 Register
      • Table 205 - Adaptive SRTS0 3 Register
      • Table 206 - Adaptive SRTS0 4 Register
      • Table 207 - Adaptive SRTS0 5 Register
      • Table 208 - Adaptive SRTS0 6 Register
      • Table 209 - Adaptive SRTS0 7 Register
      • Table 210 - Adaptive SRTS0 8 Register
      • Table 211 - Adaptive SRTS0 9 Register
      • Table 212 - Adaptive SRTS1 0 Register
      • Table 213 - Adaptive SRTS1 1Register
      • Table 214 - Adaptive SRTS1 2 Register
      • Table 215 - Adaptive SRTS1 3 Register
      • Table 216 - Adaptive SRTS1 4 Register
      • Table 217 - Adaptive SRTS1 5 Register
      • Table 218 - Adaptive SRTS1 6 Register
      • Table 219 - Adaptive SRTS1 7 Register
      • Table 220 - Adaptive SRTS1 8 Register
      • Table 221 - Adaptive SRTS1 9 Register
      • Table 222 - Pin Mux 0 Register
      • Table 223 - Pin Mux 1 Register
      • Table 224 - Pin Mux 2 Register
      • Table 225 - Pin Mux 3 Register
      • Table 226 - Pin Mux 4 Register
      • Table 227 - Pin Mux 5 Register
      • Table 228 - Integer Clock Divisor0 0 Register
      • Table 229 - Integer Clock Divisor0 1 Register
      • Table 230 - Integer Clock Divisor0 2 Register
      • Table 231 - Integer Clock Divisor0 3 Register
      • Table 232 - Integer Clock Divisor0 4 Register
      • Table 233 - Integer Clock Divisor0 5 Register
      • Table 234 - Integer Clock Divisor0 8 Register
      • Table 235 - Integer Clock Divisor0 9 Register
      • Table 236 - Integer Clock Divisor0 10 Register
      • Table 237 - Integer Clock Divisor1 0 Register
      • Table 238 - Integer Clock Divisor1 1 Register
      • Table 239 - Integer Clock Divisor1 2 Register
      • Table 240 - Integer Clock Divisor1 3 Register
      • Table 241 - Integer Clock Divisor1 4 Register
      • Table 242 - Integer Clock Divisor1 5 Register
      • Table 243 - Integer Clock Divisor1 8 Register
      • Table 244 - Integer Clock Divisor1 9 Register
      • Table 245 - Integer Clock Divisor1 10 Register
      • Table 246 - Integer Clock Divisor2 0 Register
      • Table 247 - Integer Clock Divisor2 1 Register
      • Table 248 - Integer Clock Divisor2 2 Register
      • Table 249 - Integer Clock Divisor2 3 Register
      • Table 250 - Integer Clock Divisor2 4 Register
      • Table 251 - Integer Clock Divisor2 5 Register
      • Table 252 - Integer Clock Divisor2 8 Register
      • Table 253 - Integer Clock Divisor2 9 Register
      • Table 254 - Integer Clock Divisor2 10 Register
      • Table 255 - TX SRTS Debug Register
      • Table 256 - RX SRTS Debug 0 Register
      • Table 257 - RX SRTS Debug 1 Register
      • Table 258 - AAL1 Error Debug Register
    • 5.5.9 Miscellaneous Registers
      • Table 259 - Miscellaneous Control Register
      • Table 260 - Miscellaneous Error Register
      • Table 261 - Silent Tone 2 Register
      • Table 262 - Silent Tone 3 Register
      • Table 263 - Silent Tone 4 Register
      • Table 264 - Adaptive Point/SRTS Value 0 Register
      • Table 265 - Adaptive Point/SRTS Base Address Low 0 Register
      • Table 266 - Adaptive Point/SRTS Base Address High 0 Register
      • Table 267 - Adaptive Point/SRTS Write Pointer 0 Register
      • Table 268 - Adaptive Point/SRTS Read Pointer 0 Register
      • Table 269 - Local SRTS Write Pointer 0 Register
      • Table 270 - Local SRTS Read Pointer 0 Register
      • Table 271 - Adaptive Point/SRTS Value 1 Register
      • Table 272 - Adaptive Point/SRTS Base Address Low 1 Register
      • Table 273 - Adaptive Point/SRTS Base Address High 1 Register
      • Table 274 - Adaptive Point/SRTS Write Pointer 1 Register
      • Table 275 - Adaptive Point/SRTS Read Pointer 1 Register
      • Table 276 - Local SRTS Write Pointer 1 Register
      • Table 277 - Local SRTS Read Pointer 1 Register
      • Table 278 - CAS Change Buffer Size Register
      • Table 279 - CAS Change Buffer Base Address Low Register
      • Table 280 - CAS Change Buffer Base Address High Register
      • Table 281 - CAS Write Pointer Register
      • Table 282 - CAS Read Pointer Register
      • Table 283 - CAS Timeout High Register
      • Table 284 - CAS Timeout Low Register
      • Table 285 - Treated Pulses Register
    • 5.5.10 H.100 Registers
      • Table 286 - H.100 Control 0 Register
      • Table 287 - H.100 Control 1 Register
      • Table 288 - H.100 Control 2 Register
      • Table 289 - H.100 Flags Register
      • Table 290 - H.100 Status Register
      • Table 291 - H.100 Interrupt Enable Register
• 6.0 Statistics
  • 6.1 TDM statistics
  • 6.2 TX SAR statistics
  • 6.3 RX SAR statistics
  • 6.4 UTOPIA statistics
• 7.0 Programming the fast_clk PLL
  • Figure 50 - mem_clk Output and fast_clk Generation Circuits
  • Figure 51 - mem_clk Input and mclk Generation Circuit
  • Table 292 - Register 0128h Frequency Values
  • Table 293 - Z Divisor Table
• 8.0 Electrical Specifications
  • 8.1 DC Characteristics
    • 8.1.1 Precautions During Power Sequencing
    • 8.1.2 Precautions During Power Failure
    • 8.1.3 Pull-ups
  • 8.2 H.110 Diode Clamp Rail
  • 8.3 AC Characteristics
    • Table 294 - Clock Networks
    • Table 295 - MCLK - Master Clock Input Parameters
• 9.0 Interface Timing
  • 9.1 CPU Interface Timing
    • Figure 52 - Non-multiplexed CPU Write Access - Intel Mode
    • Figure 53 - Non-multiplexed CPU Read Access - Intel Mode
    • Table 296 - Non-multiplexed CPU Interface Intel Mode
    • Figure 54 - Multiplexed CPU Write Access - Intel Mode
    • Figure 55 - Multiplexed CPU Read Access - Intel Mode
    • Table 297 - Multiplexed CPU Interface Intel Mode
    • Figure 56 - Non-Multiplexed CPU Interface Write Access - Motorola Mode
    • Figure 57 - Non-multiplexed CPU Interface Read Access - Motorola Mode
    • Table 298 - Non-multiplexed CPU Interface Motorola Mode
    • Figure 58 - Multiplexed CPU Interface Write Access - Motorola Mode
    • Figure 59 - Multiplexed CPU Interface Read Access - Motorola Mode
    • Table 299 - Multiplexed CPU Interface Motorola Mode
    • Table 300 - t5 Read Access Time
  • 9.2 UTOPIA Interface Timing
    • Figure 60 - UTOPIA Timing
    • Table 301 - UTOPIA Bus Timing
  • 9.3 External Memory Timing
    • Figure 61 - Flowthrough ZBT External Memory Timing - Write Access
    • Figure 62 - Flowthrough ZBT External Memory Timing - Read Access
    • Figure 63 - Flowthrough SSRAM External Memory Timing - Write Access
    • Figure 64 - Flowthrough SSRAM External Memory Timing - Read Access
    • Figure 65 - Late-write External Memory Timing - Write Access
    • Figure 66 - Late-write External Memory Timing - Read Access
    • Figure 67 - Pipelined ZBT External Memory Timing - Write Access
    • Figure 68 - Pipelined ZBT External Memory Timing - Read Access
    • Figure 69 - Pipelined External Memory Timing - Write Access
    • Figure 70 - Pipelined External Memory Timing - Read Access
    • Table 302 - Memory Interface Timing
  • 9.4 H.100/H.110 Interface Timing
    • Figure 71 - H.100 Input, Output, and Frame Sampling
    • Figure 72 - H.100 Message Channel Clock, Transmission Delay, and Reception Delay
    • Figure 73 - H.100 Clock Skew (when chip is Master)
    • Table 303 - H.100/H.110 Interface Timing
  • 9.5 H.100/H.110 Clocking Signals
    • Figure 74 - H.100/H.110 Clocking Signals
    • Figure 75 - TDM Bus Timing - Compatibility Clock Generation
    • Figure 76 - TDM Data Bus Timings
    • Table 304 - H.100/H.110 Clocking Signals
• 10.0 Glossary of Terms