Document Outline

• Features
• Applications
• Description
  • Figure 2 - PLCC and MQFP Pin Connections
  • Figure 3 - PBGA and LQFP Pin Connections
  • Pin Description
• Device Overview
• Functional Description
  • Data and Connection Memory
  • Connection and Message Modes
  • Serial Data Interface Timing
  • Wide Frame Pulse (WFP) Frame Alignment Timing
• Switching Configurations
  • Table 1 - Switching Configuration
  • Input Frame Offset Selection
  • Serial Input Frame Alignment Evaluation
  • Memory Block Programming
  • Loopback Control
• Delay Through the MT90823
  • Variable Delay Mode (V/C bit = 0)
  • Constant Delay Mode (V/C bit = 1)
• Microprocessor Interface
  • Table 2 - Variable Throughput Delay Value
  • Table 3 - Constant Throughput Delay Value
  • Memory Mapping
  • Connection Memory Control
    • Table 4 - Internal Register and Address Memory Mapping
    • Table 5 - Output High Impedance Control
• Initialization of the MT90823
  • Table 6 - Control (CR) Register Bits
  • Table 7 - Valid Address lines for Different Bit Rates
  • Table 8 - Interface Mode Selection (IMS) Register Bits
  • Table 9 - Serial Data Rate Selection (16 input x 16 output)
  • Table 10 - Frame Alignment (FAR) Register Bits
  • Figure 4 - Example for Frame Alignment Measurement
  • Table 11 - Frame Input Offset (FOR) Register Bits
  • Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) and Frame Delay Bits (FD11, FD2-0)
  • Figure 5 - Examples for Input Offset Delay Timing
  • Table 13 - Connection Memory Bits
• JTAG Support
  • Test Access Port (TAP)
  • Instruction Register
  • Test Data Register
    • Table 14 - Boundary Scan Register Bits
• Applications
  • Switch Matrix Architectures
  • Serial Input Frame Alignment Evaluation
    • Figure 6 - Switch Matrix with Serial Stream at Various Bit Rates
    • Figure 7 - Serial Input Frame Alignment Evaluation for Various Frame Pulses
  • Wide Frame Pulse (WFP) Frame Alignment Mode
  • Digital Access Cross-Connect System
    • Figure 8 - 256 E1/T1 Digital Access Cross-Connect System (DACS)
    • Figure 9 - 8,192 x 8,192 Channel Switch Matrix
    • Figure 10 - Trunk Card Block Diagram
    • Absolute Maximum Ratings*
    • Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise sta...
    • DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated.
    • AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
    • AC Electrical Characteristics - Frame Pulse and CLK
    • AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes
    • Figure 11 - ST-BUS Timing for 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 M...
    • Figure 12 - GCI Timing at 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s,...
    • Figure 13 - WFP Bus Timing for High Speed Serial Interface (8.192Mb/s), when WFPS pin = 1
    • Figure 14 - Serial Output and External Control
    • Figure 15 - Output Driver Enable (ODE)
    • AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1)
    • Figure 16 - Multiplexed Bus Timing (Mode 1)
    • AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2)
    • Figure 17 - Multiplexed Bus Timing (Mode2)
    • AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
    • Figure 18 - Motorola Non-Multiplexed Bus Timing
    • Figure 1 - Functional Block Diagram