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Электронный компонент: MT90882BBP1N

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1
Features
WAN interface, consisting of 32 input and output
streams at 2.048 or 8.192 Mbit/s
Up to 1024 bi-directional 64 Kbit/s channels
N * 64 Kbit/s trunking of channels across any
stream and channel
1K by 1K non-blocking TDM switch
Local TDM interface, with 32 streams at 2.048,
4.096 and 8.192 Mbit/s
Flexible, multi-protocol packet encapsulation
Dual 100Mbit/s MII interfaces for redundancy or
for load balancing
Quality of service features, including weighted
fair queuing, strict priority and queue size limit
thresholds
High performance 33MHz / 66MHz 32 bit PCI
bus
Integral Stratum 4E PLL for synchronisation to
the TDM domain
Power consumption of less than 0.75 W
Applications
Packet backplane interconnection
Circuit Emulation over packet domain
Internet Off-load
Remote Access Concentrators
H.100/H.110 extension and expansion
Description
The MT9088x is a family of highly functional TDM to
Packet bridging devices. It provides a bridge between
a WAN environment based on constant bit rate TDM
streams and a packet domain based on Ethernet tech-
nology.
It is capable of assembling user-defined packets of
TDM traffic from the WAN Access Interface and trans-
mitting them from the Ethernet interfaces using a vari-
ety of protocols. If external processing is required (e.g.
HDLC or modem termination) the traffic can be
switched to a local interface using the internal TDM
switch.
June 2003
Ordering Information
MT90880B/IG/BP1N
456 ball PBGA
MT90881A/IG/BP1N
456 ball PBGA
MT90882B/IG/BP1N
456 ball PBGA
MT90883A/IG/BP1N
456 ball PBGA
-40 to 85
0
C
MT90880/1/2/3
TDM to Packet Processors
Data Sheet
Figure 1 - MT90880 High Level Overview
Dual Packet
Interface
MAC
3
2
ST
-
B
us

TD
M
po
rts
(1
02
4 bi
-d
i
r
ect
i
on
a
l

chann
e
l
s)
Dua
l
Re
d
und
an
t
10
0 M
b
it/s
MII I
n
te
rf
ac
e
s
Local TDM Interface
e.g. for connection to local resource pool
TDM Re-
Formatter
Packetizing
and Circuit
Emulation
WAN Access
Interface
Packet Switch
Fabric Interface
1Kx1K TDM
Switch
Administration
Host Control/Data Interface
32 bit, 33MHz / 66MHz 32 PCI
PCI Interface
Memory Manager
Packet Memory
0.125 - 8 MBytes SSRAM
MT90880/1/2/3
Data Sheet
2
Packets received from the Ethernet interfaces are parsed to determine the egress destination, and are
appropriately queued either to the WAN Access Interface or to the PCI interface. An integrated DMA controller is
used to transfer packets to and from the PCI interface with a minimum of CPU intervention.
Variants
There are four device variants in the MT9088x family:
MT90880
1024 bi-directional channels, integral TDM switch
MT90881
1024 bi-directional channels, no TDM switch
MT90882
256 bi-directional channels, integral TDM switch
MT90883
256 bi-directional channels, no TDM switch
Table 1 - Variant Options
Related Documents
This data sheet should be read in conjunction with the following related documents and application notes:
Table 2 - Related Documents
Feature
MT90880
MT90881
MT90882
MT90883
No. of WAN streams
32
32
8
8
Local Port
Yes
No
Yes
No
No. of Available Channels
1024
1024
256
256
TDM Switch Availability
Master mode only
Not Available
Master mode only
Not Available
PCI Interface
33 / 66MHz
33 / 66MHz
33 / 66MHz
33 / 66MHz
MII Interface
Yes
Yes
Yes
Yes
RMII Interface
Yes
Yes
Yes
Yes
JTAG
Yes
Yes
Yes
Yes
Title
Author
Document
Number
Issue / Date
1. MT9088x Programmers Model
Zarlink
DM5708
1.0, Aug. 2002
2. MT9088x API User Guide
Zarlink
DM5805
1.0, Sept. 2002
3. MSAN-198 - Performing Clock Recovery for Circuit
Emulation when using the MT90880
Zarlink
AN5789
1, Aug. 2002
4. MSAN-199 - Unstructured Circuit Emulation Using the
MT90880
Zarlink
AN5790
1, Aug. 2002
5. MSAN-200 - MT90880 TDM Replacement Packet
Backplane
Zarlink
AN5791
1, Aug. 2002.
Data Sheet
MT90880/1/2/3
3
The following external documents and standards are referenced in this data sheet:
Table 3 - Referenced Documents
Title
Author
Document
Number
Issue / Date
1. Local and Metropolitan Area Networks, Part 3: Carrier
sense multiple access with collision detection
(CSMA/CD) access method and physical layer specifi-
cations
IEEE
IEEE 802.3u
1995
2.
PCI Local Bus Specification
PCI SIG
2.2
3.
RMII
TM
Specification
RMII
consortium
Rev 1.2,
March 1998
4.
Test Access Port and Boundary Scan Architecture
IEEE
IEEE 1149.1
1990
5.
Circuit Emulation Service Interoperability Specification
ATM Forum
af-vtoa-0078
Ver 2.0, Jan. 1997
6. Specifications of (DBCES) Dynamic Bandwidth Utiliza-
tion - in 64KBPS Time Slot Trunking over ATM - Using
CES
ATM Forum
af-vtoa-0085
July 1997
7.
ST-BUS Generic Device Specification
Mitel
MSAN-126
Rev. B, June 1995
8.
H.110 Hardware Compatibility Specification: CT Bus
ECTF
Rev. 1.0, 1997
9.
H-MVIP Standard
GO-MVIP
Rel. 1.1a, Jan. '97
10.
Clocks for the Synchronized Network: Common Generic Cri-
teria
Telcordia
GR-1244-
CORE
Iss. 2, Dec. 2000
11. The Control of Jitter and Wander within digital networks
which are based on the 2048 Kbit/s hierarchy
ITU-T
G.823
2000
12. The Control of Jitter and Wander within digital networks
which are based on the 1544 Kbit/s hierarchy
ITU-T
G.824
2000
MT90880/1/2/3
Data Sheet
4
Data Sheet
MT90880/1/2/3
i
Table of Contents
1.0 Typical Applications ........................................................................................................... 3
1.1 Packet Backplane Interconnection ............................................................................................................... 3
1.2 Circuit Emulation Services ........................................................................................................................... 4
1.3 Internet Off-load ........................................................................................................................................... 4
1.4 Remote Access Concentration..................................................................................................................... 4
1.5 Local Resource Pool Example ..................................................................................................................... 6
1.6 H.100/H.110 Extension ................................................................................................................................ 6
1.7 H.100/H.110 Expansion ............................................................................................................................... 7
2.0 Functional Operation .......................................................................................................... 8
2.1 Overview ...................................................................................................................................................... 8
2.2 Basic Operation............................................................................................................................................ 9
2.2.1 WAN Access Interface ........................................................................................................................ 9
2.2.2 TDM Packet Assembly........................................................................................................................ 9
2.2.3 Packet Transmission......................................................................................................................... 10
2.2.4 CPU Packet Generation.................................................................................................................... 10
2.2.5 Packet Reception.............................................................................................................................. 10
2.2.6 Call Setup and Control...................................................................................................................... 10
2.3 Data and Control Flows.............................................................................................................................. 11
2.4 Packet Assembly........................................................................................................................................ 17
2.4.1 Payload Order................................................................................................................................... 17
2.4.2 Packet Structure ............................................................................................................................... 17
2.4.3 Context Descriptor Protocol .............................................................................................................. 18
2.5 Context Negotiation and Establishment ..................................................................................................... 19
2.5.1 Overview ........................................................................................................................................... 19
2.5.2 New Context Establishment.............................................................................................................. 19
2.5.3 Context Modification (Addition or deletion of physical channels)...................................................... 20
2.5.4 Context Removal .............................................................................................................................. 21
2.5.5 Context Cleardown ........................................................................................................................... 21
3.0 Functional Block Descriptions ........................................................................................ 22
3.1 WAN Interface and Multiplexers................................................................................................................. 22
3.1.1 Port Data Formats............................................................................................................................. 22
3.1.2 Operational Modes............................................................................................................................ 22
3.2 TDM Cross-Connect Switch ....................................................................................................................... 27
3.2.1 Multiplexing and blocking.................................................................................................................. 28
3.2.2 Re-ordering timeslots........................................................................................................................ 28
3.2.3 Channel Broadcast ........................................................................................................................... 29
3.3 WAN Receive and Transmit Functions ...................................................................................................... 29
3.4 Operation of the WAN Receive Block ........................................................................................................ 30
3.4.1 Context Control in the WAN Receive/Transmit Controllers .............................................................. 30
3.4.2 Jitter buffer operation ........................................................................................................................ 32
3.5 Queue Manager ......................................................................................................................................... 34
3.5.1 Queues to the Packet Interface ........................................................................................................ 34
3.5.2 Queues to PCI Interface ................................................................................................................... 36
3.5.3 Queues to WAN Interface ................................................................................................................. 36
3.6 Packet Transmit ......................................................................................................................................... 37
3.6.1 Protocol Stacks ................................................................................................................................. 37
3.6.2 Shadow Headers .............................................................................................................................. 37
3.7 Ethernet MAC............................................................................................................................................. 37
3.8 Packet Classification .................................................................................................................................. 38
3.8.1 Example Classification Scheme........................................................................................................ 40
3.9 Memory Management Unit ......................................................................................................................... 44
3.9.1 External Memory Requirements ....................................................................................................... 45